IDT6116LA45SOG [IDT]
Standard SRAM, 2KX8, 45ns, CMOS, PDSO24, 0.300 INCH, SOIC-24;
| 型号： | IDT6116LA45SOG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 2KX8, 45ns, CMOS, PDSO24, 0.300 INCH, SOIC-24 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
16K (2K x 8-Bit)
IDT6116SA
IDT6116LA
Features
Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-performance,
high-reliabilityCMOStechnology.
◆
High-speed access and chip select times
– Military:20/25/35/45/55/70/90/120/150ns(max.)
– Industrial:20/25/35/45ns(max.)
– Commercial:15/20/25/35/45ns(max.)
Low-power consumption
Battery backup operation
– 2V data retention voltage (LA version only)
Produced with advanced CMOS high-performance
technology
CMOS process virtually eliminates alpha particle soft-error consumesonly1µWto4µWoperatingoffa2Vbattery.
Access times as fastas 15ns are available. The circuitalsooffers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby power mode, as long
as CS remains HIGH. This capability provides significant system level
power and cooling savings. The low-power (LA) version also offers a
battery backup data retention capability where the circuit typically
◆
◆
◆
◆
rates
AllinputsandoutputsoftheIDT6116SA/LAareTTL-compatible.Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
foroperation.
TheIDT6116SA/LAispackagedin24-pin600and300milplasticor
ceramicDIP,24-leadgull-wingSOIC,and24-leadJ-bendSOJproviding
highboard-levelpackingdensities.
◆
◆
◆
Input and output directly TTL-compatible
Static operation: no clocks or refresh required
Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,
24-pin SOIC and 24-pin SOJ
◆
Military product compliant to MIL-STD-833, Class B
Military grade product is manufactured in compliance to the latest
version of MIL-STD-883, Class B, making it ideally suited to military
temperatureapplicationsdemandingthehighestlevelofperformanceand
reliability.
FunctionalBlockDiagram
A 0
CC
V
128 X 128
MEMORY
ARRAY
ADDRESS
DECODER
GND
A 10
I/O 0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7
,
CS
CONTROL
CIRCUIT
OE
WE
3089 drw 01
FEBRUARY 2001
1
©2000IntegratedDeviceTechnology,Inc.
DSC-3089/03
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
PinConfigurations
Capacitance (TA = +25°C, f = 1.0 MHZ)
Symbol
Parameter(1 )
Input Capacitance
I/O Capacitance
Conditions
Max.
Unit
7
CC
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
V
A
A
CIN
VIN = 0V
8
pF
6
5
4
8
9
CI/O
VOUT = 0V
8
pF
P24-2
P24-1
D24-2
D24-1
SO24-2
SO24-4
WE
OE
A10
CS
3089 tbl 03
3
2
1
0
0
1
2
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
7
I/O
I/O6
I/O
I/O
I/O
5
I/O
10
11
12
15
14
13
I/O4
3
GND
,
I/O
AbsoluteMaximumRatings(1)
3089 drw 02
Symbol
Rating
Com'l.
Mil.
Unit
DIP/SOIC/SOJ
Top View
(2 )
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Operating
0 to +70
-55 to +125
-65 to +135
oC
oC
TA
Temperature
PinDescription
Temperature
Under Bias
-55 to +125
TBIAS
Name
A0 - A10
I/O0 - I/O7
Description
TSTG
PT
Storage Temperature -55 to +125
-65 to +150
oC
W
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power
Power Dissipation
DC Output Current
1.0
50
1.0
50
CS
WE
OE
IOUT
mA
3089 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
VCC
GND
Ground
3089 tbl 01
2. VTERM must not exceed VCC +0.5V.
TruthTable(1)
CS
H
L
OE
X
L
WE
X
Mode
I/O
Standby
Read
High-Z
DATAOUT
High-Z
H
Read
L
H
X
H
Write
L
L
DATAIN
3089 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't Care.
2
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Ambient
RecommendedDC
OperatingConditions
Symbol
Parameter
Min.
Typ.
5.0
0
Max.
Unit
V
Grade
Temperature
-55OC to +125OC
-45OC to +85OC
0OC to +70OC
GND
Vcc
(2 )
VCC
Supply Voltage
4.5
5.5
Military
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
GND Ground
0
0
V
Industrial
0V
V
Input High Voltage
Input Low Voltage
2.2
3.5
V
CC +0.5
V
IH
Commercial
0V
-0.5(1 )
0.8
V
____
VIL
3089 tbl 05
3089 tbl 06
NOTES:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
2. VIN must not exceed VCC +0.5V.
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT6116SA
IDT6116LA
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
____
____
____
____
Input Leakage Current
|ILI|
VCC = Max.,
IN = GND to V
MIL.
COM'L.
10
5
5
2
µA
V
CC
____
____
____
____
|ILO|
Output Leakage Current
VCC = Max., CS = VIH,
MIL.
COM'L.
10
5
5
2
µA
V
VOUT = GND to VCC
____
____
V
OL
Output Low Voltage
Output High Voltage
IOL = 8mA, VCC = Min.
IOH = -4mA, VCC = Min.
0.4
0.4
____
____
VOH
2.4
2.4
V
3089 tbl 07
DCElectricalCharacteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
6116SA15
Com'l
Only
Com'l
Com'l
Com'l.
& Ind
105
95
& Ind
Symbol
Parameter
Power
SA
Mil
130
120
150
140
Mil
90
& Ind.
Mil
90
Unit
I
Operating Power Supply Current
CS < VIL, Outputs Open
VCC = Max., f = 0
mA
CC1
105
95
80
80
LA
75
85
75
85
I
Dynamic Operating Current
mA
mA
CC2
SA
150
140
130
120
120
110
135
125
100
95
115
105
CS < VIL, Outputs Open
(2 )
LA
VCC = Max., f = fMAX
I
SB
Standby Power Supply Current
(TTL Level)
SA
LA
SA
LA
40
35
2
40
35
2
50
45
10
0.9
40
35
2
45
40
10
0.9
25
25
2
35
30
CS > VIH, Outputs Open
(2 )
VCC = Max., f = fMAX
ISB1
Full Standby Power Supply Current
(CMOS Level)
CS > VHC, VCC = Max.,
VIN < VLC or VIN > VHC, f = 0
mA
10
0.1
0.1
0.1
0.1
0.9
3089 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs are cycling at fMAX, f = 0 means address inputs are not changing.
6.42
3
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DCElectricalCharacteristics(1)(continued)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
6116SA45
6116LA45
6116SA55
6116LA55
6116SA70
6116LA70
6116SA90
6116LA90
6116SA120
6116LA120
6116SA150
6116LA150
Com'l
& Ind
Symbol
Parameter
Power
Mil
Mil Only
Mil Only
Mil Only
Mil Only
Mil Only
Unit
I
Operating Power Supply
Current, CS < VIL,
Outputs Open
mA
CC1
SA
80
90
90
90
90
90
90
LA
SA
LA
SA
LA
75
100
90
85
100
95
85
100
90
85
100
90
85
100
85
85
100
85
85
90
85
25
15
VCC = Max., f = 0
I
Dynamic Operating
Current, CS < VIL,
Outputs Open
mA
mA
mA
CC2
(2 )
VCC = Max., f = fMAX
I
SB
Standby Power Supply
Current (TTL Level)
25
25
25
25
25
25
CS > VIH, Outputs Open
(2 )
20
20
20
20
25
15
VCC = Max., f = fMAX
I
Full Standby Power
Supply Current (CMOS
Level), CS > VHC,
SB1
SA
LA
2
10
10
10
10
10
10
VCC = Max., VIN < VLC
or VIN > VHC, f = 0
0.1
0.9
0.9
0.9
0.9
0.9
0.9
3089 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs are toggling at fMAX, f = 0 means address inputs are not changing.
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) (VLC = 0.2V, VHC = VCC 0.2V)
Typ.(1 )
VCC @
Max.
VCC @
Symbol
VDR
Parameter
VCC for Data Retention
Data Retention Current
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
____
____
____
____
____
2.0
V
____
____
µ
A
MIL.
COM'L.
0.5
0.5
1.5
1.5
200
20
300
30
ICCDR
(3)
____
____
____
____
CS > VHC
VIN > VHC or < VLC
tCDR
Chip Deselect to Data
Retention Time
0
ns
____
____
____
____
____
____
(3 )
(2 )
Operation Recovery Time
Input Leakage Current
ns
tR
tRC
____
2
2
µA
II I
LI
3089 tbl 10
NOTES:
1. TA = + 25°C
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
4
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA RETENTION MODE
VCC
VDR ≥ 2V
4.5V
4.5V
tR
tCDR
VDR
CS
,
VIH
VIH
3089 drw 03
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
1.5V
See Figures 1 and 2
3089 tbl 11
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
5pF*
255Ω
30pF*
255Ω
,
,
3089 drw 05
3089 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tOLZ, tCLZ, tOHZ, tWHZ, tCHZ & tOW)
*Including scope and jig.
6.42
5
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
6116SA15(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
tRC
tAA
tACS
Read Cycle Time
15
20
25
35
ns
ns
ns
ns
ns
ns
____
____
____
____
Address Access Time
15
19
25
35
____
____
____
____
Chip Select Access Time
Chip Select to Output in Low-Z
Output Enable to Output Valid
15
20
25
35
____
____
____
____
(3)
5
5
5
5
tCLZ
____
____
____
____
tOE
10
10
13
20
____
____
____
____
(3)
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
0
0
5
5
tOLZ
____
____
____
____
(3)
10
11
12
15
ns
ns
ns
ns
tCHZ
____
____
____
____
(3)
8
8
10
13
tOHZ
____
____
____
____
tOH
5
5
5
5
____
____
____
____
(3)
0
0
0
0
tPU
____
____
____
____
(3)
Chip Deselect to Power Down Time
15
20
25
35
ns
tPD
3089 tbl 12
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
6116SA45
6116LA45
6116SA55(2)
6116LA55(2)
6116SA70(2)
6116LA70(2)
6116SA90(2)
6116LA90(2)
6116SA120(2)
6116LA120(2)
6116SA150(2)
6116LA150(2)
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
____
____
____
____
____
____
tRC
tAA
tACS
Read Cycle Time
45
55
70
90
120
150
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
Address Access Time
45
55
70
90
120
150
____
____
____
____
____
____
Chip Select Access Time
45
50
65
90
120
150
____
____
____
____
____
____
(3)
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
5
5
5
5
5
5
tCLZ
____
____
____
____
____
____
tOE
25
40
50
60
80
100
____
____
____
____
____
____
(3)
5
5
5
5
5
5
tOLZ
____
____
____
____
____
____
(3)
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
20
30
35
40
40
40
ns
ns
tCHZ
____
____
____
____
____
____
(3)
15
30
35
40
40
40
tOHZ
____
____
____
____
____
____
tOH
5
5
5
5
5
5
ns
3089 tbl 13
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
6
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1,3)
tRC
ADDRESS
tAA
tOH
OE
(5)
tOE
tOHZ
CS
(5)
tOLZ
(5)
tACS
tCHZ
(5)
tCLZ
DATA
VALID
DATAOUT
ICC
tPU
VCC
Supply
Currents
ISB
tPD
,
3089 drw 06
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DATA VALID
DATAOUT
PREVIOUS DATA VALID
,
3089 drw 07
Timing Waveform of Read Cycle No. 3(1,3,4)
CS
(5)
tACS
tCHZ
(5)
tCLZ
,
DATAOUT
DATA VALID
3089 drw 08
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±500mV from steady state.
6.42
7
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges)
6116SA15(1)
6116SA20
6116LA20
6116SA25
6116LA25
6116SA35
6116LA35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tCW
tAW
tAS
Write Cycle Time
15
13
14
0
20
15
15
0
25
17
17
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
tWP
tWR
Write Pulse Width
12
12
15
20
Write Recovery Time
0
0
0
0
____
____
____
____
(3)
Write to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
7
8
16
20
tWHZ
____
____
____
____
tDW
12
0
12
0
13
0
15
0
____
____
____
____
____
____
____
____
(4)
tDH
(3,4)
Output Active from End-of-Write
0
0
0
0
ns
tOW
3089 tbl 14
AC Electrical Characteristics (VCC = 5V ± 10%, All Temperature Ranges) (continued)
6116SA55(2)
6116LA55(2)
6116SA70(2)
6116LA70(2)
6116SA90(2)
6116LA90(2)
6116SA120(2)
6116LA120(2)
6116SA150(2)
6116LA150(2)
6116SA45
6116LA45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tCW
tAW
Write Cycle Time
45
30
30
0
55
40
45
5
70
40
65
15
40
90
55
80
15
55
120
70
150
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
105
20
120
20
AS
t
WP
t
Write Pulse Width
25
40
70
90
tWR
Write Recovery Time
0
5
5
5
5
10
____
____
____
____
____
____
(3)
Write to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
25
30
35
40
40
40
tWHZ
____
____
____
____
____
____
tDW
20
0
25
5
30
5
30
5
35
5
40
10
0
____
____
____
____
____
____
____
____
____
____
____
____
(4)
tDH
(3,4)
Output Active from End-of-Write
0
0
0
0
0
ns
tOW
3089 tbl 15
NOTES:
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
8
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,5,7)
tWC
ADDRESS
tAW
CS
(3)
(7)
tAS
tWP
tWR
(6)
tCHZ
WE
(6)
tWHZ
(4)
(6)
tOW
DATA (4)
VALID
DATAOUT
DATAIN
PREVIOUS DATA VALID
tDW
tDH
DATA VALID
3089 drw 09
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5,7)
tWC
ADDRESS
tAW
CS
WE
(3)
tWR
tAS
tCW
tDW
tDH
DATAIN
DATA VALID
3089 drw 10
,
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers
to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse
is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
6.42
9
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Ordering Information Military
IDT
6116
XX
XXX
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
B
Military (-55 C to +125 C)
°
°
Compliant to MIL-STD-883, Class B
TD
D
300 mil CERDIP (D24-1)
600 mil CERDIP (D24-2)
,
20*
25*
35*
45
Speed in nanoseconds
55
70
90
120
150**
SA
LA
Standard Power
Low Power
*Available in 300 mil packaging only.
**Available in 600 mil packaging only.
3089 drw 11
Ordering Information Commercial & Industrial
IDT
6116
XX
XXX
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-45 C to +85 C)
Blank
I
°
°
TP
P
300 mil Plastic DIP (P24-1)
600 mil Plastic DIP (P24-2)
SO
Y
300 mil Small Outline IC, Gull-Wing Bend (SO24-2)
300 mil SOJ, J-Bend (SO24-4)
,
15*
20
25
35
45
Speed in nanoseconds
SA
LA
Standard Power
Low Power
*Available in commercial temperature range and standard power only.
3089 drw 12
10
IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DatasheetDocumentHistory
1/7/00
Updatedtonewformat
AddedIndustrialTemperaturerangeofferings
Separatedorderinginformationintomilitary,commercial,andindustrialtemperaturerangeofferings
AddedDatasheetDocumentHistory
Pg. 1, 3, 4, 10
Pg. 9, 10
Pg. 11
08/09/00
02/01/01
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800 544-7726, x4033
800-345-7015 or 408-727-6116
fax:408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
11
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