IDT6116SA25TP [IDT]

CMOS STATIC RAM 16K (2K x 8 BIT); CMOS静态RAM 16K （ 2K ×8位）


型号：	IDT6116SA25TP
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CMOS STATIC RAM 16K (2K x 8 BIT) CMOS静态RAM 16K （ 2K ×8位）
文件：	总10页 (文件大小：95K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT6116SA

IDT6116LA

CMOS STATIC RAM

16K (2K x 8 BIT)

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• High-speed access and chip select times

— Military: 20/25/35/45/55/70/90/120/150ns (max.)

— Commercial: 15/20/25/35/45ns (max.)

• Low-power consumption

The IDT6116SA/LA is a 16,384-bit high-speed static RAM

organized as 2K x 8. It is fabricated using IDT's high-perfor-

mance, high-reliability CMOS technology.

Access times as fast as 15ns are available. The circuit also

offers a reduced power standby mode. When CSgoes HIGH,

the circuit will automatically go to, and remain in, a standby

power mode, as long as CS remains HIGH. This capability

provides significant system level power and cooling savings.

The low-power (LA) version also offers a battery backup data

retention capability where the circuit typically consumes only

1µW to 4µW operating off a 2V battery.

All inputs and outputs of the IDT6116SA/LA are TTL-

compatible. Fullystaticasynchronouscircuitryisused, requir-

ing no clocks or refreshing for operation.

The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil

plasticorceramicDIP anda24-leadgull-wingSOIC, anda24

-lead J-bend SOJ providing high board-level packing densi-

ties.

• Battery backup operation

— 2V data retention voltage (LA version only)

• Produced with advanced CMOS high-performance

technology

• CMOS process virtually eliminates alpha particle

soft-error rates

• Input and output directly TTL-compatible

• Static operation: no clocks or refresh required

• Available in ceramic and plastic 24-pin DIP, 24-pin Thin

Dip and 24-pin SOIC and 24-pin SOJ

• Military product compliant to MIL-STD-833, Class B

Militarygradeproductismanufacturedincompliancetothe

latest version of MIL-STD-883, Class B, making it ideally

suited to military temperature applications demanding the

highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

A ₀

VCC

128 X 128

ADDRESS

DECODER

MEMORY

GND

ARRAY

A ₁₀

I/O 0

I/O CONTROL

INPUT

DATA

CIRCUIT

I/O₇

CONTROL

CIRCUIT

3089 drw 01

The IDT logo is aregistered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MARCH 1996

1996 Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.1

3089/1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

CAPACITANCE (TA = +25°C, F = 1.0 MHZ)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions Max. Unit

CIN

VIN = 0V

CI/O

NOTE:

VOUT = 0V

P24-2

P24-1

D24-2

D24-1

SO24-2

A₁₀

3089 tbl 03

1. This parameter is determined by device characterization, but is not

production tested.

I/O

S024-4

I/O₆

I/O

I/O₄

I/O

GND

3089 drw 02

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

DIP/SOIC/SOJ

TOP VIEW

Symbol

Rating

Commercial Military

Unit

Terminal Voltage

with Respect to GND –0.5 to + 7.0 –0.5 to +7.0

(2)

VTERM

Operating

T^A

Temperature

0 to + 70 –55 to +125 °C

–55 to + 125 –65 to +135 °C

–55 to + 125 –65 to +150 °C

Temperature

Under Bias

TBIAS

TSTG

PIN DESCRIPTIONS

Storage

Temperature

A0–A13

I/O0–I/O7

Address Inputs

Data Input/Output

Chip Select

Write Enable

Output Enable

Power

Dissipation

1.0

IOUT

DC Output Current

NOTES:

3089 tbl 04

VCC

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

onlyandfunctionaloperationofthedeviceattheseoranyotherconditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

GND

Ground

3089 tbl 01

2. VTERM must not exceed VCC +0.5V.

TRUTH TABLE⁽¹⁾

Mode

Standby

Read

I/O

High-Z

DATAOUT

High-Z

Read

Write

DATAIN

NOTE:

3089 tbl 02

1. H = VIH, L = VIL, X = Don't Care.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC

OPERATING CONDITIONS

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Symbol

Parameter

Min.

Typ.

5.0

Max. Unit

Grade

Military

Commercial

Temperature

–55°C to +125°C

0°C to +70°C

GND

VCC

Supply Voltage

Supply Ground

Input High Voltage

Input Low Voltage

4.5

5.5⁽²⁾

5.0V ± 10%

GND

VIH

2.2

–0.5⁽¹⁾

3.5 VCC +0.5

0.8

3089 tbl 05

VIL

—

NOTES:

3089 tbl 06

1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.

2. VIN must not exceed VCC +0.5V.

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT6116SA

IDT6116LA

Min. Max.

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

MIL.

COM'L.

MIL.

—

2.4

—

2.4

|ILI|

Input Leakage Current

VCC = Max., VIN = GND to VCC

VCC = Max.

µA

|ILO|

VOL

VOH

Output Leakage Current

Output Low Voltage

Output High Voltage

CS = VIH, VOUT = GND to VCC

IOL = 8mA, VCC = Min.

IOH = –4mA, VCC = Min.

COM'L.

µA

0.4

—

0.4

—

3089 tbl 07

DC ELECTRICAL CHARACTERISTICS ⁽¹⁾

VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V

6116SA15⁽²⁾

6116LA15⁽²⁾

Power Com'l. Mil.

6116SA20

6116LA20

Com'l. Mil.

6116SA25

6116LA25

6116SA35

6116LA35

Symbol

Parameter

Com'l.

Mil.

Com'l.

Mil.

Unit

ICC1

Operating Power Supply

Current, CS ≤ VIL,

Outputs Open,

105

—

105

130

—

120

VCC = Max., f = 0

ICC2

ISB

Dynamic Operating

Current, CS ≤ VIL,

VCC = Max.,

150

140

—

130

120

150

140

120

110

135

125

100

115

105

(4)

Outputs Open, f = fMAX

Standby Power Supply

Current (TTL Level)

CS ≥ VIH, VCC = Max.,

—

(4)

Outputs Open, f = fMAX

ISB1

Full Standby Power

Supply Current

(CMOS Level), CS ≥ VHC, LA

VCC = Max., VIN ≥ VHC

or VIN ≤ VLC, f = 0

—

0.1

0.9

0.1

0.9

0.1

0.9

NOTES:

3089 tbl 08

1. All values are maximum guaranteed values.

2. 0°C to + 70°C temperature range only.

3. –55°C to + 125°C temperature range only.

4. fMAX = 1/tRC, only address inputs are cycling at fMAX, f = 0 means address inputs are not changing.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS ⁽¹⁾(Continued)

VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V

6116SA45

6116LA45

6116SA55⁽³⁾

6116LA55⁽³⁾

6116SA70⁽³⁾

6116LA70⁽³⁾

6116SA90⁽³⁾6116SA120⁽³⁾6116SA150⁽³⁾

6116LA90⁽³⁾6116LA120⁽³⁾6116LA150⁽³⁾

Symbol

Parameter

Power Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit

ICC1

Operating Power Supply

Current, CS ≤ VIL,

Outputs Open,

—

90 mA

—

VCC = Max., f = 0

ICC2

ISB

Dynamic Operating

Current, CS ≤ VIL,

VCC = Max.,

SA 100 100

—

100

—

100

—

100

—

100

—

90 mA

(4)

Outputs Open, f = fMAX

Standby Power Supply

Current (TTL Level)

CS ≥ VIH, VCC = Max.,

—

25 mA

(4)

Outputs Open, f = fMAX

ISB1

Full Standby Power

Supply Current

(CMOS Level), CS ≥ VHC, LA

VCC = Max., VIN ≥ VHC

or VIN ≤ VLC, f = 0

—

10 mA

0.9

0.1

0.9

NOTES:

3089 tbl 09

1. All values are maximum guaranteed values.

2. 0°C to + 70°C temperature range only.

3. –55°C to + 125°C temperature range only.

4. fMAX = 1/tRC, only address inouts are toggling at fMAX, f = 0 means address inputs are not changing.

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(LA Version Only) VLC = 0.2V, VHC = VCC – 0.2V

Typ.⁽¹⁾

VCC

Max.

VCC

Symbol

VDR

Parameter

Test Conditions

Min.

2.0

—

2.0V

—

3.0V

—

2.0V

—

3.0V

—

Unit

VCC for Data Retention

Data Retention Current

—

ICCDR

MIL.

COM'L.

0.5

1.5

—

200

300

µA

CS ≥ VHC

—

(3)

tCDR

Data Deselect to Data

Retention Time

VIN ≥ VHC or ≤ VLC

—

(3)

(2)

Operation Recovery Time

Input Leakage Current

tRC

—

|ILI|

—

µA

NOTES:

3089 tbl 10

1. TA = + 25°C

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but is not production tested.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOW VCC DATA RETENTION WAVEFORM

DATA RETENTION MODE

DR ≥

4.5V

tCDR

3089 drw 03

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

5ns

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

1.5V

See Figures 1 and 2

3089 tbl 11

480Ω

DATAOUT

255

DATA OUT

255

Ω

30pF*

5pF*

Ω

3089 drw 04

3089 drw 05

Figure 1. AC Test Load

Figure 2. AC Test Load

(for tOLZ, tCLZ, tOHZ,

tWHZ, tCHZ & tOW)

*Including scope and jig.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)

(1)

6116SA15

6116LA15

6116SA20

6116LA20

6116SA25

6116LA25

6116SA35

6116LA35

(1)

Symbol Parameter

READ CYCLE

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tRC

tAA

Read Cycle Time

—

Address Access Time

tACS

Chip Select Access Time

(3)

tCLZ

Chip Select to Output in

Low-Z

tOE

Output Enable to Output

Valid

—

(3)

tOLZ

Output Enable to Output

in Low-Z

tCHZ

tOHZ

tOH

Chip Deselect to Output

in High-Z

—

(3)

Output Disable to Output

in High-Z

Output Hold from

Address Change

—

(3)

tPU

tPD

Chip Select to Power-Up

Time

(3)

Chip Deselect to Power-

Down Time

—

3089 tbl 12

AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges) (Continued)

6116SA45

6116LA45

6116SA55⁽²⁾6116SA70⁽²⁾6116SA90⁽²⁾6116SA120⁽²⁾6116SA150⁽²⁾

6116LA55⁽²⁾6116LA70⁽²⁾6116LA90⁽²⁾6116LA120⁽²⁾6116LA150⁽²⁾

Symbol

Parameter

Min. Max.

Min. Max. Min. Max. Min.

Max. Min.

Max. Unit

READ CYCLE

tRC

tAA

Read Cycle Time

—

120

—

150

—

Address Access Time

Chip Select Access Time

120

150

tACS

—

(3)

tCLZ

Chip Select to Output in

Low-Z

—

tOE

Output Enable to Output

Valid

—

100

—

(3)

tOLZ

Output Enable to Output

in Low-Z

tCHZ

Chip Deselect to Output

in High-Z

—

(3)

tOHZ

tOH

Output Disable to Output

in High-Z

—

Output Hold from

Address Change

NOTES:

1. 0°C to + 70°C temperature range only.

2. –55°C to + 125°C temperature range only.

3089 tbl 13

3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1^{(1, 3)}

ADDRESS

tOH

(5)

tOE

tOHZ

(5)

tOLZ

(5)

ACS

CHZ

(5)

CLZ

DATA

VALID

DATA OUT

tPU

ICC

Supply

Currents

3089 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 2 ^{(1, 2, 4)}

tRC

ADDRESS

tAA

tOH

DATA VALID

DATA OUT

PREVIOUS DATA VALID

3089 drw 07

TIMING WAVEFORM OF READ CYCLE NO. 3 ^{(1, 3, 4)}

(5)

tACS

tCHZ

(5)

tCLZ

DATA OUT

DATA VALID

3089 drw 08

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±500mV from steady state.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)

6116SA15⁽¹⁾

6116LA15⁽¹⁾

6116SA20

6116SA25

6116SA35

6116LA35

6116LA20

6116LA25

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

tWC

tCW

Write Cycle Time

—

Chip Select to End-of-

Write

tAW

Address Valid to End-

of-Write

—

tAS

Address Set-up Time

Write Pulse Width

—

tWP

tWR

tWHZ

Write Recovery Time

(3)

Write to Output

in High-Z

—

tDW

Data to Write Time

Overlap

—

(4)

tDH

Data Hold from Write

Time

(3,4)

tOW

Output Active from

End-of-Write

3089 tbl 14

AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)

6116SA45

6116LA45

6116SA55⁽²⁾6116SA70⁽²⁾6116SA90⁽²⁾6116SA120⁽²⁾6116SA150⁽²⁾

6116LA55⁽²⁾6116LA70⁽²⁾6116LA90⁽²⁾6116LA120⁽²⁾6116LA150⁽²⁾

Symbol

Parameter

Min.

Max. Min.

Max. Min. Max.

Min. Max. Min. Max.

Min. Max. Unit

WRITE CYCLE

tWC

tCW

Write Cycle Time

—

120

—

150

—

Chip Select to End of

Write

tAW

Address Valid to End

of Write

—

105

—

120

—

tAS

Address Set-up Time

Write Pulse Width

—

tWP

tWR

tWHZ

Write Recovery Time

(3)

Write to Output

in High-Z

—

tDW

Data to Write Time

Overlap

—

(4)

tDH

Data Hold from Write

Time

(3,4)

tOW

Output Active from

End of Write

NOTES:

1. 0°C to +70°C temperature range only.

2. –55°C to +125°C temperature range only.

3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested.

3089 tbl 15

4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(1, 2, 5, 7)

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (

CONTROLLED TIMING)

tWC

ADDRESS

tAW

(3)

(7)

tAS

tWP

(6)

CHZ

DATA OUT

DATA IN

(6)

WHZ

(6)

DATA ⁽⁴⁾

VALID

(4)

PREVIOUS DATA VALID

DATA VALID

3089 drw 09

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

CONTROLLED TIMING) ^{(1, 2, 3, 5, 7)}

ADDRESS

tAW

(3)

tWR

tCW

tDW

tDH

DATA IN

DATA VALID

3089 drw 10

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state and the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

6. Transition is measured ±500mV from steady state.

7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the

I/O drivers to turn off and data to be placed on the bus for the required t^DW. If OE is HIGH during a WE controlled write cycle, this requirement does not

apply and the write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.

5.1

IDT6116SA/LA

CMOS STATIC RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

6116

XXX

Device Type

Power

Speed

Package

Process/

Temperature

Range

Commercial (0

C to +70

°C)

Blank

Military (-55

C to + 125 C)

Compliant to MIL-STD-883, Class B

300 mil Plastic DIP (P24-1)

600 mil Plastic DIP (P24-2)

300 mil CERDIP (D24-1)

600 mil CERDIP (D24-2)

300 mil Small Outline IC, Gull-Wing Bend (SO24-2)

300 mil SOJ, J-Bend (SO24-4)

Commercial Only

Speed in nanoseconds

Military Only

120 Military Only

150 Military Only

Standard Power

Low Power

3089 drw 11

5.1

IDT6116SA25TP [IDT]

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