IDT62ALVCH16823PA [IDT]

3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD; 3.3V CMOS 18位总线接口具有三态输出和总线保持FLIPFLOP


型号：	IDT62ALVCH16823PA
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD 3.3V CMOS 18位总线接口具有三态输出和总线保持FLIPFLOP 输出元件
文件：	总7页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT

BUS-INTERFACE FLIP-

FLOP WITH 3-STATE OUT-

PUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

This18-bitbus-interfaceflip-flopisbuiltusingadvanceddualmetalCMOS

technology.TheALVCH16823features3-stateoutputsdesignedspecifically

fordrivinghighlycapacitiveorrelativelylow-impedanceloads.Thedeviceis

particularlysuitableforimplementingwiderbufferregisters,I/Oports,bidirec-

tional bus drivers with parity, and working registers.

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

TheALVCH16823canbeusedastwo9-bitflip-flopsorone18-bitflip-flop.

Withtheclock-enable(CLKEN)inputlow,theD-typeflip-flopsenterdataonthe

low-to-hightransitionsoftheclock.TakingCLKENhighdisablestheclockbuffer,

thuslatchingtheoutputs.Takingtheclear(CLR)inputlowcausestheQoutputs

togolowindependentlyoftheclock.

Abufferedoutput-enable(OE)inputcanbeusedtoplacethenineoutputs

ineitheranormallogicstate(highorlowlogiclevels)orahigh-impedancestate.

In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the

capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.The

OEinputdoesnotaffecttheinternaloperationoftheflip-flops.Olddatacanbe

retainedornewdatacanbeenteredwhiletheoutputsareinthehigh-impedance

state.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

The ALVCH16823 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

• 3.3V and lower voltage computing systems

The ALVCH16823 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand

eliminatestheneedforpull-up/downresistor.

FUNCTIONALBLOCKDIAGRAM

1OE

2OE

1CLR

2CLR

1CLKEN

2CLKEN

1CLK

1D1

1Q1

2CLK

2D1

2Q1

TO 8 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2004

DSC-4237/2

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

1CLR

1OE

1Q1

1CLK

1CLKEN

1D1

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

°C

Continuous Clamp Current,

VI < 0 or VI > VCC

GND

1Q2

GND

1D2

IOK

Continuous Clamp Current, VO < 0

–50

1Q3

1D3

ICC

ISS

Continuous Current through each

VCC or GND

±100

VCC

1Q4

1Q5

1Q6

VCC

1D4

1D5

1D6

GND

1D7

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

GND

1Q7

1Q8

1Q9

2Q1

2. V^CCterminals.

3. All terminals except V^CC.

1D8

1D9

2D1

2D2

2D3

GND

2D4

2D5

2D6

VCC

2D7

2D8

2Q2

2Q3

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

GND

2Q4

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

2Q5

COUT

2Q6

VCC

2Q7

COUT

NOTE:

1. As applicable to the device type.

2Q8

GND

2Q9

GND

2D9

2OE

2CLKEN

2CLK

2CLR

(1)

FUNCTION TABLE (EACH 9-BIT FLIP-FLOP)

Inputs

Output

TSSOP

TOP VIEW

xOE

xCLR

xCLKEN

xCLK

xDx

xQx

↑

PINDESCRIPTION

Pin Names

Description

(2)

Q₀

xDx

xCLK

xCLKEN

xQx

Data Inputs⁽¹⁾

Clock Input

(2)

Q₀

Clock Enable Inputs

3-State Outputs

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

xOE

xCLR

3-State Output Enable Inputs

Clear Inputs

Z = High Impedance

↑ = LOW-to-HIGH transition

2. Output level before the indicated steady-state input conditions were established.

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

±5

µA

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

±10

–1.2

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

Input Hysteresis

—

100

0.1

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µA

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

VCC = 2.3V

VCC = 2.7V

VCC = 3V

1.7

2.2

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

IOL = 24mA

VCC = 2.7V

VCC = 3V

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

Unit

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

Parameter

Min.

150

Max.

—

Min.

150

—

Max.

—

Min.

150

Max.

—

Unit

MHz

PropagationDelay

5.8

5.2

4.5

xCLK to xQx

PropagationDelay

5.4

—

5.2

5.7

4.7

1.2

4.6

4.8

4.5

xCLR to xQx

OutputEnableTime

xOE to xQx

OutputDisableTime

1.1

5.4

1.3

xOE to xQx

PulseDuration, xCLRLOW

Pulse Duration, xCLK HIGH or LOW

Set-upTime,xCLRinactive

Set-upTime, dataLOWbeforexCLK↑

Set-up Time, data HIGH before xCLK↑

Set-up Time, xCLKEN LOW before xCLK↑

Hold Time, data LOW after xCLK↑

Hold Time, data HIGH after xCLK↑

Hold Time, xCLKEN LOW after CLK↑

OutputSkew⁽²⁾

3.3

0.7

1.4

1.1

1.8

0.4

0.7

0.2

—

3.3

0.7

1.6

1.1

1.9

0.5

0.1

0.3

—

3.3

0.8

1.3

—

500

tSU

1.5

0.5

0.8

0.4

—

tSK(O)

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

tPLH

VLOAD

VIH

2 x Vcc

Vcc

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPLH

tPHL

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

Propagation Delay

ALVC Link

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

Generator

VLZ

VOL

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

VIH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

DATA

INPUT

tSU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

tREM

Open Drain

Disable Low

Enable Low

ASYNCHRONOUS

CONTROL

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

All Other Tests

Open

ALVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

tPHL1

VOH

VOL

LOW-HIGH-LOW

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

ALVC

XXX

Device Type Package

IDT

XXX

Bus-Hold

Family

Temp. Range

Thin Shrink Small Outline Package

18-Bit Bus-Interface Flip-Flop with 3-State Outputs

Double-Density, ±24mA

823

Bus-Hold

–40°C to +85°C

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for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT62ALVCH16823PA [IDT]

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