IDT7007L15GI_技术文档

HIGH-SPEED

IDT7007S/L

32K x 8 DUAL-PORT

STATIC RAM

Features

◆

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

Military:25/35/55ns(max.)

Industrial: 55ns (max.)

◆

Commercial:15/20/25/35/55ns(max.)

Low-power operation

◆

Full on-chip hardware support of semaphore signaling

between ports

IDT7007S

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA and PLCC and a 80-pin TQFP

Industrial temperature range (40°C to +85°C) is available

for selected speeds

Active:850mW(typ.)

Standby: 5mW (typ.)

IDT7007L

Active:850mW(typ.)

Standby: 1mW (typ.)

IDT7007 easily expands data bus width to 16 bits or more

◆

FunctionalBlockDiagram

OER

OEL

CE

R/W

L

CE

R/W

R

L

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

(1,2)

R

BUSY ^(1,2)

L

BUSY

A

14R

A

14L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

A0R

15

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

OE

R/W

L

CE

OE

R/W

R

L

R

L

SEM

INT

R

SEM

L

M/S

INT ⁽²⁾

L

(2)

2940 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

JUNE 1999

1

DSC 2940/8

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

IDT7007isdesignedtobeusedasastand-alone256K-bitDual-PortRAM a very LOW standby power mode.

orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more FabricatedusingIDTsCMOShigh-performancetechnology,these

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach devices typically operate on only 850mW of power.

in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC,

and an 80-pin thin quad flatpack, TQFP. Military grade product is

This device provides two independent ports with separate control, manufacturedincompliancewiththelatestrevisionofMIL-PRF-38535

address,andI/Opinsthatpermitindependent,asynchronousaccessfor QML,ClassB,makingitideallysuitedtomilitarytemperatureapplications

reads or writes to any location in memory. An automatic power down demandingthehighestlevelofperformanceandreliability.

PinConfigurations^(1,2,3)

INDEX

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

60

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

A5L

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

59

58

57

56

55

IDT7007J

J68-1

54

53

52

51

50

49

48

47

46

45

44

(4)

GND

M/S

BUSYR

68-Pin PLCC

(5)

Top View

INTR

A0R

A1R

A2R

A3R

A4R

I/O3R

I/O4R

I/O5R

I/O_6R

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

2940 drw 02

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately .95 in x .95 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

2

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

INDEX

1

2

N/C

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

60

A

5L

4L

3L

2L

1L

0L

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

3

4

5

6

7

7007PF

8

INTL

PN80-1⁽⁴⁾

9

BUSY

GND

M/S

L

V

N/C

GND

CC

10

11

12

13

14

15

16

17

18

19

20

80-Pin TQFP

Top View⁽⁵⁾

BUSY

R

0R

I/O

,

INT

R

I/O1R

I/O2R

A

0R

1R

2R

3R

4R

V

CC

I/O3R

I/O4R

5R

I/O

N/C

I/O6R

N/C

2940 drw 03

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

3

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

51

A5L

52

A6L

54

A8L

56

50

A4L

48

A2L

46

A0L

44

BUSYL

42

M/S

40

INTR

38

A1R

36

A3R

11

10

09

08

07

53

A7L

49

A3L

47

A1L

45

INTL

43

GND

41

BUSYR

39

37

35

A4R

34

A5R

A0R A2R

55

A9L

32

A7R

33

A6R

57

A11L

30

A9R

31

A8R

A10L

58

59

VCC

28

A11R

29

A10R

IDT7007G

G68-1

A12L

60

A13L

62

(4)

61

26

GND

27

A12R

06

05

04

03

02

01

A14L

68-Pin PGA

Top View

63

24

25

(5)

SEML

A14R A13R

CEL

65

64

22

SEMR

23

CER

OEL

R/WL

66

67

20

OER

21

R/WR

I/O0L

N/C

1

3

5

7

9

68

11

13

VCC

15

18

I/O7R

19

N/C

GND

I/O7L

I/O1L

I/O4L

I/O2L

I/O1R

I/O4R

2

4

6

8

10

12

14

16

17

I/O5L

I/O0R I/O2R I/O3R I/O5R I/O6R

VCC

E

I/O6L

I/O3L

K

A

B

C

D

F

G

H

J

L

INDEX

2940 drw 04

NOTES:

1. All Vcc pins must be connected to power supply

2. All GND pins must be connected to power supply

3. Package body is approximately 1.8 in x 1.8 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

PinNames

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

Address

CE^L

CER

W^L

W^R

R/

OE^L

OER

0L

14L

0R

14R

A

- A

A

- A

0L

7L

0R

7R

I/O - I/O

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

SEM^L

SEMR

INTR

BUSYR

S

INT^L

BUSY^L

M/

Master or Slave Select

Power

CC

V

GND

Ground

2940 tbl 01

4

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/

W

I/O0-7

Mode

CE

H

L

OE

X

SEM

H

X

High-Z

DATA^IN

Deselected: Power-Down

Write to Memory

L

H

X

H

L

H

DATA^OUTRead Memory

High-Z Outputs Disabled

X

H

X

2940 tbl 02

NOTE:

1. A0L A14L ≠ A0R A14R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

I/O0-7

Mode

CE

OE

SEM

H

L

DATAOUT

Read Semaphore Flag Data Out (I/O0-I/O7)

H

L

↑

X

L

DATAIN

Write I/O0 into Semaphore Flag

Not Allowed

______

X

2940 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.

AbsoluteMaximumRatings⁽¹⁾

MaximumOperatingTemperature

andSupply Voltage^(1,2)

Symbol

Rating

Commercial

& Industrial

Military

Unit

Ambient

(2)

Grade

Temperature

-55^OC to+125^OC

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

Vcc

V^TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

Military

5.0V + 10%

Temperature

Under Bias

-55 to +125

-55 to +120

50

-55 to +135

-65 to +150

50

^oC

Commercial

Industrial

0V

T^BIAS

T^STG

IOUT

0V

Storage

Temperature

2940 tbl 05

NOTES:

1. This is the parameter TA.

2. Industrial temperature: for other speeds, packages and powers contact your

sales office.

DC Output

Current

mA

2940 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sec-tions of this specification is not implied. Exposure

to absolute maxi-mum rating conditions for extended periods may affect

reliability.

RecommendedOperating

Conditions

Symbol

Parameter

Min.

Typ.

Max. Unit

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

V^CC

Supply Voltage

4.5

5.0

5.5

0

V

GND

V^IH

Ground

0

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

Capacitance(TA = +25°C, f = 1.0mhz)

Parameter⁽¹⁾

Input Capacitance

Output Capacitance

Conditions⁽²⁾

Max.

Unit

V

IL

-0.5⁽¹⁾

V

____

Symbol

2940 tbl 06

C^IN

V^IN= 3dV

9

pF

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

C^OUT

V^OUT= 3dV

10

pF

2940 tbl 07

NOTES:

1. This parameter is determined by device characterization but is not production

tested. TQFP package only.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

5

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7007S

7007L

Symbol

|I^LI|

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

V^CC= 5.5V, V^IN= 0V to V^CC

CE = V^IH, V^OUT= 0V to V^CC

I^OL= 4mA

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

5

___

|I^LO|

10

V^OL

0.4

___

V^OH

Output High Voltage

I^OH= -4mA

2.4

V

2940 tbl 08

NOTE:

1. At Vcc < 2.0V, input leakages are undefined.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6)(VCC = 5.0V ± 10%)

7007X15

Com'l Only

7007X20

Com'l Only

7007X25

Com'l &

Military

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

CC

I

Dynamic Operating

Current

(Both Ports Active)

S

L

190

325

285

180

315

275

170

305

265

mA

IL, Outputs Open

CE = V

SEM = VIH

(3)

f = fMAX

___

MIL &

IND

S

L

170

345

305

ISB1

ISB2

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

35

85

60

30

85

60

25

85

60

mA

L =

R = VIH

SEM^R= SEM^L= VIH

CE CE

(3)

MAX

f = f

___

MIL &

IND

S

L

25

100

80

(5)

Standby Current

(One Port - TTL Level

Inputs)

COM'L

"A"

IL

"B"

IH

S

L

125

220

190

115

210

180

105

200

170

CE = V and CE = V

Active Port Outputs Open,

(3)

MAX

f=f

___

MIL &

IND

S

L

105

230

200

SEM^R= SEM^L= VIH

ISB3

ISB4

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE^Land

CE^R> VCC - 0.2V

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0⁽⁴⁾

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

mA

___

MIL &

IND

S

L

1.0

02.

30

10

R

L

CC

SEM = SEM > V - 0.2V

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

S

L

120

190

160

110

185

160

100

175

160

CE^"A"< 0.2V and

CE^"B"> VCC - 0.2V⁽⁵⁾

SEM^R= SEM^L> VCC - 0.2V

___

MIL &

IND

S

L

100

200

175

VIN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Open

(3)

f = fMAX

2940 tbl 09

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

6

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6)(con't.) (VCC = 5.0V ± 10%)

7007X35

Com'l &

Military

7007X55

Com'l, Ind

& Military

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating Current

(Both Ports Active)

S

L

160

295

255

150

270

230

mA

CE = VIL, Outputs Open

SEM = VIH

(3)

f = fMAX

____

MIL &

IND

S

L

335

295

150

310

270

I

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

20

85

60

20

85

60

mA

SB1

CE^L= CE^R= VIH

SEM^R= SEM^L= VIH

(3)

f = fMAX

____

MIL &

IND

S

L

100

80

13

100

80

(5)

ISB2

Standby Current

(One Port - TTL Level Inputs)

COM'L

S

L

95

185

155

85

165

135

CE = V and CE = V

IH

"A"

IL

"B"

Active Port Outputs Open,

(3)

f=fMAX

____

MIL &

IND

S

L

215

185

85

195

165

SEM^R= SEM^L= VIH

I

Full Standby Current (Both

Ports - All CMOS Level

Inputs)

Both Ports CE and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

SB3

L

CE^R> VCC - 0.2V

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0⁽⁴⁾

____

MIL &

IND

S

L

30

10

1.0

0.2

30

10

SEM^R= SEM^L> VCC - 0.2V

ISB4

Full Standby Current

(One Port - All CMOS Level

Inputs)

COM'L

S

L

90

160

135

80

135

110

CE < 0.2V and

"A"

CE^"B"> VCC - 0.2V⁽⁵⁾

SEM^R= SEM^L> VCC - 0.2V

____

MIL &

IND

S

L

190

165

80

165

140

VIN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Open

(3)

f = fMAX

2940 tbl 10

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using

AC Test Conditions of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for other speeds, packages and powers contact your sales office.

7

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

5ns Max.

1.5V

893

Ω

893

Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

30pF

5pF*

347

Ω

347

Ω

1.5V

Figures 1 and 2

.

2940 tbl 11

2940 drw 05

2940 drw 06

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

Figure 1. AC Output Test Load

* Including scope and jig.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(4,5)

7007X15

Com'l Only

7007X20

Com'l Only

7007X25 Com'l

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

tRC

tAA

Read Cycle Time

15

20

25

ns

____

Address Access Time

15

20

25

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

tACE

tAOE

t^OH

tLZ

____

10

12

13

____

3

____

3

Output High-Z Time^(1,2)

10

12

15

____

tHZ

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

0

____

tPU

tPD

tSOP

tSAA

____

15

20

25

____

Semaphore Flag Update Pulse (OE or SEM

)

10

12

____

Semaphore Address Access Time

15

20

25

ns

2940 tbl 12a

7007X35

Com'l &

Military

7007X55

Com'l, Ind

& Military

Symbol

READ CYCLE

Parameter

Min.

Max.

Min.

Max.

Unit

____

tRC

tAA

Read Cycle Time

35

55

ns

____

Address Access Time

35

55

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

tACE

tAOE

tOH

____

20

30

____

3

____

tLZ

3

Output High-Z Time^(1,2)

15

25

____

tHZ

Chip Enable to Power Up Time ⁽²⁾

Chip Disable to Power Down Time ⁽²⁾

0

____

tPU

____

tPD

35

50

____

tSOP

tSAA

NOTES:

Semaphore Flag Update Pulse (OE or SEM

)

15

____

Semaphore Address Access Time

35

55

ns

2940 tbl 12b

1. Transition is measured ±200mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part numbers indicates power rating (S or L).

5. Industrial temperature: for other speeds, packages and powers contact your sales office.

8

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

R/W

(1)

LZ

t

OH

(2)

t

VALID DATA⁽⁴⁾

DATAOUT

t

HZ

BUSYOUT

(3,4)

2940 drw 07

tBDD

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

tPD

ICC

ISB

,

2940 drw 08

9

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage^(5,6)

7007X15

Com'l Only

7007X20

Com'l Only

7007X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

tWC

tEW

tAW

tAS

Write Cycle Time

15

12

0

20

15

0

25

20

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

tWP

tWR

tDW

tHZ

12

0

15

0

20

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

10

15

____

10

12

15

____

tDH

0

(1,2)

____

tWZ

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

tOW

tSWRD

tSPS

0

5

0

5

0

5

____

ns

2940 tbl 13a

7007X35

Com'l Only

7007X55

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

tWC

tEW

tAW

tAS

Write Cycle Time

35

30

0

55

45

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

tWP

tWR

tDW

tHZ

Write Pulse Width

25

0

40

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

15

30

____

12

25

tDH

Data Hold Time⁽⁴⁾

0

____

Write Enable to Output in High-Z^(1,2)

Output Active from End-of-Write ^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

12

25

____

tWZ

____

tOW

tSWRD

tSPS

0

5

0

5

____

ns

2940 tbl 13b

NOTES:

1. Transition is measured ±200mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

6. Industrial temperature: for other speeds, packages and powrs contact your sales office.

10

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

tWP

tWR

tAS

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

2940 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

tWC

ADDRESS

tAW

CE or SEM⁽⁹⁾

(6)

tAS

(3)

(2)

tWR

tEW

R/W

tDW

tDH

DATAIN

2940 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +200mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

11

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

t

SAA

t

OH

0 2

A -A

VALID ADDRESS

t

AW

t

WR

t

ACE

t

EW

SEM

t

DW

t

SOP

DATAOUT

VALID

DATAIN VALID

DATA

0

t

AS

t

WP

t

DH

R/

W

t

SWRD

t

AOE

OE

t

SOP

Write Cycle

Read Cycle

2940 drw 11

NOTE:

1. CE = VIH for the duration of the above timing (both write and read cycle).

Timing Waveform of Semaphore Write Contention^(1,3,4)

0"A" 2"A"

A

-A

MATCH

SIDE⁽²⁾"A"

W"A"

R/

SEM"A"

SPS

t

0"B" 2"B"

A

-A

MATCH

SIDE⁽²⁾

"B"

W"B"

R/

SEM"B"

2940 drw 12

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W^Aor SEMA going HIGH to R/WB or SEMB going HIGH.

4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

12

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(6,7)

7007X15

Com'l Only

7007X20

Com'l Only

7007X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/

t^BAA

S=VIH)

____

15

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t^BDA

t^BAC

tBDC

t^APS

t^BDD

t^WH

15

17

____

5

____

BUSY Disable to Valid Data⁽³⁾

18

30

(5)

____

Write Hold After BUSY

12

15

17

BUSY TIMING (M/S=VIL)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY

t^WB

0

ns

(5)

____

t^WH

12

15

17

PORT-TO-PORT DELAY TIMING

t^WDD

Write Pulse to Data Delay⁽¹⁾

30

25

45

30

50

35

ns

____

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

____

2940 tbl 14a

7007X35

Com'l &

Military

7007X55

Com'l, Ind

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S=VIH)

____

t^BAA

20

45

40

ns

BUSY Access Time from Address Match

tBDA

t^BAC

tBDC

t^APS

t^BDD

t^WH

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

20

35

____

5

____

BUSY Disable to Valid Data⁽³⁾

35

40

(5)

____

Write Hold After BUSY

25

BUSY TIMING (M/S=VIL)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY

t^WB

0

ns

(5)

____

t^WH

25

PORT-TO-PORT DELAY TIMING

t^WDD

Write Pulse to Data Delay⁽¹⁾

60

45

80

65

ns

____

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

____

2940 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD tWP (actual) or tDDD tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial temperature: for other speeds, packages and powers contact your sales office.

13

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY^(2,5)

(M/S = VIH)⁽⁴⁾

tWC

MATCH

ADDR"A"

t

WP

W_"A"

R/

t

DW

t

DH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

tBDA

tBDD

BUSY_"B"

tWDD

VALID

DATAOUT "B"

(3)

tDDD

2940 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

WP

t

"A"

R/W

WB

t

BUSY"B"

R/W"B"

(1)

WH

t

(2)

,

2940 drw 14

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

14

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

tBAC

tBDC

BUSY"B"

2940 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

t

APS

MATCHING ADDRESS "N"

t

BAA

tBDA

2940 drw 16

NOTES:

1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(1,2)

7007X15

Com'l Only

7007X20

Com'l Only

7007X25

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

tAS

Address Set-up Time

0

ns

____

tWR

tINS

tINR

Write Recovery Time

Interrupt Set Time

0

____

15

20

____

Interrupt Reset Time

ns

2940 tbl 15a

7007X35

Com'l &

Military

7007X55

Com'l, Ind

& Military

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Unit

____

tAS

Address Set-up Time

0

ns

____

tWR

tINS

tINR

Write Recovery Time

Interrupt Set Time

0

____

25

40

____

Interrupt Reset Time

ns

2940 tbl 15b

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. Industrial temperature: for other speeds, packages and powers contact your sales office.

15

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

t

WC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR"A"

(4)

(3)

t

AS

t

WR

CE"A"

R/

W

"A"

(3)

t

INS

INT"B"

2940 drw 17

t

RC

ADDR"B"

CE"B"

INTERRUPT CLEAR ADDRESS ⁽²⁾

(3)

t

AS

OE"B"

(3)

t

INR

INT"B"

2940 drw 18

NOTES:

1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III Interrupt Flag⁽¹⁾

Left Port

Right Port

R/

W

L

A14L-A0L

7FFF

X

R/

W

R

A14R-A0R

X

Function

CE

L

OE

L

INT

L

CE

R

OE

R

INT

R

L

X

L

X

L

X

L

X

L

X

L⁽²⁾

H⁽³⁾

X

Set Right INTR Flag

Reset Right INTR Flag

Set Left INTL Flag

X

L

7FFF

7FFE

X

L⁽³⁾

H⁽²⁾

L

X

L

7FFE

X

Reset Left INT^LFlag

2940 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

16

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table IV Address BUSY

Arbitration

Inputs

Outputs

AOL-A14L

AOR-A14R

(1)

Function

Normal

CE^L

X

CER

X

BUSYL

BUSYR

NO MATCH

MATCH

H

X

Normal

X

H

MATCH

H

Normal

L

MATCH

(2)

Write Inhibit⁽³⁾

2940 tbl 17

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are

push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0 - D7 Left

D0 - D7 Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2940 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.

2. There are eight semaphore flags written to via I/O5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

when CE^R= OER = VIL, R/W is a "don't care". Likewise, the right port

interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread

thememorylocation7FFF. Themessage(8bits)at7FFEor7FFFisuser-

definedsinceitisanaddressableSRAMlocation.Iftheinterruptfunction

isnotused,addresslocations7FFEand7FFFarenotusedasmailboxes,

butaspartoftherandomaccessmemory.RefertoTableIIIfortheinterrupt

operation.

TheIDT7007providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7007hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CEHIGH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

INTERRUPTS

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 7FFE

(HEX), where a write is defined as CE = R/W= VIL per the Truth Table.

Theleftportclearstheinterruptthroughaccessofaddresslocation7FFE

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime. Italsoallowsoneof

the two accesses to proceed and signals the other side that the RAM is

17

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

busy. The BUSY pin can then be used to stall the access until the

operation on the other side is completed. If a write operation has been

attemptedfromthesidethatreceivesaBUSYindication,thewritesignal

isgatedinternallytopreventthewritefromproceeding.

Semaphores

TheIDT7007isanextremelyfastDual-Port 32Kx8CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesignerssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSYindication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations

can be prevented to a port by tying the BUSYpin for that port LOW.

TheBUSYoutputsontheIDT7007RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

The Dual-Port RAM features a fast access time, and both ports are

completelyindependentofeachother.Thismeansthattheactivityonthe

left port in no way slows the access time of the right port. Both ports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both HIGH.

Width Expansion with Busy Logic

Master/SlaveArrays

Systems which can best use the IDT7007 contain multiple proces-

sors or controllers and are typically very high-speed systems which

are software controlled or software intensive. These systems can

benefit from a performance increase offered by the IDT7007 hardware

semaphores, which provide a lockout mechanism without requiring

complexprogramming.

Software handshaking between processors offers the maximum in

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7007doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

CE

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

(L)

(R)

BUSY

BUSY (L)

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L) BUSY (R)

(L)

BUSY

,

2940 drw 19

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7007 RAMs.

WhenexpandinganIDT7007RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill

receiveaBUSYindication,andtooutputthatindication.Anynumberof

slavestobeaddressedinthesameaddressrangeasthemaster,usethe

BUSYsignalasawriteinhibitsignal.ThusontheIDT7007RAMtheBUSY

pinisanoutputifthepartisusedasamaster(M/Spin=H),andtheBUSY

pin is an input if the part used as a slave (M/S pin = L) as shown in

Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration, onamaster, isbasedonthechipenableand

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan

result in a glitched internal write inhibit signal and corrupted data in the

slave.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

calledTokenPassingAllocation.Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst,hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

thatsemaphoresstatusorremoveitsrequestforthatsemaphoretoperform

anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,

theleftsideshouldsucceedingainingcontrol.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

18

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstsidesrequest

aonetothatlatch. latch.Thesecondsidesflagwillnowstaylowuntilitssemaphorerequest

The eight semaphore flags reside within the IDT7007 in a separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requested and the processor which requested it no longer needs the

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that

semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.

R/W) as they would be used in accessing a standard Static RAM. Each

The critical case of semaphore timing is when both sides request a

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The

throughaddresspinsA0A2.Whenaccessingthesemaphores,noneof semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

theotheraddresspinshasanyeffect.

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel the token. If one side is earlier than the other in making the request, the

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero firstsidetomaketherequestwillreceivethetoken.Ifbothrequestsarrive

on that side and a one on the other side (see Truth Table V). That at the same time, the assignment will be arbitrarily made to one port or

semaphorecannowonlybemodifiedbythesideshowingthezero.When

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

L PORT

R PORT

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside

ispending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D

0

D

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

2940 drw 20

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintoonesidesoutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableV).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation. Onasubsequentread, theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attempts to write a zero to the same semaphore flag it will fail, as will be

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

Figure 4. IDT7007 Semaphore Logic

theother.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

or misinterpreted, a software error can easily happen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

Using SemaphoresSome Examples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resourcemarkersfortheIDT7007sDual-PortRAM. Saythe32Kx8RAM

was to be divided into two 16K x 8 blocks which were to be dedicated at

anyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

Totakearesource,inthisexamplethelower16KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

back rather than a one), the left processor would assume control of the

lower16K.Meanwhiletherightprocessorwasattemptingtogaincontrol

ofthe resourceaftertheleftprocessor,itwouldreadbackaoneinresponse

to the zero it had attempted to write into Semaphore 0. At this point, the

softwarecouldchoosetotryandgaincontrolofthesecond16Ksection

bywriting,thenreadingazerointoSemaphore1.Ifitsucceededingaining

control,itwouldlockouttheleftside.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation. The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

sideHIGH. Thisconditionwillcontinueuntilaoneiswrittentothesame

semaphorerequestlatch.Shouldtheothersidessemaphorerequestlatch

havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

19

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Once the left side was finished with its task, it would write a one to wasoff-limitstotheCPU,boththeCPUandtheI/Odevicescouldaccess

Semaphore 0 and may then try to gain access to Semaphore 1. If theirassignedportionsofmemorycontinuouslywithoutanywaitstates.

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

SemaphoresarealsousefulinapplicationswherenomemoryWAIT

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then stateisavailableononeorbothsides.Onceasemaphorehandshakehas

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask been performed, both processors can access their assigned RAM

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap segmentsatfullspeed.

16K blocks of Dual-Port RAM with each other.

Anotherapplicationisintheareaofcomplexdatastructures. Inthis

The blocks do not have to be any particular size and can even be case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

variable, depending upon the complexity of the software using the mayberesponsibleforbuildingandupdatingadatastructure.Theother

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

Port RAM or other shared resources into eight parts. Semaphores can processorreadsanincompletedatastructure,amajorerrorconditionmay

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

given a common meaning as was shown in the example above.

differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

Semaphores are a useful form of arbitration in systems like disk itandthenisabletogoinandupdatethedatastructure.Whentheupdate

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring is completed, the data structure block is released. This allows the

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse interpretingprocessortocomebackandreadthecompletedatastructure,

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea therebyguaranteeingaconsistentdatastructure.

20

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I⁽¹⁾

B

Commercial (0°C to +70°C)

°

Industrial (-40 C to +85 C)

°

Military (-55 C to +125 C)

Compliant to MIL-PRF-38535 QML

PF

G

J

80-pin TQFP (PN80-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

Commercial Only

Commercial & Military

Commercial, Industrial & Military

15

20

25

35

55

Speed in nanoseconds

S

L

Standard Power

Low Power

256K (32K x 8) Dual-Port RAM

7007

2940 drw 21

NOTE:

1. Industrial temperature range is available on selected packages.

For other speeds, packages and powers contact your sales office.

DatasheetDocumentHistory

1/5/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Pages2, 3, 4Addedadditionalnotestopinconfigurations

Changeddrawingformat

6/3/99:

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800-345-7015 or 408-727-5166

fax: 408-492-8674

for Tech Support:

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DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

21


型号：	IDT7007L15GI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM 高速32K ×8双端口静态RAM
文件：	总21页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7007L15GI [IDT]

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