IDT7026S35JB [IDT]
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM; 高速16K ×16双口静态RAM型号: | IDT7026S35JB |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM |
文件: | 总18页 (文件大小:239K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7026S/L
16K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
• IDT7026 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• On-chip port arbitration logic
— IDT7026S
• Full on-chip hardware support of semaphore signaling
between ports
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• Fully asynchronous operation from either port
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA and 84-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
UB
W
L
L
R/
W
R
UB
R
LB
CE
OE
L
LB
CE
OER
R
L
R
L
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSY(1,2)
L
BUSY (1,2)
R
A
13L
0L
A
13R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0R
14
14
ARBITRATION
SEMAPHORE
LOGIC
CEL
CER
SEM
R
SEM
L
M/S
2939 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs are non-tri-stated push-pull.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
©1996 Integrated Device Technology, Inc.
DSC 2939/3
1
6.17
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7026 is a high-speed 16K x 16 Dual-Port Static
RAM. The IDT7026 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 32-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7026 is packaged in a ceramic 84-pin PGA, and a
84-pin PLCC. Military grade product is manufactured in com-
pliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
INDEX
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
I/O8L
I/O9L
A
A
A
A
A
A
A
A
8L
7L
6L
5L
4L
3L
2L
1L
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
A0L
IDT7026
J84-1
BUSY
L
VCC
84-PIN PLCC
(3)
GND
I/O0R
I/O1R
I/O2R
GND
TOP VIEW
M/S
BUSY
R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
V
CC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2939 drw 02
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.17
2
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D) (1,2)
63
61
60
58
55
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
A
8L
A
11L
A
12L
I/O7L
I/O5L
I/O4L
I/O2L
I/O0L
OE
L
SEM
L
LB
L
66
I/O10L
64
62
59
56
49
50
47
44
43
40
39
37
A
6L
A
9L
A
10L
I/O8L
I/O6L
I/O3L
I/O1L
A13L
UBL
CEL
67
I/O11L
65
57
53
52
41
A
7L
R/W
L
GND
V
CC
A
5L
I/O9L
69
I/O13L
68
I/O12L
71
I/O14L
70
38
A
3L
A
4L
72
I/O15L
73
33
35
34
A
1L
BUSY
L
V
CC
A
0L
IDT7026
G84-3
75
74
32
31
36
84-PIN PGA
TOP VIEW
I/O0R
GND
A
2L
M/S
GND
GND
(3)
76
77
78
28
29
30
V
CC
I/O1R
I/O2R
A
1R
A
0R
3R
6R
BUSY
R
79
80
26
27
A
2R
A
I/O3R
I/O4R
81
83
7
11
12
23
25
A
4R
A
SEMR
I/O5R
I/O7R
GND
GND
82
1
3
2
5
8
10
14
17
20
18
22
24
A
9R
A
7R
A
5R
A12R
I/O6R
I/O9R
I/O10R I/O13R I/O15R R/WR
UBR
84
4
6
9
15
13
16
19
21
I/O8R
I/O11R I/O12R I/O14R
OER
LBR
CER
A
11R
A10R
A13R
A8R
A
B
C
D
E
F
G
H
J
K
L
2939 drw 03
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
PIN NAMES
Left Port
Right Port
CER
Names
Chip Enable
Grade
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
CEL
Military
0V
5.0V ± 10%
R/WL
R/WR
Read/Write Enable
Output Enable
Address
Commercial
0V
5.0V ± 10%
OEL
OER
2939 tbl 02
A0L – A13L
I/O0L – I/O15L
SEML
A0R – A13R
I/O0R – I/O15R
SEMR
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Busy Flag
UBL
UBR
LBL
LBR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
2939 tbl 01
6.17
3
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
X
OE UB
LB
X
H
H
L
SEM
H
I/O8-15
I/O0-7
Mode
H
X
X
X
X
X
L
X
H
L
High-Z
High-Z
DATAIN
High-Z
High-Z Deselected: Power-Down
High-Z Both Bytes Deselected
High-Z Write to Upper Byte Only
DATAIN Write to Lower Byte Only
X
X
H
L
L
H
L
L
H
L
H
L
L
L
H
DATAIN DATAIN Write to Both Bytes
DATAOUT High-Z Read Upper Byte Only
High-Z DATAOUT Read Lower Byte Only
DATAOUT DATAOUT Read Both Bytes
L
H
H
H
X
L
H
L
H
L
L
L
H
L
H
L
L
H
X
H
X
X
X
High-Z
High-Z Outputs Disabled
NOTE:
2939 tbl 03
1. A0L — A13L ≠ A0R — A13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
H
OE
UB
X
LB
X
SEM
I/O8-15
I/O0-7
Mode
H
L
L
L
L
L
L
L
L
DATAOUT DATAOUT Read Data in Semaphore Flag
DATAOUT DATAOUT Read Data in Semaphore Flag
DATAIN DATAIN Write I/O0 into Semaphore Flag
DATAIN DATAIN Write I/O0 into Semaphore Flag
X
H
H
X
H
X
H
X
X
X
X
X
H
L
H
X
L
L
X
X
—
—
—
—
Not Allowed
Not Allowed
X
L
NOTE:
2939 tbl 04
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING
Symbol
Rating
Commercial
Military
Unit
CONDTIONS
Symbol
(2)
Parameter
Min. Typ. Max. Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
with Respect
to GND
VCC
Supply Voltage
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
GND
TA
Operating
Temperature
0 to +70
–55 to +125 °C
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
–0.5(1)
—
—
6.0(2)
V
V
0.8
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
NOTES:
2939 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
Storage
Temperature
DC Output
Current
50
50
mA
NOTES:
2939 tbl 05
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol
Parameter
Conditions(2) Max. Unit
CIN
Input Capacitance
VIN = 3dv
9
pF
pF
COUT
Output
VOUT = 3dv
10
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
Capacitance
NOTES:
2939 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.17
4
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7026S
IDT7026L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
Min.
Max.
10
Min.
—
Max.
5
Unit
|ILI|
—
—
µA
|ILO|
VOL
VOH
10
—
5
µA
—
0.4
—
—
0.4
—
V
Output High Voltage
IOH = –4mA
2.4
2.4
V
NOTE:
1. At Vcc = 2.0V, input leakages are undefined.
2939 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7026X20
7026X25
Test
Com'l. Only
Typ.(2) Max. Typ.(2) Max. Unit
Symbol
Parameter
Condition
Version
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
MIL.
S
L
—
—
—
—
170
170
345 mA
305
(3)
(Both Ports Active)
f = fMAX
COM’L.
MIL.
S
L
180
180
315
275
170
170
305
265
ISB1
ISB2
ISB3
Standby Current
(Both Ports — TTL
CER = CEL = VIH
SEMR = SEML = VIH
S
L
—
—
—
—
25
25
100 mA
80
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
30
30
85
60
25
25
85
60
(5)
Standby Current
(One Port — TTL
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
S
L
—
—
—
—
105
105
230 mA
200
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
115
115
210
180
105
105
200
170
SEMR = SEML = VIH
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
S
L
—
—
—
—
1.0
0.2
30 mA
10
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM’L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC - 0.2V
ISB4
Full Standby Current
(One Port — All
CE"A" < 0.2V and
MIL.
S
L
—
—
—
—
100
100
200 mA
175
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or
COM’L.
S
L
110
110
185
160
100
100
170
145
VIN < 0.2V
Active Port Outputs Open,
(3)
f = fMAX
NOTES:
2939 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.17
5
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Con't.) (VCC = 5.0V ± 10%)
7026X35
7026X55
Test
Symbol
Parameter
Condition
Version
MIL.
Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
S
L
160
160
335
295
150
150
310 mA
270
(3)
(Both Ports Active)
f = fMAX
COM’L.
MIL.
S
L
160
160
295
255
150
150
270
230
ISB1
ISB2
ISB3
Standby Current
(Both Ports — TTL
CEL = CER = VIH
SEMR = SEML = VIH
S
L
20
20
100
80
13
13
100 mA
80
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
20
20
85
60
13
13
85
60
(5)
Standby Current
(One Port — TTL
CE"A"=VIL and CE"B"=VIH
Active Port Outputs Open,
S
L
95
95
215
185
85
85
195 mA
165
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
95
95
185
155
85
85
165
135
SEMR = SEML = VIH
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
S
L
1.0
0.2
30
10
1.0
0.2
30 mA
10
CMOS Level Inputs)
VIN > VCC - 0.2V or
COM’L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
VIN < 0.2V, f = 0(4)
SEMR = SEML >VCC - 0.2V
ISB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
CE"A" < 0.2V and
MIL.
S
L
90
90
190
165
80
80
175 mA
150
CE"B" > VCC - 0.2V(5)
SEMR = SEML >VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V
COM’L.
S
L
90
90
160
135
80
80
135 mA
110
Active Port Outputs Open,
(3)
f = fMAX
NOTES:
2939 tbl 10
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.17
6
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
5V
5V
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
893Ω
893Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
Input Timing Reference Levels
Output Reference Levels
DATAOUT
1.5V
347Ω
30pF
347Ω
5pF
Output Load
Figures 1 and 2
2939 tbl 11
2939 drw 04
2939 drw 05
Figure 1. AC Output Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7026X20
Com'l. Only
IDT7026X25
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
20
—
—
—
—
3
—
20
20
20
12
—
—
12
—
20
—
20
25
—
—
—
—
3
—
25
25
25
13
—
—
15
—
25
—
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Chip Enable Access Time(3)
Byte Enable Access Time(3)
tACE
tABE
tAOE
tOH
tLZ
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
3
3
tHZ
—
0
—
0
tPU
tPD
—
10
—
—
12
—
tSOP
tSAA
IDT7026X35
IDT7026X55
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
35
—
—
—
—
3
—
35
35
35
20
—
—
15
—
35
—
35
55
—
—
—
—
3
—
55
55
55
30
—
—
25
—
50
—
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACE
tABE
tAOE
tOH
tLZ
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
3
3
tHZ
Output High-Z Time(1, 2)
—
0
—
0
tPU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
tPD
—
15
—
—
15
—
tSOP
tSAA
ns
NOTES:
2939 tbl 12
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.17
7
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
tOH
(1)
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3, 4)
2939 drw 06
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
t
PU
tPD
I
CC
50%
50%
ISB
2939 drw 07
6.17
8
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE (5)
IDT7026X20
Com'l. Only
IDT7026X25
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
Chip Enable to End-of-Write(3)
20
15
15
0
—
—
—
—
—
—
—
12
—
12
—
—
—
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
15
0
20
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
15
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
0
—
0
5
5
5
5
IDT7026X35
IDT7026X55
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
—
—
—
—
—
—
—
15
—
15
—
—
—
55
45
45
0
—
—
—
—
—
—
—
25
—
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
25
0
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
30
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
0
—
0
5
5
5
5
NOTES:
2939 tbl 13
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.17
9
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM (9)
UB or LB (9)
R/W
(3)
(2)
(6)
tWR
tAS
tWP
(7)
t
OW
tWZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2939 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5)
tWC
ADDRESS
tAW
CE or SEM(9)
UB or LB (9)
(6)
AS
(3)
WR
(2)
EW
t
t
t
R/W
tDW
tDH
DATAIN
2939 drw 09
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.17
10
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tACE
tWR
tAW
tEW
SEM
tSOP
tDW
DATAIN
VALID
DATAOUT
I/O0
(2)
VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2939 drw 10
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
“A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2939 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.17
11
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7026X20
Com'l. Only
IDT7026X25
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
—
—
—
5
20
20
20
17
—
30
—
—
—
—
—
5
20
20
20
17
—
30
—
ns
ns
ns
ns
ns
ns
ns
—
15
—
17
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
ns
ns
15
17
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
45
30
—
—
50
35
ns
ns
IDT7026X35
IDT7026X55
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
—
—
—
—
5
20
20
20
20
—
35
—
—
—
—
—
5
45
40
40
35
—
40
—
ns
ns
ns
ns
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
25
—
25
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
ns
ns
25
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
60
45
—
—
80
65
ns
tDDD
ns
NOTES:
2939 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S= VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
6.17
12
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)
t
WC
MATCH
ADDR"A"
R/W"A"
t
WP
t
DW
tDH
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
tBAA
t
BDA
t
BDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
NOTES:
2939 drw 12
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
2939 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
6.17
13
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2939 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
2939 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
2683 tbl 16
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
6.17
14
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION WITH BUSY LOGIC
TRUTH TABLE IV —
MASTER/SLAVE ARRAYS
ADDRESS BUSY ARBITRATION
When expanding an IDT7026 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7026 RAM the busy pin is
an output if the part is used as a master (M/Spin = H), and the
busy pin is an input if the part used as a slave (M/Spin = L) as
shown in Figure 3.
Inputs
Outputs
A0L-A13L
CER A0R-A13R BUSYL
(1)
(1)
CEL
BUSYR
Function
Normal
X
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
L
MATCH
H
H
Normal
Write Inhibit(3)
MATCH
(2)
(2)
NOTES:
2683 tbl 17
1. Pins BUSYL and BUSYR are both outputs when the part is configured as
a master. Both are inputs when configured as a slave. BUSYX outputs on
the IDT7026 are push pull, not open drain outputs. On slaves the BUSYX
input internally inhibits writes.
2. LOW if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. HIGH if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs
cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving LOW regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving LOW regard-
less of actual logic level on the pin.
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY
L
BUSY
R
BUSY
L
BUSY
R
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
R
BUSY
L
BUSYL
BUSY
R
BUSYR
BUSY
L
2939 drw 16
FUNCTIONAL DESCRIPTION
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
The IDT7026 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreads
or writes to any location in memory. The IDT7026 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enableandaddresssignalsonly.Itignoreswhetheranaccess
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiatedwitheithertheR/Wsignalorthebyteenables. Failure
to observe this timing can result in a glitched internal write
inhibit signal and corrupted data in the slave.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signalstheothersidethattheRAMis“Busy”. Thebusypincan
thenbeusedtostalltheaccessuntiltheoperationon theother
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/Spin. Once in slave mode theBUSY
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the BUSY pins HIGH. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port LOW.
SEMAPHORES
The IDT7026 is an extremely fast Dual-Port 16K x 16
CMOS Static RAM with an additional 8 address locations
dedicatedtobinarysemaphoreflags. Theseflagsalloweither
processorontheleftorrightsideoftheDual-PortRAMtoclaim
a privilege over the other processor for functions defined by
the system designer’s software. As an example, the sema-
phore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The busy outputs on the IDT 7026 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
oftherightport. Bothportsareidenticalinfunctiontostandard
6.17
15
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMOS Static RAM and can be read from, or written to, at the address space is accessed by placing a low input on the SEM
same time with the only possible conflict arising from the pin (which acts as a chip select for the semaphore flags) and
simultaneous writing of, or a simultaneous READ/WRITE of, using the other control pins (Address, OE, and R/W) as they
anon-semaphorelocation. Semaphoresareprotectedagainst would be used in accessing a standard Static RAM. Each of
such ambiguous situations and may be used by the system the flags has a unique address which can be accessed by
program to avoid any conflicts in the non-semaphore portion eithersidethroughaddresspinsA0–A2. Whenaccessingthe
of the Dual-Port RAM. These devices have an automatic semaphores, none of the other address pins has any effect.
power-down feature controlled by CE, the Dual-Port RAM
When writing to a semaphore, only data pin D0 is used. If
enable, and SEM, the semaphore enable. The CE and SEM a low level is written into an unused semaphore location, that
pins control on-chip power down circuitry that permits the flagwillbesettoazeroonthatsideandaoneontheotherside
respective port to go into standby mode when not selected. (see Table III). That semaphore can now only be modified by
This is the condition which is shown in Truth Table where CE thesideshowingthezero. Whenaoneiswrittenintothesame
and SEM are both HIGH.
locationfromthesameside,theflagwillbesettoaoneforboth
Systems which can best use the IDT7026 contain multiple sides (unless a semaphore request from the other side is
processors or controllers and are typically very high-speed pending)andthencanbewrittentobybothsides.Thefactthat
systems which are software controlled or software intensive. the side which is able to write a zero into a semaphore
These systems can benefit from a performance increase subsequently locks out writes from the other side is what
offered by the IDT7026's hardware semaphores, which pro- makes semaphore flags useful in interprocessor communica-
vide a lockout mechanism without requiring complex pro- tions. (Athoroughdiscussingontheuseofthisfeaturefollows
gramming.
shortly.) A zero written into the same location from the other
Software handshaking between processors offers the side will be stored in the semaphore request latch for that side
maximum in system flexibility by permitting shared resources until the semaphore is freed by the first side.
to be allocated in varying configurations. The IDT7026 does
When a semaphore flag is read, its value is spread into all
not use its semaphore flags to control any resources through data bits so that a flag that is a one reads as a one in all data
hardware, thus allowing the system designer total flexibility in bits and a flag containing a zero reads as all zeros. The read
system architecture.
valueislatchedintooneside’soutputregisterwhenthatside's
An advantage of using semaphores rather than the more semaphore select (SEM) and output enable (OE) signals go
common methods of hardware arbitration is that wait states active. This serves to disallow the semaphore from changing
are never incurred in either processor. This can prove to be state in the middle of a read cycle due to a write cycle from the
a major advantage in very high-speed systems.
other side. Because of this latch, a repeated read of a
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
HOW THE SEMAPHORE FLAGS WORK
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema-
phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW
and the other side HIGH. This condition will continue until a
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active LOW. A token is re-
quested by writing a zero into a semaphore latch and is
released when the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7026 in a
separate memory space from the Dual-Port RAM. This
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success-
fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 8K. Mean-
while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain
controlofthesecond8Ksectionbywriting,thenreadingazero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
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Figure 4. IDT7026 Semaphore Logic
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resourcesintoeightparts.Semaphorescanevenbeassigned
different meanings on different sides rather than being given
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
ofmemoryduringatransferandtheI/Odevicecannottolerate
any wait states. With the use of semaphores, once the two
deviceshasdeterminedwhichmemoryareawas“off-limits”to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
one is written to the same semaphore request latch. Should
the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay LOW until
its semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
applicationoneprocessormayberesponsibleforbuildingand
updatingadatastructure. Theotherprocessorthenreadsand
interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7026’s Dual-Port
RAM. Say the 16K x 16 RAM was to be divided into two 8K
x 16 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
usedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
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IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
G
J
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
20
25
35
55
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
7026
256K (16K x 16) Dual-Port
RAM
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6.17
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