IDT7052S25PFI [IDT]
Four-Port SRAM, 2KX8, 25ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-120;
| 型号： | IDT7052S25PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Four-Port SRAM, 2KX8, 25ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-120 静态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7052S/L
HIGH-SPEED
2K x 8 FourPortTM
STATIC RAM
Features
◆
◆
Battery backup operation—2V data retention
TTL-compatible; single 5V (±10%) power supply
High-speed access
◆
◆
– Commercial:20/25/35ns (max.)
– Industrial:25ns (max.)
Available in 120 pin and 132 pin Thin Quad Flatpacks and
108 pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
– Military:25/35ns(max.)
Low-power operation
◆
◆
◆
– IDT7052S
Active:750mW(typ.)
Standby: 7.5mW (typ.)
– IDT7052L
◆
Green parts available, see ordering information
Active:750mW(typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
Description
TheIDT7052isahigh-speed2Kx8FourPort™StaticRAMdesigned
to be used in systems where multiple access into a common RAM is
required.ThisFourPortStaticRAMoffersincreasedsystemperformance
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess
is requiredinthe same cycle.
◆
◆
P1, P2, P3, P4
◆
Versatile control for write-inhibit: separate BUSY input to
control write-inhibit for each of the four ports
FunctionalBlockDiagram
R/WP1
CEP1
R/WP4
CEP4
OEP1
OEP4
COLUMN
I/O
COLUMN
I/O0P1-I/O7P1
BUSYP1
I/O0P4-I/O7P4
I/O
BUSYP4
PORT 1
PORT 4
ADDRESS
DECODE
LOGIC
ADDRESS
A0P1 - A10P1
A0P4 - A10P4
DECODE
LOGIC
MEMORY
ARRAY
PORT 2
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
A0P2 - A10P2
A0P3 - A10P3
BUSYP2
BUSYP3
COLUMN
I/O
COLUMN
I/O
I/O0P2-I/O7P2
I/O0P3-I/O7P3
OEP2
OEP3
CEP2
R/WP2
CEP3
R/WP3
2674 drw 01
JULY 2006
1
DSC 2674/12
©2006IntegratedDeviceTechnology,Inc.
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
TheIDT7052is alsodesignedtobeusedinsystems whereon-chip
Fabricated using IDT’s CMOS high-performance technology, this
hardware port arbitration is not needed. This part lends itself to those FourPortSRAMtypicallyoperatesononly750mWofpower.Low-power
systems whichcannottoleratewaitstates oraredesignedtobeableto (L)versionsofferbatterybackupdataretentioncapability,witheachport
externallyarbitrateorwithstandcontentionwhenallportssimultaneously typicallyconsuming50µWfroma2Vbattery.
accessthesameFourPortRAMlocation.
TheIDT7052ispackagedinaceramic108-pinPinGridArray(PGA),
TheIDT7052providesfourindependentportswithseparatecontrol, 120-pinThinQuadFlatpack(TQFP)and132-pinPlasticQuadFlatpack
address,andI/Opinsthatpermitindependent, asynchronousaccessfor (PQF).Militarygradeproductismanufacturedincompliancewiththelatest
readsorwritestoanylocationinmemory.Itistheuser’sresponsibilityto revision of MIL-PRF-38535 QML, making it ideally suited to military
ensuredataintegritywhensimultaneouslyaccessingthesamememory temperatureapplicationsdemandingthehighestlevelofperformanceand
locationfromallports.Anautomaticpowerdownfeature,controlledbyCE, reliability.
permitstheon-chipcircuitryofeachporttoenteraverylowpowerstandby
powermode.
PinConfigurations(1,2,3)
11/07/01
81
80
83
86
88
91
94
97
77
78
82
85
89
93
98
74
76
79
72
73
75
69
70
71
68
67
66
65
64
62
63
61
58
60
59
55
52
48
44
57
56
51
49
46
43
40
37
34
32
29
54
R/W
P2
NC
A
P2
7
A
P2
5
A
P2
3
A
P2
0
A
P3
3
A
P3
5
A
P3
7
R/W
P3
NC
A
P3
0
12
11
84
53
BUSY
OE
P2
OE
P3
BUSY
A
P2
8
A10
A4
A
1
A1
A
P3
4
A10
A
P3
8
P2
P3
P2
P2
P2
P3
P3
87
90
92
95
96
99
50
47
45
42
41
38
CE
A2
A
1
A
9
A
6
A2
A2
A
6
A
P3
9
A1
A2
10
09
08
07
06
05
04
03
02
01
CE
P3
P1
P1
P2
P2
P2
P3
P3
P4
P4
A5
A3
A0
P1
A
P4
0
A3
A5
P4
P1
P1
P4
A
6
A
P1
4
A
P4
4
A6
A10
P4
A
10
P1
P1
P4
8
GND
A
A7
P4
A8
A7
P1
VCC
IDT7052G
G108-1(4)
P4
P1
39
CE
P4
A9
P4
NC
CE
P1
A9
NC
108-Pin PGA
Top View(5)
P1
100
102
35
OE
P4
OE
P1
GND
R/W
R/W
I/O
0
P4
P1
P1
101
103
106
31
36
BUSY
7
BUSY
GND
GND
I/O
I/O
1
P1
P1
P4
P4
104
105
1
5
6
4
7
8
12
17
21
25
22
20
28
24
23
33
I/O
5
I/O
2
P1
I/O
3
P1
I/O
6
I/O
2
I/O
6
GND
V
CC
V
CC
GND
VCC
VCC
P4
P1
P4
P4
107
2
3
10
13
16
19
30
I/O
4
P1
I/O
7
P1
I/O
0
I/O
2
I/O
4
I/O
6
I/O
3
I/O
5
I/O
P3
7
I/O
3
P4
I/O
P4
4
I/O
P3
1
P2
P2
P2
P2
P3
P3
108
9
11
14
15
18
26
27
I/O
P2
1
I/O
P2
5
I/O
P3
4
I/O
P1
5
NC
B
I/O
P2
3
I/O
P2
7
I/O
P3
0
I/O
P3
2
I/O
P3
6
I/O
P4
0
I/O1
P4
A
C
D
E
F
G
H
J
K
L
M
2674 drw 02
INDEX
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
11/07/01
1
17
117
116
N/C
OEP2
18
N/C
BUSYP3
BUSYP2
N/C
N/C
A
A
A
A
A
A
A
0P4
1P4
2P4
3P4
4P4
5P4
6P4
A0P1
A1P1
A2P1
A3P1
A4P1
A5P1
A6P1
N/C
N/C
10P1
A
GND
A
A
A
10P4
A
VCC
7P4
8P4
9P4
A
A
A
7P1
8P1
9P1
IDT7052PQF
PQ132-1(4)
N/C
132-Pin Plastic Quad Flatpack
Top View(5,6)
N/C
CEP1
R/WP1
OEP1
BUSYP1
N/C
CEP4
R/WP4
OEP4
BUSYP4
N/C
GND
I/O0P1
I/O1P1
I/O2P1
I/O3P1
GND
N/C
I/O7P4
I/O6P4
I/O5P4
GND
I/O4P4
I/O3P4
I/O2P4
N/C
N/C
I/O4P1
I/O5P1
N/C
50
51
84
N/C
N/C
83
2674 drw 03
11/07/01
1
2
3
4
5
6
7
8
N/C
N/C
BUSYP3
N/C
N/C
OEP2
BUSYP2
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A0P4
A1P4
A2P4
A3P4
A4P4
A5P4
A6P4
A10P4
A0P1
A1P1
A2P1
A3P1
A4P1
A5P1
A6P1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
A
10P1
A7P4
A8PR
A9P4
VCC
IDT7052PF
PN120-1(4)
A
A
A
7P1
8P1
9P1
N/C
120-Pin Thin Quad Flatpack
Top View(5)
CEP4
R/WP4
OEP4
BUSYP4
GND
I/O7P4
I/O6P4
I/O5P4
GND
I/O4P4
I/O3P4
I/O2PR
N/C
N/C
CEP1
R/WP1
OEP1
BUSYP1
I/O0P1
I/O1P1
I/O2P1
I/O3P1
GND
I/O4P1
I/O5P1
N/C
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PQ132-1 package body is approximately
.95 in x .95 in x .14 in.
N/C
N/C
PN120-1 package body is approximately
14mm x 14mm x 1.4mm.
2674 drw 04
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
6. The side of the package containing pin1 may have a bevelled edge in place of the indicator dot..
3
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
PinConfigurations(1,2)
AbsoluteMaximumRatings(1)
Symbol
Pin Name
Symbol
Rating
Commercial
& Industrial
Military
Unit
A
0
P1 - A10 P1
Address Lines - Port 1
Address Lines - Port 2
Address Lines - Port 3
Address Lines - Port 4
Data I/O - Port 1
(2)
V
TERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
A0
P2 - A10P2
P3 - A10 P3
P4 - A10 P4
A0
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
T
BIAS
A0
I/O
I/O
I/O
0
P1 - I/O
P2 - I/O
P3 - I/O
7
P1
P2
P3
P4
Storage
Temperature
TSTG
0
7
Data I/O - Port 2
mA
IOUT
DC Output Current
0
7
Data I/O - Port 3
2674 tbl 02
I/O0
P4 - I/O
7
Data I/O - Port 4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
R/W P1
R/W P2
R/W P3
R/W P4
GND
Read/Write - Port 1
Read/Write - Port 2
Read/Write - Port 3
Read/Write - Port 4
Ground
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
CE P1
Chip Enable - Port 1
Chip Enable - Port 2
Chip Enable - Port 3
Chip Enable - Port 4
Output Enable - Port 1
Output Enable - Port 2
Output Enable - Port 3
Output Enable - Port 4
Write Disable - Port 1
Write Disable - Port 2
Write Disable - Port 3
Write Disable - Port 4
Power
CE P2
MaximumOperating
CE P3
Temperature and Supply Voltage(1)
CE P4
Ambient
OE P1
Grade
Temperature
-55OC to+125OC
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
OE P2
Military
5.0V
+
+
+
10%
OE P3
Commercial
Industrial
0V
5.0V
5.0V
10%
10%
OE P4
0V
BUSY P1
BUSY P2
BUSY P3
BUSY P4
2674 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
VCC
RecommendedDCOperating
Conditions
2674 tbl 01
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ.
Max. Unit
VCC
4.5
5.0
5.5
0
V
V
V
Capacitance(1)
0
0
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
(TA = +25°C, f = 1.0MHz) TQFP only
____
-0.5(1)
V
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 0V
OUT = 0V
Max. Unit
____
VIL
2674 tbl 05
CIN
V
9
pF
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
COUT
V
10
pF
2674 tbl 03
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
the output signals switch from 0V to 3V or from 3V to 0V.
4
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%)
7052X20
7052X25
Com'l, Ind
& Military
7052X35
Com'l &
Military
Com'l Only
Symbol
Parameter
Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC1
Operating Power
Supply Current
(All Ports Active)
COM'L.
S
150
150
300
250
150
150
300
250
150
150
300
250
CE = VIL
mA
L
Outputs Disabled
(3)
f = 0
____
____
____
____
MIL. &
IND.
S
L
150
150
360
300
150
150
360
300
I
CC2
Dynamic Operating
Current
COM'L.
S
L
240
210
370
325
225
195
350
305
210
180
335
290
CE = VIL
mA
mA
Outputs Disabled
(4)
(All Ports Active)
f = fMAX
____
____
____
____
MIL. &
IND.
S
L
225
195
400
340
210
180
395
330
I
SB
Standby Current
(All Ports - TTL Level
Inputs)
COM'L.
S
L
70
60
95
80
45
40
85
70
40
35
75
60
CE = VIH
(4)
f = fMAX
____
____
____
____
MIL. &
IND.
S
L
45
40
115
85
40
35
110
80
ISB1
Full Standby Current
(All Ports - All CMOS
Level Inputs)
All Ports
COM'L.
S
L
1.5
0.3
15
1.5
1.5
0.3
15
1.5
1.5
0.3
15
1.5
mA
CE > VCC - 0.2V
V
IN > VCC - 0.2V or
____
____
____
____
IN < 0.2V, f = 0(3)
MIL. &
IND.
S
L
1.5
0.3
30
4.5
1.5
0.3
30
4.5
V
2674 tbl 06
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C and are not production tested.
3. f = 0 means no address or control lines change.
4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
5. For the case of one port, divide the appropriate current above by four.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7052S
7052L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
CE = VIH, VOUT = 0V to VCC
VOL
IOL = 4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2674 tbl 07
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
5
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics Over All Temperature Ranges(4)
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
V
DR
V
VCC = 2
V
2.0
___
ICCDR
Data Retention Current
µA
CE > VHC
IN > VHC or < VLC
Com'l.
Mil. & Ind.
25
600
___
V
25
1800
(3)
CDR
___
___
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
___
___
t
R
t
RC
ns
2674 tbl 08a
NOTES:
1. VCC = 2V, TA = +25°C
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
4. Industrial temperature: For other speeds, packages and powers contact your sales office.
Low VCCData Retention Waveform
DATA RETENTION MODE
VCC
≥
4.5V
VDR
4.5V
2V
t
CDR
tR
VDR
VIH
CE
VIH
2674 drw 05
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
5V
5V
Input Rise/Fall Times
893Ω
893Ω
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
347Ω
DATAOUT
347Ω
1.5V
5pF*
Figures 1 and 2
30pF
2674 tbl 08b
,
2674 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
6
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(3)
7052X20
Com'l Only
7052X25
Com'l, Ind
& Military
7052X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
Chip Enable Access Time
Output Enable Access Time
20
20
25
25
35
35
____
____
____
____
____
____
t
t
10
15
25
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
0
0
0
____
____
____
t
5
5
5
Output High-Z Time(1,2)
12
15
15
____
____
.____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0
____
____
____
____
____
____
t
20
25
35
ns
2674 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2)
2. This parameter is guaranteed by device characterization but is not production tested.
3. 'X' in part number indicates power rating (S or L)
Timing Waveform of Read Cycle No. 1, Any Port(1)
tRC
ADDRESS
tAA
tOH
t
OH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2674 drw 07
NOTES:
1. R/W = VIH, OE = VIL and CE = VIL.
Timing Waveform of Read Cycle No. 2, Any Port(1,2)
tACE
CE
tAOE
tHZ
OE
tLZ
tHZ
DATAOUT
VALID DATA
tLZ
tPU
tPD
I
CC
CURRENT
50%
50%
I
SB
2674 drw 08
NOTES:
1. R/W = VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE transition LOW.
7
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(7)
7052X20
Com'l Only
7052X25
Com'l &
Military
7052X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
WDD
WDD
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time
t
t
(3)
t
Write Pulse Width
15
0
20
0
30
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time
t
15
15
20
____
____
____
t
15
15
15
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2)
Write Pulse to Data Delay(4)
12
15
15
____
____
____
t
0
0
0
____
____
____
t
35
30
45
35
55
45
Write Data Valid to Read Data Delay(4)
____
____
____
t
BUSY INPUT TIMING
Write to BUSY
Write Hold After BUSY
(5)
____
____
____
____
____
____
t
WB
0
0
0
ns
(6)
tWH
15
15
20
ns
2674 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers
to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8).
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
7. 'X' in part number indicates power rating.
8
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8)
tWC
ADDRESS
(6)
AS
t
OE
(3)
tAW
tWR
(9)
CE
(7)
(2)
tHZ
tWP
R/W
(7)
(7)
tWZ
tHZ
tLZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2674 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
tWC
ADDRESS
tAW
CE(9)
(3)
(6)
AS
(2)
t
tEW
tWR
R/W
tDW
tDH
DATAIN
2674 drw 10
NOTES:
1. R/W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production
tested.
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed
on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read(1,2,3)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
DATAIN"A"
ADDR"B"
VALID
MATCH
tWDD
VALID
DATA"B"
tDDD
NOTES:
2674 drw 11
1. Assume BUSY input = VIH and CE = VIL for the writing port.
2. OE = VIL for the reading ports.
3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.
Timing Waveform of Write with BUSY Input
t
WP
R/W"A"
BUSY"B"
R/W"B"
tWH
t
WB
(1)
,
2674 drw 12
NOTES:
1. BUSY is asserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH.
Truth Table I – Read/Write Control(3)
FunctionalDescription
TheIDT7052providesfourportswithseparatecontrol,address,and
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
in memory. These devices have an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permitstherespectiveporttogointostandbymodewhennotselected(CE
= VIH). When a port is enabled, access to the entire memory array is
permitted.EachporthasitsownOutputEnablecontrol(OE).Intheread
mode, the port’s OE turns on the output drivers when set LOW. READ/
WRITEconditionsareillustratedinthetablebelow.
Any Port(1)
R/W
D0-7
Function
CE
OE
X
H
X
Z
Z
Port Deselected: Power-Down
CEP1=CEP2=CEP3=CEP4=VIH
X
H
X
Power Down Mode ISB or ISB1
L
H
X
L
L
X
X
L
DATAIN
Data on port written into memory(2)
DATAOUT Data in memory output on port
Outputs Disabled
H
Z
2674 tbl 11
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance
2. If BUSY = VIL, write is blocked.
3. For valid write operation, no more than one port can write to the same address
location at the same time.
10
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
A
IDT
XXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C
Military (-55°C to +125°C)
I(1)
B
Compliant to MIL-PRF-38535 QML
G(2)
Green
G
PQF
PF
108-Pin Pin Grid Array (G108-1)
132-Pin Plastic Quad Flatpack (PQ132-1)
120-Pin Thin Quad Plastic Flatpack (PN120-1)
,
20
25
35
Commercial Only
Commercial, Industrial & Military
Commercial & Military
Speed in nanoseconds
L
S
Low Power
Standard Power
16K (2K x 8) FourPort RAM
7052
2674 drw 13
NOTE:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
1/18/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmetictypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/4/99:
Page1 CorrectedDSCnumber
11/10/99:
11/18/99:
5/23/00:
Replaced IDT logo
Page 10 FixedtypoincaptionforBUSY Inputwaveform
Page 4 Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
10/22/01:
07/24/06:
Pages 2 & 3 Added date revision for pin configurations
Page 5, 7& 8 AddedIndustrialtemptocolumnheadingfor25ns speedtoDC&ACElectricalCharacteristics
Page 11 AddedIndustrialtempofferingto25nsorderinginformation
Page 4, 5, 7& 8 RemovedIndustrialtempfootnote fromalltables
Page 1 & 11 Replace TM logo with ® logo
Page 1 Addedgreenavailabilitytofeatures
Page 11 Addedgreenindicatortoorderinginformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
11
6.42
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