IDT7052S35G [IDT]

Four-Port SRAM, 2KX8, 35ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108;


型号：	IDT7052S35G
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Four-Port SRAM, 2KX8, 35ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, PGA-108 静态存储器内存集成电路
文件：	总11页 (文件大小：119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7052S/L

HIGH-SPEED

2K x 8 FourPort^TM

STATIC RAM

Features

◆

TTL-compatible; single 5V (±10%) power supply

Available in 120 pin and 132 pin Thin Quad Flatpacks and

108 pin PGA

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

High-speed access

– Military:25/35ns(max.)

◆

– Commercial:20/25/35ns (max.)

Low-power operation

◆

– IDT7052S

Active:750mW(typ.)

Standby: 7.5mW (typ.)

– IDT7052L

Description

Active:750mW(typ.)

Standby: 1.5mW (typ.)

True FourPort memory cells which allow simultaneous

TheIDT7052isahigh-speed2Kx8FourPort™StaticRAMdesigned

to be used in systems where multiple access into a common RAM is

required.ThisFourPortStaticRAMoffersincreasedsystemperformance

inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand

alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess

is requiredinthe same cycle.

◆

access of the same memory locations

Fully asynchronous operation from each of the four ports:

◆

P1, P2, P3, P4

◆

Versatile control for write-inhibit: separate BUSY input to

TheIDT7052is alsodesignedtobeusedinsystems whereon-chip

hardware port arbitration is not needed. This part lends itself to those

control write-inhibit for each of the four ports

Battery backup operation—2V data retention

◆

FunctionalBlockDiagram

R/WP1

CEP1

R/WP4

CEP4

OEP1

OEP4

COLUMN

I/O

COLUMN

I/O0P1-I/O7P1

BUSYP1

I/O0P4-I/O7P4

I/O

BUSYP4

PORT 1

PORT 4

ADDRESS

DECODE

LOGIC

ADDRESS

DECODE

LOGIC

A0P1 - A10P1

A0P4 - A10P4

MEMORY

ARRAY

PORT 2

ADDRESS

DECODE

LOGIC

PORT 3

ADDRESS

DECODE

LOGIC

A0P2 - A10P2

A0P3 - A10P3

BUSYP2

BUSYP3

COLUMN

I/O

COLUMN

I/O

I/O0P2-I/O7P2

I/O0P3-I/O7P3

OEP2

OEP3

CEP2

CEP3

R/WP3

R/WP2

2674 drw 01

JUNE 1999

DSC 2674/9

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

systems whichcannottoleratewaitstates oraredesignedtobeableto

Fabricated using IDT’s CMOS high-performance technology, this

externallyarbitrateorwithstandcontentionwhenallportssimultaneously FourPortSRAMtypicallyoperatesononly750mWofpower.Low-power

accessthesameFourPortRAMlocation. (L)versionsofferbatterybackupdataretentioncapability,witheachport

TheIDT7052providesfourindependentportswithseparatecontrol, typicallyconsuming50µWfroma2Vbattery.

address,andI/Opinsthatpermitindependent, asynchronousaccessfor

TheIDT7052ispackagedinaceramic108-pinPinGridArray(PGA),

readsorwritestoanylocationinmemory.Itistheuser’sresponsibilityto 120-pinThinQuadFlatpack(TQFP)and132-pinPlasticQuadFlatpack

ensuredataintegritywhensimultaneouslyaccessingthesamememory (PQF).Militarygradeproductismanufacturedincompliancewiththelatest

locationfromallports.Anautomaticpowerdownfeature,controlledbyCE, revision of MIL-PRF-38535 QML, making it ideally suited to military

permitstheon-chipcircuitryofeachporttoenteraverylowpowerstandby temperatureapplicationsdemandingthehighestlevelofperformanceand

powermode.

reliability.

PinConfigurations^(1,2,3)

R/W

BUSY

A10

GND

A₇

VCC

IDT7052G

G108-1⁽⁴⁾

108-Pin PGA

Top View⁽⁵⁾

100

102

GND

R/W

I/O0

101

103

106

BUSY

GND

I/O

I/O1

104

105

I/O5

I/O2

I/O3

I/O6

I/O2

I/O6

GND

VCC

GND VCC

VCC

107

I/O4

I/O7

I/O0

I/O2

I/O4

I/O6

I/O3

I/O5

I/O7

I/O3

I/O4

I/O1

108

I/O1

I/O5

I/O4

I/O

2674 drw 02

INDEX

NOTES:

1. All VCC pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. Package body is approximately 1.21 in x 1.21 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

117

116

N/C

OEP2

BUSYP2

N/C

A0P1

A1P1

A2P1

A3P1

A4P1

A5P1

N/C

BUSYP3

N/C

A0P4

A1P4

A2P4

A3P4

A4P4

A5P4

A6P4

N/C

A6P1

N/C

A10P1

VCC

A7P1

A8P1

A10P4

GND

A7P4

A8P4

IDT7052PQF

PQ132-1

(4)

9P4

A9P1

N/C

132-Pin Plastic Quad Flatpack

CEP4

R/WP4

OEP4

BUSYP4

N/C

(5,6)

Top View

CEP1

R/WP1

OEP1

BUSYP1

N/C

GND

I/O0P1

I/O1P1

I/O2P1

I/O3P1

GND

N/C

I/O4P1

I/O5P1

N/C

I/O7P4

I/O6P4

I/O5P4

GND

I/O4P4

I/O3P4

I/O2P4

N/C

2674 drw 03

N/C

BUSY

A0P4

N/C

OEP2

BUSY

1P4

2P4

3P4

4P4

5P4

6P4

10P4

A0P1

1P1

A2P1

A3P1

4P1

A5P1

6P1

A10P1

A7P1

A8P1

GND

7P4

8PR

9P4

IDT7052PF

PN120-1⁽⁴⁾

9P1

N/C

120-Pin Thin Quad Flatpack

Top View⁽⁵⁾

N/C

R/W

R/WP1

OEP1

BUSYP1

I/O0P1

I/O1P1

I/O2P1

BUSY

GND

I/O

7P4

6P4

I/O

5P4

GND

3P1

I/O

4P4

I/O

3P4

2PR

I/O

GND

I/O4P1

I/O5P1

N/C

NOTES:

N/C

1. All VCC pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. PQ132-1 package body is approximately

.95 in x .95 in x .14 in.

N/C

PN120-1 package body is approximately

14mm x 14mm x 1.4mm.

2674 drw 04

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking

6. The side of the package containing pin1 may have a bevelled edge in place of the indicator dot..

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

PinConfigurations^(1,2)

AbsoluteMaximumRatings⁽¹⁾

Symbol

A0 P1 - A10 P1

A P2 - A P2

Pin Name

Symbol

Rating

Commercial

& Industrial

Military

Unit

Address Lines - Port 1

Address Lines - Port 2

Address Lines - Port 3

Address Lines - Port 4

Data I/O - Port 1

(2)

VTERM

Terminal Voltage

with Respect to

GND

-0.5 to +7.0

A0 P3 - A10 P3

A0 P4 - A10 P4

I/O0 P1 - I/O7 P1

I/O0 P2 - I/O7 P2

I/O0 P3 - I/O7 P3

I/O0 P4 - I/O7 P4

R/W P1

Temperature

Under Bias

-55 to +125

-65 to +135

-65 to +150

^oC

TBIAS

TSTG

IOUT

Storage

Temperature

Data I/O - Port 2

DC Output Current

Data I/O - Port 3

2674 tbl 02

Data I/O - Port 4

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

Read/Write - Port 1

Read/Write - Port 2

Read/Write - Port 3

Read/Write - Port 4

Ground

R/W P2

R/W P3

R/W P4

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.

GND

CE P1

Chip Enable - Port 1

Chip Enable - Port 2

Chip Enable - Port 3

Chip Enable - Port 4

Output Enable - Port 1

Output Enable - Port 2

Output Enable - Port 3

Output Enable - Port 4

Write Disable - Port 1

Write Disable - Port 2

Write Disable - Port 3

Write Disable - Port 4

Power

CE P2

MaximumOperating

CE P3

TemperatureandSupplyVoltage^(1,2)

CE P4

Ambient

OE P1

Grade

Temperature

-55^OC to+125^OC

0^OC to +70^OC

-40^OC to +85^OC

GND

Vcc

OE P2

Military

5.0V + 10%

OE P3

Commercial

Industrial

OE P4

5.0V + 10%

BUSY P1

BUSY P2

BUSY P3

BUSY P4

VCC

2674 tbl 04

NOTES:

1. This is the parameter TA.

2. Industrial temperature: for specific speeds, packages and powers, contact your

sales office

RecommendedDCOperating

Conditions

2674 tbl 01

NOTES:

1. All VCC pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply

Symbol

Parameter

Min.

Typ. Max. Unit

VCC

Supply Voltage

4.5

5.0

5.5

Capacitance⁽¹⁾

(TA = +25°C, f = 1.0MHz) TQFP only

GND Ground

VIH

VIL

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

Symbol

C^IN

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

Max. Unit

-0.5⁽¹⁾

____

2674 tbl 05

V^IN= 0V

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

C^OUT

V^OUT= 0V

2674 tbl 03

NOTES:

1. This parameter is determined by device characterization but is not

production tested.

2. 3dV references the interpolated capacitance when the input and

the output signals switch from 0V to 3V or from 3V to 0V.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,5,6)(VCC = 5.0V ± 10%)

7052X20

Com'l Only

7052X25

Com'l &

Military

7052X35

Com'l &

Military

Symbol

Parameter

Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

I^CC1

Operating Power

Supply Current

(All Ports Active)

COM'L.

150

300

250

150

300

250

150

300

250

CE = V^IL

Outputs Open

(3)

f = 0

____

MIL. &

IND.

150

360

300

150

360

300

I^CC2

Dynamic Operating

Current

COM'L.

240

210

370

325

225

195

350

305

210

180

335

290

CE = V^IL

Outputs Open

(4)

(All Ports Active)

f = f^MAX

____

MIL. &

IND.

225

195

400

340

210

180

395

330

I^SB

Standby Current

(All Ports - TTL Level

Inputs)

COM'L.

CE = VIH

(4)

f = f^MAX

____

MIL. &

IND.

115

110

I^SB1

Full Standby Current

(All Ports - All CMOS

Level Inputs)

All Ports

COM'L.

1.5

0.3

1.5

0.3

1.5

0.3

CE > V^CC- 0.2V

V^IN> V^CC- 0.2V or

V^IN< 0.2V, f = 0⁽³⁾

1.5

____

MIL. &

IND.

1.5

0.3

4.5

1.5

0.3

4.5

2674 tbl 06

NOTES:

1. 'X' in part number indicates power rating (S or L).

2. VCC = 5V, TA = +25°C and are not production tested.

3. f = 0 means no address or control lines change.

4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

5. For the case of one port, divide the appropriate current above by four.

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7052S

7052L

Symbol

|I^LI|

Parameter

Test Conditions

V^CC= 5.5V, V^IN= 0V to V^CC

CE = V^IH, V^OUT= 0V to V^CC

I^OL= 4mA

Min.

Max.

Min.

Max.

Unit

µA

(1)

___

Input Leakage Current

___

|I^LO|

Output Leakage Current

Output Low Voltage

Output High Voltage

V^OL

0.4

___

V^OH

I^OH= -4mA

2.4

2674 tbl 07

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

Data Retention Characteristics Over All Temperature Ranges⁽⁴⁾

(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Symbol

V^DR

I^CCDR

Parameter

Test Condition

Min.

Typ.⁽¹⁾

Max.

Unit

___

V^CCfor Data Retention

V^CC= 2V

2.0

___

Data Retention Current

µA

CE > V^HC

Com'l.

600

___

V^IN> V^HCor < V^LC

Mil. & Ind.

1800

(3)

___

t^CDR

Chip Deselect to Data Retention Time

Operation Recovery Time

(3)

(2)

___

t^R

t^RC

2674 tbl 08a

NOTES:

1. VCC = 2V, TA = +25°C

2. tRC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

4. Industrial temperature: For other speeds, packages and powers contact your sales office.

Low VCC Data Retention Waveform

DATA RETENTION MODE

VCC

≥

4.5V

VDR

4.5V

CDR

VDR

VIH

2674 drw 05

AC Test Conditions

Input Pulse Levels

GND to 3.0V

893Ω

Input Rise/Fall Times

5ns Max.

1.5V

893Ω

Input Timing Reference Levels

Output Reference Levels

Output Load

DATA^OUT

347Ω

DATA^OUT

347Ω

1.5V

5pF*

Figures 1 and 2

30pF

2674 tbl 08b

2674 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and jig

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature andSupplyVoltage^(3,4)

7052X20

Com'l Only

7052X25

Com'l &

Military

7052X35

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

t^AA

t^ACE

t^AOE

t^OH

t^LZ

Read Cycle Time

____

Address Access Time

Chip Enable Access Time

Output Enable Access Time

____

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

Output High-Z Time^(1,2)

____

.____

t^HZ

t^PU

t^PD

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

____

2674 tbl 09

NOTES:

1. Transition is measured ±200mV from Low or High-Impedance voltage with the Output Test Load (Figure 2)

2. This parameter is guaranteed by device characterization but is not production tested.

3. 'X' in part number indicates power rating (S or L)

4. Industrial temperature: for specific speeds, packages and powers contact your sales office.

Timing Waveform of Read Cycle No. 1, Any Port⁽¹⁾

t_RC

ADDRESS

t_AA

t_OH

PREVIOUS DATA VALID

t_OH

DATA VALID

DATA_OUT

2674 drw 07

NOTES:

1. R/W = VIH, OE = VIL and CE = VIL.

Timing Waveform of Read Cycle No. 2, Any Port^(1,2)

t_ACE

t_AOE

t_HZ

t_LZ

t_HZ

DATA_OUT

VALID DATA

t_LZ

t_PU

t_PD

I_CC

CURRENT

50%

I_SB

2674 drw 08

NOTES:

1. R/W = VIH for Read Cycles.

2. Addresses valid prior to or coincident with CE transition LOW.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage^(7,8)

7052X20

Com'l Only

7052X25

Com'l &

Military

7052X35

Com'l &

Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time

(3)

t^WP

t^WR

t^DW

t^HZ

Write Pulse Width

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time

____

t^DH

t^WZ

t^OW

(1,2)

____

Write Enable to Output in High-Z

Output Active from End-of-Write^(1,2)

____

(4)

____

WDD

Write Pulse to Data Delay

Write Data Valid to Read Data Delay⁽⁴⁾

____

t^WDD

BUSY INPUT TIMING

t^WB

Write to BUSY⁽⁵⁾

t^WH

Write Hold After BUSY⁽⁶⁾

____

2674 tbl 10

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers

to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement

does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8).

4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.

5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.

6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.

7. 'X' in part number indicates power rating.

8. Industrial temperature: for specific speeds, packages and powers contact your sales office.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(5,8)

tWC

ADDRESS

(6)

t_AS

(3)

tAW

tWR

(9)

(7)

(2)

tHZ

tWP

R/W

(7)

t_WZ

tHZ

tLZ

tOW

(4)

DATAOUT

DATA_IN

t_DH

t_DW

2674 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^{(1, 5)}

tWC

ADDRESS

tAW

CE⁽⁹⁾

(3)

(6)

(2)

tAS

tEW

tWR

R/W

tDW

tDH

DATAIN

2674 drw 10

NOTES:

1. R/W or CE = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.

3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production

tested.

8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed

on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read^(1,2,3)

tWC

MATCH

ADDR"A"

tWP

R/W"A"

DATAIN"A"

ADDR"B"

VALID

MATCH

tWDD

VALID

DATA"B"

tDDD

NOTES:

2674 drw 11

1. Assume BUSY input = VIH and CE = VIL for the writing port.

2. OE = VIL for the reading ports.

3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.

Timing Waveform of Write with BUSY Input

tWP

R/W"A"

tWH

t_WB

BUSY"B"

R/W"B"

(1)

2674 drw 12

NOTES:

1. BUSY is aserted on Port "B" blocking R/W^"B"until BUSY"B" goes HIGH.

Truth Table I Read/Write Control⁽³⁾

FunctionalDescription

TheIDT7052providesfourportswithseparatecontrol,address,and

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

in memory. These devices have an automatic power down feature

controlled by CE. The CE controls on-chip power down circuitry that

permitstherespectiveporttogointostandbymodewhennotselected(CE

= VIH). When a port is enabled, access to the entire memory array is

permitted.EachporthasitsownOutputEnablecontrol(OE).Intheread

mode, the port’s OE turns on the output drivers when set LOW. READ/

WRITEconditionsareillustratedinthetablebelow.

Any Port⁽¹⁾

0-7

R/W

Function

Port Deselected: Power-Down

P4 IH

CE =CE =CE =CE =V

SB1

Power Down Mode I or I

Data on port written into memory⁽²⁾

Data in memory output on port

Outputs Disabled

DATA

OUT

DATA

2674 tbl 11

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance

2. If BUSY = VIL, write is blocked.

3. For valid write operation, no more than one port can write to the same address

location at the same time.

6.42

IDT7052S/L

High-Speed 2K x 8 FourPort™ Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

IDT

XXXX

999

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C

Military (-55°C to +125°C)

I⁽¹⁾

Compliant to MIL-PRF-38535 QML

PQF

108-Pin Pin Grid Array (G108-1)

132-Pin Plastic Quad Flatpack (PQ132-1)

120-Pin Thin Quad Plastic Flatpack (PN120-1)

Commercial Only

Commercial & Military

Speed

in nanoseconds

Low Power

Standard Power

7052

16K (2K x 8) FourPort RAM

2674 drw 13

NOTE:

1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

DatasheetDocumentHistory

1/18/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmetictypographicalcorrections

Addedadditionalnotestopinconfigurations

Changeddrawingformat

6/4/99:

Page1 Corrected DSC number

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

831-754-4613

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

IDT7052S35G [IDT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E