IDT709379L12PF9 [IDT]
Dual-Port SRAM, 32KX18, 12ns, CMOS, PQFP100, TQFP-100;
| 型号： | IDT709379L12PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 32KX18, 12ns, CMOS, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 32K x 18
IDT709379L
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
Low-power operation
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
◆
◆
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– IDT709379L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
– 12ns cycle time, 83MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
◆
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LBL
LBR
OEL
OER
1b 0b
0a 1a
0b 1b
1a 0a
a
FT/PIPEL
0/1
0/1
b
a
b
FT/PIPER
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
I/O
Control
I/O
Control
A14R
A14L
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A0R
A0L
CLKR
ADSR
CLKL
ADSL
CNTENL
CNTENR
CNTRSTL
CNTRSTR
4845 drw 01
JANUARY 2001
1
DSC-4845/3
©2000IntegratedDeviceTechnology,Inc.
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
With an input data register, the IDT709379 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
Anautomaticpowerdownfeature, controlledbyCE0andCE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 1.2W of power.
The IDT709379 is a high-speed 32K x 18 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Pin Configurations(1,2,3)
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A9L
A10L
A11L
A12L
A13L
A14L
NC
LBL
UBL
A8R
A9R
A10R
A11R
A12R
A13R
A14R
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
4
5
6
7
8
9
LBR
UBR
CE0L
CE1L
CNTRSTL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
709379PF
PN100-1(4)
CE
0R
CE1R
CNTRSTR
R/WL
OEL
Vcc
100-Pin TQFP
Top View(5)
R/
R
W
GND
OER
/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
FT
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4845 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables
CE0L
1L
CE0R
1R
, CE
, CE
WL
R/
WR
R/
Read/Write Enable
Output Enable
Address
OEL
OER
0L
A
14L
0R
A
14R
- A
- A
0L
17L
0R
17R
I/O - I/O
I/O - I/O
Data Input/Output
Clock
L
CLK
R
CLK
Upper Byte Select
Lower Byte Select
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
UBL
UBR
LBL
LBR
ADSL
ADSR
CNTENL
CNTRSTL
CNTENR
CNTRSTR
FT
/PIPE
L
FT
/PIPE
R
CC
V
GND
Ground
4845 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte
I/O9-17
Lower Byte
I/O0-8
CLK
↑
0
CE1
X
L
R/W
X
X
X
L
Mode
Deselected—Power Down
OE
X
X
X
X
X
X
L
CE
UB
X
X
H
L
LB
X
X
H
H
L
H
X
L
L
L
L
L
L
L
L
High-Z
High-Z
High-Z
DATAIN
High-Z
DATAIN
DATAOUT
High-Z
DATAOUT
High-Z
High-Z
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
↑
H
H
H
H
H
H
H
H
↑
↑
H
L
L
↑
L
L
↑
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
↑
L
L
↑
H
X
L
L
Outputs Disabled
4845 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.342
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2,6)
Previous
Address
Addr
Used
Mode
(3)
Address
CLK
I/O
ADS
CNTEN
CNTRST
X
An
An
X
X
X
0
An
X
X
X
H
L
H
H
H
DI/O(0)
DI/O(n)
DI/O(n)
Counter Reset to Address 0
↑
↑
↑
↑
(4)
L
External Address Loaded into Counter
External Address Blocked—Counter Disabled (Ap reused)
Ap
Ap
Ap
H
H
(5)
Ap + 1
L
DI/O(n+1) Counter Enable—Internal Address Generation
4845 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Recommended Operating
Recommended DC Operating
Temperature and Supply Voltage(1) Conditions
Symbol
Parameter
Min.
4.5
0
Typ. Max. Unit
Grade
Ambient
GND
Vcc
Temperature(2)
VCC
Supply Voltage
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V + 10%
5.0V + 10%
GND Ground
0
Industrial
-40OC to +85OC
(1)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0
4845 tbl 04
(2)
____
NOTES:
-0.5
0.8
V
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter TA. This is the "instant on" case temperature.
4845 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
CIN
VIN = 3dV
9
pF
(3)
COUT
VOUT = 3dV
10
pF
4845 tbl 07
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
TBIAS
TSTG
IOUT
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
Storage
Temperature
3. COUT also references CI/O.
DC Output
Current
mA
4845 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
4
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709379L
Symbol
|ILI|
Parameter
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
___
Input Leakage Current
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
0
IH
1
IL OUT
CC
5
CE = V or CE = V , V = 0V to V
VOL
IOL = +4mA
0.4
___
VOH
IOH = -4mA
2.4
V
4845 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3,6) (VCC = 5V ± 10%)
709379L7
Com'l Only
709379L9
Com'l Only
709379L12
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
ICC
Dynamic Operating
Current
(Both Ports Active)
L
L
L
L
L
L
275
465
250
400
230
355
CEL and CER= VIL
Outputs Disabled
(1)
____
____
____
____
____
____
IND
f = fMAX
mA
mA
ISB1
ISB2
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
95
150
80
135
70
110
CEL = CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
200
295
175
275
150
240
CE"A" = VIL and
(3)
CE"B" = VIH
____
____
____
____
____
____
Active Port Outputs
Disabled, f=fMAX
(1)
mA
mA
ISB3
ISB4
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
IND
L
L
0.5
3
0.5
3
0.5
3
____
____
____
____
____
____
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
L
L
190
290
170
270
140
225
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
____
____
____
____
____
____
(1)
Outputs Disabled, f = fMAX
4845 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.542
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
4845 tbl 10
5V
5V
893Ω
Ω
893
DATAOUT
DATAOUT
30pF
Ω
347
5pF*
347Ω
4845 drw 04
4845 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
8
7
6
5
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
4845 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709379L7
Com'l Only
709379L9
Com'l Only
709379L12
Com'l Only
Symbol
tCYC1
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Clock Cycle Time (Flow-Through)
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
(2)
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
Clock Cycle Time (Pipelined)
(2)
Clock High Time (Flow-Through)
Clock Low Time (Flow-Through)(2)
(2)
Clock High Time (Pipelined)
(2)
Clock Low Time (Pipelined)
5
6
8
____
____
____
Clock Rise Time
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
tSA
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tSC
tHC
tSB
tHB
tSW
tHW
tSD
R/
W
W
Setup Time
Hold Time
R/
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
0
1
1
____
____
____
9
12
12
(1)
____
____
____
tOLZ
tOHZ
tCD1
tCD2
tDC
Output Enable to Output Low-Z
2
2
2
(1)
Output Enable to Output High-Z
1
7
1
7
1
7
Clock to Data Valid (Flow-Through)(2)
18
20
25
____
____
____
(2)
____
____
____
Clock to Data Valid (Pipelined)
7.5
9
12
____
____
____
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
tCKHZ
tCKLZ
Clock High to Output High-Z
9
9
9
(1)
____
____
____
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD Write Port Clock High to Read Data Delay
tCCS Clock-to-Clock Setup Time
____
____
____
____
____
____
28
10
35
15
40
15
ns
ns
4845 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for
that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.742
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
(4)
tHC
tHB
tSC
tSB
tHC
tHB
CE1
UB, LB
R/W
tSB
tHW
tHA
tSW
tSA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
tDC
(1)
tOHZ
tOLZ
tOE
OE(2)
4845 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
(4)
tHC
tHB
tSC tHC
CE1
tSB
(6)
tHB
tSB
UB, LB
R/W
tHW
tHA
tSW
tSA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
OE(2)
tOE
4845 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X" here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
tSC tHC
(3)
tCKHZ
tCD2
tCD2
tCD2
(3)
Q0
Q3
A5
Q1
A3
DATAOUT(B1)
ADDRESS(B2)
(3)
tDC
tCKLZ
tDC
tCKHZ
tSA tHA
A0
A6
A4
A2
A1
tSC tHC
CE0(B2)
tSC tHC
(3)
tCD2
(3)
tCKHZ
tCD2
(3)
DATAOUT(B2)
Q4
Q
2
tCKLZ
tCKLZ
4845 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA tHA
NO
ADDRESS "A"
DATAIN "A"
CLK "B"
MATCH
MATCH
tSD tHD
VALID
(6)
tCCS
tCD1
R/W "B"
tHW
tHA
tSW
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
tCD1
tCWDD
VALID
VALID
tDC
tDC
4845 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709289 for this waveform, and are setup for depth expansion in this example.
ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.942
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
tSC tHC
tSB tHB
UB, LB
R/W
tSW tHW
An + 2
tSW tHW
(4)
An + 3
An + 4
An
An +1
An + 2
ADDRESS
tSA tHA
tSD
tHD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
4845 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
tSW tHW
W
R/
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
(1)
tCD2
tCD2
tCKLZ
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
READ
WRITE
READ
4845 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
tSC tHC
tSB
tHB
,
UB LB
tSW tHW
R/
W
tSW tHW
ADDRESS(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
tSD tHD
Dn + 2
tSA tHA
DATAIN
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
tCKLZ
(1)
tDC
tDC
tCKHZ
NOP(5)
READ
WRITE
4845 drw 13
TimingWaveformofFlow-ThroughRead-to-Write-to-Read(OEControlled)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 5
An
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
t
OE
tDC
t
CD1
tCD1
tCD1
(2)
Qn + 4
tDC
Qn
DATAOUT
(1)
tCKLZ
(1)
tOHZ
OE
READ
WRITE
READ
4845 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4845 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
tDC
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
4845 drw 16
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4845 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS(4)
An + 2
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
CNTEN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
4845 drw 18
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
61.432
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
A Functional Description
The IDT709379 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the various
chip enables in order to expand two devices in depth.
The 709379 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 36-bit
or wider applications.
The IDT709379 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
CE0 = VIH or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709379's for depth
expansion configurations. When the Pipelined output mode is en-
abled, two cycles are required with CE0 = VIL and CE1 = VIH to re-
activate the outputs.
15
A
IDT709379
IDT709379
CE0
CE0
CE1
CE1
CC
CC
V
V
Control Inputs
Control Inputs
IDT709379
IDT709379
CE1
CE1
CE0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
4845 drw 19
W
R/
LB UB
OE
,
Figure 4. Depth and Width Expansion with IDT709379
14
6.42
IDT709379L
High-Speed 32K x 18 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40 C to +85 C)
°
°
PF
100-pin TQFP (PN100-1)
7
9
12
Commercial Only
Commercial Only
Commercial Only
Speed in nanoseconds
L
Low Power
709379 576K (32K x 18-Bit) Synchronous Dual-Port RAM
4845 drw 20
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
9/30/99:
11/10/99:
12/22/99:
1/12/01:
InitialPublicRelease
Replaced IDT log
Page 1 Addednmissingdiamond
Page 4 ChangedinformationinTruthTableII
Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
RemovedPreliminarystatus
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61.452
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