IDT70P247L55BYGI8 [IDT]
Dual-Port SRAM, 4KX16, 55ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, BGA-100;
| 型号： | IDT70P247L55BYGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 4KX16, 55ns, CMOS, PBGA100, 6 X 6 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, BGA-100 静态存储器 |
| 文件： | 总23页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM
IDT70P257/247L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
M/S = VDD for BUSY output flag on Master
M/S = VSS for BUSY input on Slave
Input Read Register
Output Drive Register
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in 100 Ball 0.5mm-pitch BGA
Industrial temperature range (-40°C to +85°C)
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
– Industrial:55ns (max.)
Low-power operation
IDT70P257/247L
Active:27mW(typ.)
Standby:3.6µW(typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70P257/247 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
R/W
R
R/W
L
UBR
UBL
LB
CE
OE
R
LBL
CEL
OEL
R
R
,
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
BUSY (2,3)
L
(2,3)
BUSY
R
(1)
12R
(1)
A
A
12L
Address
Decoder
Address
Decoder
MEMORY
ARRAY
A0R
A
0L
CE
L
CE
OE
R/W
ODR
R
INPUT
READ REGISTER
AND
OE
L
L
R
R/W
R
OUTPUT
DRIVE REGISTER
ODR
0
-
4
IRR0,IRR1
SFEN
13
13
CE
OE
R/W
L
CE
R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
L
OE
R
L
R/W
R
SEM
INTR
R
(3)
SEM
L
(3)
M/S
INTL
5684 drw 01
NOTES:
1. A12X is a NC for IDT70P247.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
MAY 2006
1
DSC-5684/3
©2006IntegratedDeviceTechnology,Inc.
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Description
reads or writes to any location in memory. An automatic power down
The IDT70P257/247 is a very low power 8K/4K x 16 Dual-Port
StaticRAM.TheIDT70P257/247isdesignedtobeusedasastand-alone featurecontrolledbyCE permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
128/64K-bitDual-PortSRAMorasacombinationMASTER/SLAVEDual-
PortSRAMfor32-bit-or-more wordsystems. Usingthe IDTMASTER/
SLAVE Dual-Port SRAM approach in 32-bit or wider memory system
applicationsresultsinfull-speed,error-freeoperationwithouttheneedfor
additionaldiscretelogic.
Fabricated using IDT’s CMOS high-performance technology,
thesedevices typicallyoperateononly27mWofpower.
TheIDT70P257/247ispackagedina100ball0.5mm-pitchBall
Grid Array. The package is a 1mm thick and designed to fit in wireless
Thisdeviceprovidestwoindependentportswithseparatecontrol, handsetapplications.
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
PinConfigurations(2,3,4)
70P257/247BY
BY-100
100-Ball 0.5mm Pitch BGA
Top View(5)
02/04/04
A5
A1
A2
A3
A6
A7
A8
A9
A4
A10
A11R UB
R
Vss SEM
R
I/O15R I/O12R I/O10R Vss
A5R
A8R
B1
B2
B3
B6
B7
B9
B4
B5
B8
B10
OE
R
A3R
A4R
A7R
A9R
CER
R/WR
VDD I/O9R I/O6R
C1
C5
C6
C2
C3
D3
C4
C7
C8
C9
C10
A
0R
A
1R
A
2R
A
6R
I/O14R I/O11R I/O7R Vss
LB
R
IRR
1
D1
D2
D6
D9
D5
D7
D8
D10
D4
(1)
ODR
4
ODR
2
A
10R A12R I/O13R I/O8R I/O5R I/O2R
BUSYR INTR
E5
E6
E7
E8
E9
E10
E1
E2
E3
E4
Vss
I/O1R Vss
Vss
ODR
3
Vss
I/O4R
VDD
M/S
INTL
F7
F5
F6
F9
F10
F1
F2
F3
F8
F4
Vss
A1L
V
DD
I/O3R
I/O15L
VDD
SFEN
ODR
1
BUSY
L
I/O0R
G1
G5
G2
G4
G6
G8
G9
G3
G7
G10
(1)
A12L
A5L
OEL
I/O3L I/O11L I/O12L I/O14L I/O13L
ODR
0
A2L
,
H7
H8
H9
H10
H3
H4
H5
H6
H1
H2
A9L
A
0L
A4L
LB
L
CEL
I/O1L
VDD
NC
NC I/O10L
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
I/O4L
A10L IRR
0
V
DD
Vss
I/O6L I/O8L I/O9L
A
3L
A7L
K6
K8
K10
K2
K4
K5
K7
K9
K1
K3
R/W
L
L
I/O2L
A
6L
A8L
A
11L
UBL
I/O0L
I/O5L I/O7L
SEM
5684 drw 02b
NOTES:
1. A12X is a NC for IDT70P247.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
PinNames
Left Port
Right Port
Names
Chip Enable (Input)
CE
R/W
OE
L
CE
R
L
R/W
R
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
L
OE
R
(1)
(1)
A0L - A12L
A0R - A12R
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
Semaphore Enable (Input)
Upper Byte Select (Input)
Lower Byte Select (Input)
Interrupt Flag (Output)
Busy Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
, IRR
- ODR
R
L
R
L
R
L
R
L
R
NOTE:
1. A12X is a NC for IDT70P247.
2. SFEN is active when either CEL = VIL or CER = VIL.
SFEN is inactive when CEL = CER = VIH.
IRR
0
1
Input Read Register (Input)
Output Drive Register (Output)
Special Function Enable (Input)
Master or Slave Select (Input)
Power (1.8V) (Input)
ODR
0
4
SFEN(2)
M/S
VDD
VSS
Ground (0V) (Input)
5684 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
X
L
I/O8-15
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Mode
Deselected: Power Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
L
L
H
L
H
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
5684 tbl 02
NOTE:
1. A0L — A12L ≠ A0R — A12R for IDT70P257; A0L — A11L ≠ A0R — A11R for IDT70P247.
6.42
3
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O8-15
I/O0-7
Mode
CE
H
X
H
X
L
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
Read Data in Semaphore Flag
H
L
L
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
↑
X
X
X
X
L
↑
L
DATAIN
DATAIN
____
____
X
L
____
____
L
X
X
L
Not Allowed
5684 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
AbsoluteMaximumRatings(1)
Symbol
Rating
Industrial
Unit
V
V
TERM
Supply Voltage on VDD
with Respect to GND
-0.5 to +2.9
(2)
TERM
V
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.3
V
(3)
BIAS
T
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
T
STG
JN
OUT
oC
T
I
20
mA
5684 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and
is limited to < 20mA for the period over VTERM = VDD + 0.3V.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
6.42
4
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Capacitance
MaximumOperatingTemperature
andSupplyVoltage(1)
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
Grade
Ambient
GND
VDD
Temperature
CIN
V
9
pF
Industrial
-40OC to +85OC
0V
1.8V
+
100mV
COUT
V
11
pF
5684 tbl 05
5684 tbl 07
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
RecommendedDCOperatingConditions
Symbol
Parameter
Min.
1.7
0
Typ.
Max.
Unit
Supply Voltage(3)
Ground
V
V
V
V
DD
SS
IH
1.8
1.9
V
0
0
V
___
Input High Voltage
Input Low Voltage
1.2
-0.2
V
DD + 0.2
V
V
___
IL
0.4
5684 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
3. M/S operates at the VDD and VSS voltage levels.
6.42
5
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
DD = 1.8V, VIN = 0V to
CE = VIH, VOUT = 0V to
OL = +0.1mA
OH = -0.1mA
___
ILI
Input Leakage Current
Output Leakage Current
Output Low Voltage
1
1
µA
µA
V
V
VDD
___
ILO
VDD
___
VOL
0.2
I
___
VOH
Output High Voltage
V
DD - 0.2V
V
I
5684 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 1.8V ±100mV)
70P257/247
Ind'l Only
Symbol
Parameter
Test Condition
Version
IND'L
Typ.(1)
Max.
15 25
Unit
IDD
Dynamic Operating Current
(Both Ports Active)
mA
L
L
L
CE = VIL, Outputs Open
f = fMAX
(2)
ISB1
Standby Current (Both Ports -
TTL Level Inputs)
2
µA
mA
µA
CE
R
and CE
L
= VIH, SEM
=
VIH
IND'L
IND'L
8
(2)
f = fMAX
ISB2
Standby Current (One Port -
TTL Level Inputs)
8.5
14
CE"
A
" = VIL and CE"
B
" = VIH(4), Active Port Outputs Open
(2)
f = fMAX
ISB3
Full Standby Current (Both
Ports - CMOS Level Inputs)
Both Ports CE
L
and CE
R > VDD - 0.2V,
IND'L
IND'L
L
L
2
8
SEM
f = fMAX
L
and SEM
R > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V
(2)
(4)
, M/S = VDD or VSS
(4)
ISB4
Full Standby Current (One
Port - CMOS Level Inputs)
8.5
14
mA
CE"A" < 0.2V and CE"B" > VDD - 0.2V
V
IN > VDD - 0.2V or VIN < 0.2V, Active Port Outputs Open
(2)
f = fMAX
5684 tbl 09
NOTES:
1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.)
2. At f = fMAX, address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. If M/S = VSS, then fBUSYL = fBUSYR = 0 for full standby mode.
6.42
6
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 1.8V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns Max.
0.9V
0.9V
Figure 1
5684 tbl 10
1.8V
1.8V
R1
R1 13500Ω
R2 10800Ω
5684 tbl 10_5
R2
30pF
5684 drw 03
Figure 1. AC Output Test Load
(5pF for tLZ, tHZ, tWZ, tOW)
Timing of Power-Up Power-Down
CE
t
PU
t
PD
I
CC
50
%
50%
I
SB
,
5684 drw 04
6.42
7
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70P257/247
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
READ CYCLE
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
t
Address Access Time
55
55
55
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2,5)
____
____
____
t
t
t
30
____
t
5
____
t
5
Output High-Z Time(1,2,5)
25
____
t
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
____
____
t
55
____
t
15
____
t
55
ns
5684 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
6.42
8
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Waveform of Read Cycles(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
(4)
ABE
t
UB, LB
R/W
tOH
(1)
t
LZ
(4)
DATAOUT
BUSYOUT
VALID DATA
(2)
tHZ
,
(3,4)
BDD
5684 drw 05
t
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation
to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltage(4)
70P257/247
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
30
____
t
25
____
t
0
(1,2)
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
25
____
t
0
____
____
t
10
10
t
ns
5684 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
6.42
10
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
(9)
CE or SEM
CE or SEM(9)
(3)
(6)
(2)
t
WR
t
AS
tWP
R/W
DATAOUT
DATAIN
(7)
t
WZ
t
OW
(4)
(4)
t
DW
tDH
,
5684 drw 06
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9)
(3)
WR
(2)
(6)
AS
t
t
EW
t
UB or LB(9)
R/W
t
DW
tDH
DATAIN
,,
5684 drw 07
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
6.42
11
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
O
H
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tWR
tACE
tAW
tEW
SEM
tDW
tSOP
DATAOUT
VALID(2)
DATAIN
VALID
I/O
0
tAS
tWP
t
DH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
,
5684 drw 08
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15)equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
"B"
R/W"B"
SEM"B"
5684 drw 09
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH.
2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag.
6.42
12
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P257/247
Ind'l Only
Symbol
BUSY TIMING (M/S = VDD
Parameter
Min.
Max.
Unit
)
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
45
45
45
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
45
____
t
5
____
BUSY Disable to Valid Data(3)
t
40
t
Write Hold After BUSY(5)
35
____
BUSY TIMING (M/S = VSS
)
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
ns
ns
tWH
35
PORT-TO-PORT DELAY TIMING
____
____
t
WDD
Write Pulse to Data Delay(1)
80
65
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5684 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VDD)" or "Timing Waveform of Write
With Port-To-Port Delay (M/S = VSS)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6.42
13
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
t
WC
MATCH
ADDR"A"
R/W"A"
t
WP
t
DW
t
DH
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
tBAA
t
BDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
,
5684 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VSS (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
Timing Waveform of Slave Write (M/S = VIL)
t
WP
R/W"A"
(3)
WB
t
BUSY"B"
(1)
t
WH
(2)
R/W"B"
,
5684 drw 11
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “slave” version.
6.42
14
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
t
BDC
,
BUSY"B"
5684 drw 12
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
t
APS
MATCHING ADDRESS "N"
t
BAA
tBDA
,
5684 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P257/247
Ind'l Only
Symbol
Parameter
Min.
Max.
Unit
INTERRUPT TIMING
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
ns
ns
ns
ns
t
0
____
t
45
45
____
t
Interrupt Reset Time
5684 tbl 14
6.42
15
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Waveform of Interrupt Timing(1)
t
WC
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS(2)
(3)
(4)
t
AS
tWR
R/W"A"
INT"B"
(3)
t
INS
,
5684 drw 14
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
,
INT"B"
5684 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
16
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
(4)
(4)
R/W
L
L
A
12L-A0L
R/W
R
A
12R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
X
L
CE
R
OE
R
INTR
(2)
L
X
X
L
X
X
X
L
1FFF
X
X
X
L
L
X
X
L
X
L
R
(3)
X
X
X
1FFF
1FFE
X
H
R
(3)
X
X
L
L
X
X
X
X
L
(2)
X
1FFE
H
X
L
5684 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12X is a NC for IDT70P247, therefore Interrrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
(4)
A
0L-A12L
(1)
(1)
A
0R-A12R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
5684 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70P257/247 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A0L — A11L and A0R — A11R for IDT70P247.
6.42
17
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5684 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P257/247.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table VI — Input Read Register Operation(3)
R/W
H
ADDR
I/O0-I/O1
I/O2-I/O15
Mode
SFEN
H
CE
L
OE
L
UB
LB
(1)
(1)
(1)
(1)
L
L
x0000 - Max VALID
VALID
Standard Memory Access
(2)
L
L
H
L
X
L
x0000
VALID
X
IRR Read(3)
5684 tbl 18
NOTES:
1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
2. LB must be active (LB = VIL) for these bits to be valid.
3. SFEN = VIL to activate IRR reads.
Truth Table VII — Output Drive Register Operation(5)
R/W
H
ADDR
I/O0-I/O4
I/O5-I/O15
Mode
SFEN
H
CE
L
OE
UB
LB
(1)
(2)
(2)
(2)
(2)
X
L
L
x0000 - Max VALID
VALID
X
Standard Memory Access
ODR Write(4,5)
(3)
L
L
L
X
L
X
X
L
L
x0001
x0001
VALID
(3)
L
L
H
VALID
X
ODR Read(5)
5684 tbl 19
NOTES:
1. Output enable must be low (OE = Vil) during reads for valid data to be output.
2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
3. LB must be active (LB = VIL) for these bits to be valid.
4. During ODR writes data will also be written to the memory.
5. SFEN = VIL to activate ODR reads and writes.
6.42
18
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Device 1
Device 2
IRR
0
IRR
1
Input Read Register
(ADDRESS x0000)
(1)
(1)
0L - A12L
A
0R - A12R
A
Address & I/O
Control
I/O0L - I/O15L
I/O0R - I/O15R
Memory
Array
5684 drw 16
Figure 3. Input Read Register
Device 2
Device 1
Device 4
Device 3 Device 5
0 ODR
ODR
1
ODR
2
ODR
3
ODR
4
Output Drive Register
(ADDRESS x0001)
(1)
(1)
A
0R - A12R
A
0L - A12L
Address & I/O
Control
I/O0L - I/O15L
I/O0R - I/O15R
Memory
Array
5684 drw 17
Figure 4. Output Drive Register
NOTE:
1. A12X is a NC for IDT70P247.
6.42
19
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSY
L
BUSY
R
BUSY
L
BUSYR
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSY
R
BUSY
L
BUSYL
BUSY
R
BUSYR
BUSY
L
,
5684 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P257/247 SRAMs.
FunctionalDescription
ThebusyoutputsontheIDT70P257/247SRAMinmastermode,are
push-pulltypeoutputs anddonotrequirepullupresistors tooperate.If
theseSRAMsarebeingexpandedindepth,thentheBUSYindicationfor
the resulting array requires the use of an external AND gate.
The IDT70P257/247 provides two ports with separate control, ad-
dress and I/O pins that permit independent access to any location in
memory. The IDT70P257/247 has an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permitstherespectiveporttogointoastandbymodewhennotselected
(CEHIGH).Whenaportis enabled,access totheentirememoryarray
ispermitted.
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT70P257/247 SRAM array in width while
usingbusylogic,onemasterpartisusedtodecidewhichsideoftheSRAM
array will receive aBUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70P257/247SRAMtheBUSYpinisanoutputifthepartisusedasa
master(M/Spin=VDD),andtheBUSY pinis aninputifthepartusedas
a slave (M/S pin = VSS) as shown in Figure 3.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag(INTL)isassertedwhentherightportwritestomemorylocation1FFE
(HEX)(FFEforIDT70P247),whereawriteisdefinedastheCE=R/W=VIL
perTruthTableIII.Theleftportclearstheinterruptbyaccessingaddress
location 1FFE when CER = OER = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 1FFF (HEX) (FFF for IDT70P247) and to clear the
interruptflag(INTR),therightportmustreadthememorylocation1FFF.
The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 1FFEand1FFFarenotusedas mailboxes,butas partofthe
random access memory. Refer to Truth Table III for the interrupt
operation.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actualwrite pulse canbe initiatedwitheitherthe R/Wsignalorthe byte
enables. Failure to observe this timing can result in a glitched internal
writeinhibitsignalandcorrupteddataintheslave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
thattheSRAMis“busy”.TheBUSYpincanthenbeusedtostalltheaccess
untiltheoperationon theothersideiscompleted.Ifawriteoperationhas
beenattemp-tedfromthesidethatreceivesaBUSYindication,thewrite
signalisgatedinternallytopreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSY indicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSYpin for that port LOW.
Input Read Register
TheInputReadRegister(IRR)oftheIDT70P257/247captures the
statusoftwoexternalbinaryinputdevicesconnectedtotheInputReadpins
(e.g. DIP switches). The contents of the IRR are read as a standard
memoryaccesstoaddressx0000fromeitherportandthedataisoutput
viathestandardI/Os(TruthTableVI). DuringInputRegisterreadsI/O0
- I/O1 are valid bits and I/O2 - I/O15 are "Dont' Care". Writes to address
x0000arenotallowedfromeitherport.WhenSFEN = VIL, theIRRisactive
and address x0000 is not available for standard memory operations.
WhenSFEN = VIH, the IRR is inactive and address x0000 can be used
aspartofthemainmemory.TheIRRsupportsinputsupto3.5V(VIL<0.4V,
VIH>1.4V).RefertoFigure3andTruthTableVIforInputReadRegister
operation.
6.42
20
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Output Drive Register
How the Semaphore Flags Work
TheOutputDriveRegister(ODR)oftheIDT70P257/247determines
thestateofuptofiveexternalbinary-statedevicesbyprovidingapathto
VSSfortheexternalcircuit.ThefiveexternaldevicessupportedbytheODR
canoperateatdifferentvoltages(1.5V<VSUPPLY<3.5V),butthecombined
currentofthedevicesmustnotexceed40mA(8mAIMAXforeachexternal
device).ThestatusoftheODRbitsissetusingstandardwriteaccesses
fromeitherporttoaddress x0001witha“1”correspondingto“on“anda
“0” corresponding to “off”. The status of the ODR bits can also be read
(withoutchangingthe status ofthe bits)via a standardreadtoaddress
x0001. When SFEN = VIL, the ODR is active and address x0001 is not
availableforstandardmemoryoperations.WhenSFEN=VIH,theODR
isinactiveandaddressx0001canbeusedaspartofthemainmemory.
During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 -
I/O15are "Don'tCare". RefertoFigure 4andTruthTable VIIforOutput
DriveRegisteroperation.
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortSRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveHIGH.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
Semaphores
TheIDT70P257/247isanextremelyfastDual-Port8K/4Kx16CMOS
Static RAM with an additional 8 address locations dedicated to binary
semaphoreflags.Theseflagsalloweitherprocessorontheleftorrightside
ofthe Dual-PortSRAMtoclaima privilege overthe otherprocessorfor
functionsdefinedbythesystemdesigner’ssoftware.Asanexample,the
semaphore can be used by one processor to inhibit the other from
accessingaportionoftheDual-PortSRAMoranyothersharedresource.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbeaccessed
to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
haveanautomaticpower-downfeaturecontrolledbyCE,theDual-Port
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo
intostandbymodewhennotselected.Thisistheconditionwhichisshown
in Truth Table I where CE and SEM are LOW.
The eight semaphore flags reside within the IDT70P257/247 in a
separate memory space from the Dual-Port SRAM. This address
spaceisaccessedbyplacingaLOWinputontheSEMpin(whichactsas
a chip select for the semaphore flags) and using the other control pins
(Address,OE,andR/W)astheywouldbeusedinaccessingastandard
StaticRAM.Eachoftheflagshasauniqueaddresswhichcanbeaccessed
by either side through address pins A0 – A2. When accessing the
semaphores,noneoftheotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
Systems which can best use the IDT70P257/247 contain multiple
processors or controllers and are typically very high-speed systems
whicharesoftwarecontrolledorsoftwareintensive.Thesesystemscan
benefit from a performance increase offered by the IDT70P257/247's
hardware semaphores, which provide a lockout mechanism without
requiringcomplexprogramming.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varyingconfigurations.TheIDT70P257/247doesnotuseitssemaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
6.42
21
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation.On
asubsequentread,theprocessorwillverifythatithas writtensuccess-
fullytothatlocationandwillassumecontrolovertheresourceinquestion.
Meanwhile,ifaprocessorontherightsideattemptstowriteazerotothe
samesemaphoreflagitwillfail,aswillbeverifiedbythefactthataonewill
bereadfromthatsemaphoreontherightsideduringsubsequentread.
HadasequenceofREAD/WRITEbeenusedinstead,systemcontention
problemscouldhaveoccurredduringthegapbetweenthereadandwrite
cycles.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5684 drw 19
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requestedandthe processorwhichrequesteditnolongerneeds the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The criticalcase ofsemaphore timingis whenbothsides requesta
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
bothrequests arriveatthesametime,theassignmentwillbearbitrarily
made to one port or the other.
Figure 4. IDT70P257/247 Semaphore Logic
assumecontrolofthelower4K/2K.Meanwhiletherightprocessorwas
attemptingtogaincontrolofthe resourceaftertheleftprocessor,itwould
read back a one in response to the zero it had attempted to write into
Semaphore0.Atthispoint,thesoftwarecouldchoosetotryandgaincontrol
ofthesecond4K/2Ksectionbywriting,thenreadingazerointoSemaphore
1.Ifitsucceededingainingcontrol,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
4K/2Kblocks ofDual-PortSRAMwitheachother.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Sema-
phores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT70P257/247’sDual-PortSRAM. Saythe8K/
4Kx16SRAMwastobedividedintotwo4K/2Kx16blockswhichwere
to be dedicated at any one time to servicing either the left or right port.
Semaphore0couldbeusedtoindicatethesidewhichwouldcontrolthe
lower section of memory, and Semaphore 1 could be defined as the
indicatorfortheuppersectionofmemory.
To take a resource, in this example the lower 4K/2K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
6.42
22
IDT70P257/247L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
Ordering Information
IDT XXXXX
A
999
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Industrial (-40°C to +85°C)
I
G(1)
Green
100 Ball 0.5mm-pitch BGA(BY100)
BY
Industrial Only
Low Power
Speed in nanoseconds
55
L
128K (8K x 16) 1.8V Dual-Port SRAM
64K (4K x 16) 1.8V Dual-Port SRAM
70P257
70P247
5684 drw 20
NOTE:
1. Greenparts available.Forspecificspeeds,packages andpowers contactyourlocalsales office.
DatasheetDocumentHistory
02/04/04:
03/22/05:
InitialDatasheet
Page 1 Addedgreenavailabilitytofeatures
Page 23 Addedgreenindicatortoorderinginformation
Page 1 & 23 Replaced old IDT TM with new IDT TM logo
RemovedPreliminarystatus
05/08/06:
Page 4 UpdatedVTERM inAbsoluteMaximumRatingstable
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
408-284-2794
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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