IDT70P34L25BYI [IDT]
HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM; HIGH -SPEED 1.8V 8 / 4K ×18的双端口， 8 / 4K ×16双口静态RAM
| 型号： | IDT70P34L25BYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT, 8/4K x 16 DUAL-PORT STATIC RAM |
| 文件： | 总23页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 1.8V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
ADVANCED
IDT70P35/34L
IDT70P25/24L
Features
◆
select when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
◆
◆
◆
IDT70P35/34L (IDT70P25/24L)
– Commercial: 20/25ns (max.)
Full on-chip hardware support of semaphore signaling
between ports
– Industrial: 25ns (max.)
Low-power operation
◆
◆
◆
◆
Fully asynchronous operation from either port
LVTTL-compatible, single 1.8V (±100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package,
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin
0.5mm pitch BGA (fpBGA)
IDT70P35/34L (IDT70P25/24L)
Active:30.6mW(typ.)
Standby: 5.4mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70P35/34L (IDT70P25/24L) easily expands data bus
width to 36 bits (32 bits) or more using the Master/Slave
◆
◆
◆
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
R/W
R
R
UBL
UB
LB
CE
OE
R
LB
L
CEL
R
R
OEL
,
(5)
(5)
(4)
I/O9R-I/O17R
I/O9L-I/O17L
I/O
Control
I/O
Control
(4)
I/O0R-I/O8R
I/O0L-I/O8L
BUSY (2,3)
L
(2,3)
BUSY
R
(1)
12L
(1)
A
A
A
12R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
R
CE
OE
R/W
L
L
R
R
L
SEM
R
SEM
L
(3)
(3)
INTR
M/S
INTL
5683 drw 01
NOTES:
1. A12 is a NC for IDT70P34 and IDT70P24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70P25/24.
5. I/O8x - I/O15x for IDT70P25/24.
FEBRUARY 2004
1
DSC-5683/2
©2004 IntegratedDeviceTechnology,Inc.
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70P35/34L (IDT70P25/24L) is a high-speed 8/4K x 18 reads or writes to any location in memory. An automatic power down
(8/4Kx16)Dual-PortStaticRAM. TheIDT70P35/34L(IDT70P25/24L) featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
is designed to be used as a stand-alone Dual-Port RAM or as a a very low standby power mode.
combinationMASTER/SLAVEDual-PortRAMfor36-bit(32-bit)orwider
FabricatedusingIDT’sCMOShigh-performancetechnology,these
memory system applications results in full-speed, error-free operation devices typically operate on only 30.6mW of power.
withouttheneedforadditionaldiscretelogic.
TheIDT70P35/34L(IDT70P25/24L)ispackagedinaplastic100-pin
This device provides two independent ports with separate control, Thin Quad Flatpack, a 100-pin fine pitch Ball Grid Array, and a 100-pin
address,andI/Opinsthatpermitindependent,asynchronousaccessfor 0.5mmpitchfpBGA.
IDT70P35/34PinConfigurations(1,2,3,4)
12/17/03
Index
100 99 98 9796 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
N/C
N/C
75
74
2
3
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
Vss
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
5
A5L
A4L
A3L
A2L
A1L
A0L
6
7
8
9
I/O15L
I/O16L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70P35/34PF
PN100-1
(5)
INTL
BUSY
Vss
M/S
VDD
L
100-Pin TQFP
Vss
I/O0R
I/O1R
I/O2R
(6)
Top View
BUSY
R
INT
R
VDD
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
5683 drw 02
NOTES:
1. A12 is a NC for IDT70P34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.422
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
IDT70P35/34PinConfigurations(cont'd)(1,2,3,4)
IDT70P35/34BF
BF100(5)
100-Pin fpBGA
Top View(6)
12/16/03
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
(1)
A
6R
A9R
A
12R
CER
V
SS
V
SS
VSS
I/O7R
I/O13R I/O10R
B1
B2
B3
B6
B7
B9
B8
B10
B4
B5
A
8R
A
10R
NC
NC
I/O12R I/O9R I/O6R
R
SEM
R
R/W
R
OE
C2
C3
C4
D4
C1
C5
C6
C7
C8
C9
C10
A
4R
A
5R
2R
0R
I/O16R
A
3R
A
7R
1L
I/O15R I/O11R I/O8R
I/O3R
UB
R
D1
D2
D3
D9
D5
D6
D7
D8
D10
A
1R
A
11R
SS
I/O1R
A
NC
I/O14R I/O17R I/O5R
INT
R
LBR
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
M/S BUSY
R
A
A
V
V
SS
I/O4R I/O2R I/O0R
VDD
F7
F6
F8
F9
F10
F1
F2
F3
F5
F4
V
SS
A
0L
6L
V
DD
V
SS
V
DD
NC
I/O14L I/O15L I/O16L
BUSY
L
G1
G2
G4
G5
G6
G7
G8
G9
G10
G3
A
3L
V
SS
V
SS
INT
L
A
NC
I/O3L NC I/O12L
,
I/O13L
H7
H8
H9
H10
H5
H6
H1
H2
H3
H4
A
2L
A
5L
A
10L
I/O1L I/O7L I/O8L I/O17L I/O11L
CE
L
LB
L
J1
J2
J3
J4
J5
J6
J7
J8
J10
J9
A
4L
7L
A
8L
A
11L SEM
L
I/O4L I/O6L
V
SS
R/W
L
OE
L
I/O10L
K1
K2
K3
K5
K6
K7
K8
K9
K10
K4
(1)
V
DD
V
DD
A
A
12L
UB
L
I/O0L
A9L
I/O2L I/O5L I/O9L
5683 drw 03
NOTES:
1. A12 is a NC for IDT70P34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
IDT70P25/24PinConfigurations(1,2,3,4)
12/17/03
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
75
2
74
3
N/C
N/C
N/C
N/C
I/O10L
I/O11L
I/O12L
I/O13L
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
5
A5L
A4L
A3L
A2L
A1L
A0L
6
7
8
9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O14L
I/O15L
IDT70P25/24PF
PN100-1(5)
INT
L
VDD
BUSY
VSS
M/S
BUSY
L
100-Pin TQFP
Top View(6)
VSS
I/O0R
I/O1R
I/O2R
R
INT
R
A
A
A
A
A
0R
VDD
1R
2R
3R
4R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
.
5683 drw 04
NOTES:
1. A12 is a NC for IDT70P24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.442
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
IDT70P25/24PinConfigurations(cont'd)(1,2,3,4)
IDT70P25/24BF
BF100(5)
100-Pin fpBGA
Top View(6)
12/16/03
A1
A2
A3
A6
A7
A8
A9
A4
A5
A10
(1)
12R
A
A
6R
A
9R
CE
R
V
SS
V
SS
V
SS
I/O9R I/O7R
I/O12R
B1
B2
B3
B6
B7
B9
B4
B5
B8
B10
NC
NC
A
8R
A
10R
SEM
R
R/W
R
I/O11R I/O8R I/O6R
OE
R
C1
C5
C6
C2
C3
C4
D4
C7
C8
C9
C10
A
3R
A
4R
A
5R
2R
0R
A
7R
UB
R
I/O15R I/O14R
I/O10R NC
I/O3R
D1
D2
D3
D5
D6
D7
D8
D9
D10
A
1R
A
NC
I/O13R
I/O5R
A
11R
NC
I/O1R
INT
R
LB
R
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
A
1L
BUSY
R
M/S
A
V
SS
V
SS
I/O4R I/O2R I/O0R
V
DD
F7
F5
F6
F8
F9
F10
F1
F2
F3
F4
V
DD
V
SS
V
SS
A0L
NC
VDD I/O13L I/O14L
I/O15L
BUSY
L
G1
G2
G4
G5
G6
G7
G3
G8
G9
G10
A
6L
INT
L
A
3L
V
SS
I/O3L
NC
NC I/O11L
V
SS I/O12L
,
H7
H5
H6
H8
H9
H10
H1
H3
H4
H2
A
2L
A
5L
A
10L
11L
LB
L
CE
L
I/O1L I/O7L
I/O10L
NC
NC
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
A
4L
A
8L
A
V
SS
SEM
L
R/W
L
OE
L
I/O4L I/O6L
I/O9L
K6
K8
K1
K2
K3
K4
K5
K7
K9
K10
(1)
12L
A
7L
V
DD
A
9L
A
UB
L
V
DD
I/O0L I/O2L I/O5L I/O8L
5683 drw 05
NOTES:
1. A12 is a NC for IDT70P24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
5
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
IDT70P25/24PinConfigurations(1,2,3,4)
70P25/24BY
BY-100(5)
100-Ball 0.5mm Pitch BGA
Top View(6)
12/17/03
A1
A5
A2
A3
A6
A7
A8
A9
A4
A10
A
11R UB
R
Vss SEM
R
I/O15R I/O12R I/O10R Vss
A
5R
A
8R
4R
B1
B2
B3
B6
B7
B9
B4
B5
B8
B10
OE
R
A3R
A
A
7R
A
9R
CE
R
R/WR
VDD I/O9R I/O6R
C1
C5
C6
C2
C3
D3
C4
C7
C8
C9
C10
A
0R
A
1R
A
2R
A
6R
I/O14R I/O11R I/O7R Vss
LB
R
NC
D6
D1
D2
D9
D5
D7
D8
D10
D4
(1)
NC
NC
A
10R
A12R I/O13R I/O8R I/O5R I/O2R
BUSY
R INTR
E5
E6
E7
E8
E9
E10
E1
E2
E3
E4
Vss
I/O1R Vss
Vss
NC
Vss
I/O4R
VDD
M/S
INTL
F7
F5
F6
F9
F10
F1
F2
F3
F8
F4
Vss
A1L
V
DD
I/O3R I/O15L
I/O0R
V
DD
NC BUSY
L
Vss
G1
G5
G2
G4
G6
G8
G9
G3
G7
G10
(1)
A
12L
A
5L
9L
I/O3L I/O11L I/O12L I/O14L I/O13L
OE
L
A
2L
NC
H7
H8
H9
H10
H5
H6
H3
H4
H1
H2
A
A
0L
A
4L
7L
LB
L
CE
L
I/O1L
V
DD
NC
NC I/O10L
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
I/O4L
A
10L
NC
V
DD
Vss
I/O6L I/O8L I/O9L
A
3L
A
K6
K8
K10
K2
K4
K5
K7
K9
K1
K3
R/W
L
L
I/O2L
A
6L
A
8L
A
11L
UB
L
I/O0L
I/O5L I/O7L
SEM
5683 drw 06
NOTES:
1. A12X is a NC for IDT70P24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.462
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
L
R
(1)
(1)
A
0L - A12L
A
0R - A12R
Address
(2)
(2)
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
Semaphore Enable
Upper Byte Select(3)
Lower Byte Select(4)
Interrupt Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
L
R
L
R
L
R
Busy Flag
L
R
NOTE:
Master or Slave Select
Power (1.8V)
1. A12 is a NC for IDT70P34 and IDT70P24.
2. I/O0x - I/O15x for IDT70P25/24.
V
V
DD
3. IDT70P35/34L: UBx controls I/O9x - I/O17x
IDT70P25/24L: UBx controls I/O8x - I/O15x
4. IDT70P35/34L: LBx controls I/O0x - I/O8x
IDT70P25/24L: LBx controls I/O0x - I/O7x
SS
Ground (0V)
5683 tbl 01
6.42
7
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
(3)
(2)
R/W
X
I/O9-17
I/O0-8
Mode
CE
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
High-Z
High-Z
DATAIN
High-Z
DATAIN
High-Z
High-Z
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
X
H
L
L
H
High-Z
L
L
H
L
H
DATAIN
DATAIN
High-Z
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
DATAOUT
DATAOUT
High-Z
L
X
L
L
H
DATAOUT
High-Z
H
X
X
X
Outputs Disabled
5683 tbl 02
NOTE:
1. A0L — A12L ≠ A0R — A12R for IDT70P35 and IDT70P25; A0L — A11L ≠ A0R — A11R for IDT70P34 and IDT70P24.
2. Outputs for IDT70P25/24 are I/O0x - I/O7x.
3. Outputs for IDT70P25/24 are I/O8x - I/O15x.
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
(1)
(1)
R/W
H
I/O9-17
I/O0-8
Mode
Read Data in Semaphore Flag
CE
OE
L
UB
X
LB
X
SEM
H
L
L
L
L
L
L
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
X
H
L
H
X
H
X
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
↑
H
X
↑
X
X
H
L
H
X
DATAIN
DATAIN
____
____
L
L
X
X
____
____
X
X
X
L
Not Allowed
5683 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70P35/34 and I/O0-I/O15 for IDT70P25/24). These eight semaphores
are addressed by A0-A2.
6.482
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating Temperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
V
Grade
Ambient
GND
V
DD
Temperature
VTERM
Terminal Voltage
with Respect to GND
-0.5 to VDDMAX
+ 0.3V
Commercial
0OC to +70OC
0V
0V
1.8V
1.8V
+
+
100mV
100mV
Temperature Under Bias
-55 to +125
oC
(2)
Industrial
-40OC to +85OC
T
BIAS
STG
JN
OUT
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
oC
oC
5683 tbl 05
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
T
I
20
mA
5683 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in Recommended DC Operating
the operational sections of this specification is not implied. Exposure to absolute
Conditions
maximum rating conditions for extended periods may affect reliability.
2. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
Symbol
Parameter
Supply Voltage
Ground
Min.
1.7
Typ.
Max.
1.9
Unit
V
V
V
DD
SS
1.8
0
0
0
V
____
V
V
IH
IL
Input High Voltage
Input Low Voltage
1.2
V
DD+0.2
0.4
V
-0.2(1)
V
____
Capacitance(1) (TA = +25°C, f = 1.0MHz)
5683 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
9
pF
COUT
V
11
pF
5683 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
(70P25/24L)
70P35/34L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Test Conditions
DD = 1.8V, VIN = 0V to
CE = VIH, VOUT = 0V to
OL = +0.1mA
OH = -0.1mA
Min.
Max.
Unit
___
|
V
V
DD
1
1
µA
µA
V
___
___
|
Output Leakage Currentt
Output Low Voltage
Output High Voltage
VDD
V
V
OL
OH
I
0.2
___
I
V
DD - 0.2
V
5683 tbl 08
6.42
9
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 1.8V ± 100mV)
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
25
Max.
40
Typ.(2)
20
Max.
32
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
mA
L
L
L
L
CE = VIL, Outputs Disabled
SEM = VIH
(3)
IND
25
46
20
38
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
3.5
5.6
6.0
2.2
3.5
4.6
CE
R
and CE
L
= VIH
L = VIH
SEM
R
= SEM
(3)
3.5
2.2
f = fMAX
(1)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
CE"A" = VIL and CE"B" = VIH
L
L
15
15
25
32
12
12
20
26
Active Port Outputs Disabled,
(3)
f=fMAX
IND
SEM
R
= SEM
L
= VIH
and
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
L
mA
mA
COM'L
L
L
L
L
4.5
4.5
15
7.5
7.5
25
3
3
5
5
CE
R
> VDD - 0.2V,
V
V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
IND
SEM
R
= SEML > VDD-0.2V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
COM'L
CE"B" > VDD - 0.2V(1)
12
20
SEM
V
R
= SEML > VDD-0.2V
IN > VDD - 0.2V or VIN < 0.2V
IND
Active Port Outputs Disabled,
15
32
12
26
(3)
f = fMAX
5683 tbl 09
NOTES:
1. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. DD = 1.8V, TA = +25°C, and are not production tested. IDD dc = 15mA (typ.)
V
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
1.8V
AC Test Conditions
Input Pulse Levels
13500Ω
10800Ω
GND to 1.8V
3ns Max.
0.9V
Input Rise/Fall Times
30pF
Input Timing Reference Levels
Output Reference Levels
Output Load
0.9V
Figure 1
5683 drw 07
5683 tbl 10
Figure 1. AC Output Test Load
*(For tLZ, tHZ, tWZ, tOW)
Timing of Power-Up Power-Down
CE
tPU
t
PD
I
CC
50%
50%
I
SB
,
5683 drw 07
6.1402
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
20
25
ns
ns
ns
____
____
t
Address Access Time
20
20
20
25
25
25
____
____
____
____
____
____
Chip Enable Access Time(3)
Byte Enable Access Time(3)
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
t
12
13
____
____
t
Output Hold from Address Change
3
3
____
____
Output Low-Z Time(1,2)
t
3
3
Output High-Z Time(1,2)
____
____
t
12
15
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
____
____
Chip Disable to Power Down Time(1,2)
t
20
25
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
Semaphore Address Access(3)
____
____
t
20
25
ns
5683 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
(1)
tOH
tLZ
(4)
DATAOUT
BUSYOUT
VALID DATA
(2)
t
HZ
,
(3,4)
5683 drw 09
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
11
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
____
____
t
12
15
____
____
t
0
0
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
12
15
____
____
t
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
5683 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire
tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
6.1422
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9)
CE or SEM(9)
R/W
(3)
WR
(2)
tWP
(6)
t
t
AS
(7)
t
WZ
tOW
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
,
5683 drw 10
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
CE or SEM(9)
UB or LB(9)
t
AW
(3)
(6)
(2)
t
WR
tEW
t
AS
R/W
t
DW
tDH
DATAIN
,
5683 drw 11
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 1).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition.
6.42
13
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
OH
t
SAA
A0 - A2
VALID ADDRESS
VALID ADDRESS
t
AW
tWR
tACE
tEW
SEM
tSOP
tDW
OUT
DATA
DATA
0
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
t
SOP
Read Cycle
.
Write Cycle
5683 drw 12
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70P35/34) and (I/O0-I/O15 for IDT70P25/24) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
"B"
R/W"B"
SEM"B"
,
5683 drw 13
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.1442
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
17
17
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
30
30
t
Write Hold After BUSY(5)
15
17
____
____
BUSY TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5683 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
t
WC
ADDR"A"
MATCH
t
WP
R/W"A"
t
DH
t
DW
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
t
BAA
tBDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
,
NOTES:
5683 drw 14
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
6.42
15
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
,
5683 drw 15
NOTES:
1. tWH must be met for both master BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
tBAC
t
BDC
BUSY"B"
,
5683 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
t
BAA
tBDA
,
BUSY"B"
5683 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.1462
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
20
20
20
20
____
____
t
Interrupt Reset Time
ns
5683 tbl 14
Waveform of Interrupt Timing(1)
t
WC
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS(2)
(3)
AS
(4)
t
tWR
R/W"A"
INT"B"
(3)
t
INS
,
5683 drw 18
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
INT"B"
,
5683 drw 19
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
(4)
(4)
R/W
L
L
A
12L-A0L
R/W
X
R
A
12R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
X
L
CE
X
R
OE
R
INTR
L
X
1FFF
X
X
X
L(2)
H(3)
X
R
X
X
X
X
X
L
L
1FFF
1FFE
X
R
X
X
X
X
L(3)
L
L
X
L
X
L
L
1FFE
H(2)
X
X
X
X
L
5683 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12 is a NC for IDT70P34 and IDT70P24, therefore Interrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
(4)
A
12L-A0L
(1)
(1)
A
12R-A0R
Function
Normal
Normal
Normal
CE
X
L
CE
X
R
BUSY
H
L
BUSYR
NO MATCH
MATCH
H
H
H
X
H
X
H
MATCH
H
H
L
L
MATCH
(2)
(2)
Write Inhibit(3)
5683 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70P35/34L (IDT70P25/24L) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A12 is a NC for IDT70P34 and IDT70P24. Address comparison will be for A0 - A11.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left(2)
D0
- D17 Right(2)
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5683 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P35/34L (IDT70P25/24L).
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70P35/34 and I/O0-I/O15 for IDT70P25/24). These eight semaphores
are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
6.1482
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
SLAVE
Dual Port
SRAM
CE
MASTER
Dual Port
SRAM
BUSY
R
BUSY
R
BUSY
L
BUSY
L
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSY
R
BUSY
R
BUSYR
BUSY
L
BUSYL
BUSY
L
,
5683 drw 20
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P35/34L (IDT70P25/24L) SRAMs.
FunctionalDescription
The IDT70P35/34L (IDT70P25/24L) provides two ports with sepa- operationscanbepreventedtoaportbytyingtheBUSYpinforthatport
ratecontrol,addressandI/Opinsthatpermitindependentaccessforreads LOW.
orwritestoanylocationinmemory.TheIDT70P35/34L(IDT70P25/24L)
TheBUSYoutputsontheIDT70P35/34L(IDT70P25/24L)SRAMin
hasanautomaticpowerdownfeaturecontrolledbyCE.TheCEcontrols master mode, are push-pull type outputs and do not require pull up
on-chippowerdowncircuitrythatpermitstherespectiveporttogointoa resistorstooperate.IftheseSRAMsarebeingexpandedindepth,then
standby mode when not selected (CE HIGH). When a port is enabled, theBUSYindicationfortheresultingarrayrequirestheuseofanexternal
accesstotheentirememoryarrayispermitted.
ANDgate.
Width Expansion with Busy Logic
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
1FFE(HEX)(FFFforIDT70P34andIDT70P24),whereawrite isdefined
astheCER=R/WR=VIL perTruthTableIII.Theleftportclearstheinterrupt
by an address location 1FFE access when CEL = OEL = VIL, R/WL is a
"don'tcare".Likewise,therightportinterruptflag(INTR)issetwhenthe
leftportwritestomemorylocation1FFF(HEX)(FFFforIDT70P34and
IDT70P24)andtocleartheinterruptflag(INTR),therightportmustread
thememorylocation1FFF. Themessagetotheinterruptmailboxisuser-
defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction
isnotused,theinterruptaddresslocationsarenotusedasmailboxesbut
aspartoftherandomaccessmemory.
Master/Slave Arrays
When expanding an IDT70P35/34L (IDT70P25/24L) SRAM array
inwidthwhileusingBUSYlogic,onemasterpartisusedtodecidewhich
sideoftheSRAMarraywillreceiveaBUSYindication,andtooutputthat
indication. Any number of slaves to be addressed in the same address
rangeasthemaster,usetheBUSYsignalasawriteinhibitsignal.Thus
ontheIDT70P35/34L(IDT70P25/24L)SRAMtheBUSYpinisanoutput
ifthepartisusedasamaster(M/Spin=VIH),andtheBUSYpinisaninput
if the part used as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSYoutputs
togetheranduseany BUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. If the write inhibit function of
BUSYlogicisnotdesirable, the BUSYlogiccanbedisabledbyplacing
the part in slave mode with the M/Spin. Once in slave mode the BUSY
pinoperatessolelyasawriteinhibitinputpin. Normaloperationcanbe
programmedbytyingtheBUSYpinsHIGH.Ifdesired,unintendedwrite
Semaphores
TheIDT70P35/34L(IDT70P25/24L)isanextremelyfastDual-Port
8/4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address
locationsdedicatedtobinarysemaphoreflags.Theseflagsalloweither
processorontheleftorrightsideoftheDual-PortSRAMtoclaimaprivilege
overtheotherprocessorforfunctionsdefinedbythesystemdesigner’s
software.Asanexample,thesemaphorecanbeusedbyoneprocessor
6.42
19
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
toinhibittheotherfromaccessingaportionoftheDual-PortSRAMorany the SEM pin (which acts as a chip select for the semaphore flags) and
other shared resource. using the other control pins (Address, OE, and R/W) as they would be
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare usedinaccessingastandardstaticRAM. Eachoftheflagshasa
completelyindependentofeachother.Thismeansthattheactivityonthe unique address which can be accessed by either side through
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare address pins A0 –A2. When accessing the semaphores, none of the
identicalinfunctiontostandardCMOSStaticRAMandcanbeaccessed otheraddresspinshasanyeffect.
atthesametimewiththeonlypossibleconflictarisingfromthesimultaneous
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
writingof,orasimultaneousREAD/WRITEof,anon-semaphorelocation. iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
Semaphoresareprotectedagainstsuchambiguoussituationsandmay on that side and a one on the other side (see Truth Table V). That
be used by the system program to avoid any conflicts in the non- semaphorecannowonlybemodifiedbythesideshowingthezero.When
semaphore portion of the Dual-Port SRAM. These devices have an aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
automatic power-down feature controlled by CE, the Dual-Port SRAM settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol ispending)andthencanbewrittentobybothsides.Thefactthattheside
on-chip power down circuitry that permits the respective port to go into whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
standbymodewhennotselected.Thisistheconditionwhichisshownin fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
Truth Table I where CE and SEM are both HIGH.
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
Systems which can best use the IDT70P35/34L (IDT70P25/24L) shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
contain multiple processors or controllers and are typically very high- storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
speedsystemswhicharesoftwarecontrolledorsoftwareintensive.These freedbythefirstside.
systemscanbenefit fromaperformanceincreaseofferedbytheIDT70P35/
34L(IDT70P25/24L)'shardwaresemaphores,whichprovidealockout thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
mechanismwithoutrequiringcomplexprogramming. azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
Softwarehandshakingbetweenprocessorsoffersthemaximumin registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
system flexibility by permitting shared resources to be allocated in signalsgoactive.Thisservestodisallowthesemaphorefromchanging
varying configurations. The IDT70P35/34L (IDT70P25/24L) does not stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
useitssemaphoreflagstocontrolanyresourcesthroughhardware,thus Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
allowingthesystemdesignertotalflexibilityinsystemarchitecture.
cause either signal (SEM or OE) to go inactive or the output will never
An advantage of using semaphores rather than the more common change.
methods of hardware arbitration is that wait states are never incurred
A sequence WRITE/READ must be used by the semaphore in
in either processor. This can prove to be a major advantage in very order to guarantee that no system level contention will occur. A
high-speed systems.
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation. On
asubsequentread, theprocessorwillverifythatithaswrittensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
azerointhemeantime,thesemaphoreflagwillflipovertotheotherside
assoonasaoneiswrittenintothefirstside’srequestlatch.Thesecond
side’sflagwillnowstayLOWuntilitssemaphorerequestlatchiswrittento
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
TheeightsemaphoreflagsresidewithintheIDT70P35/34L
(IDT70P25/24L) in a separate memory space from the Dual-Port
SRAM. This address space is accessed by placing a LOW input on
6.2402
IDT70P35/34L (IDT70T25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
aone.Fromthisitiseasytounderstandthat,ifasemaphoreisrequested 4Ksectionbywriting,thenreadingazerointoSemaphore1.Ifitsucceeded
andtheprocessorwhichrequesteditnolongerneedstheresource,the ingainingcontrol,itwouldlockouttheleftside.
entiresystemcanhangupuntilaoneiswrittenintothatsemaphorerequest
latch.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
The critical case of semaphore timing is when both sides request a Semaphore 1 was still occupied by the right side, the left side could
single token by attempting to write a zero into it at the same time. The undo its semaphore request and perform other tasks until it was able
semaphore logic is specially designed to resolve this problem. If to write, then read a zero into Semaphore 1. If the right processor
simultaneous requests are made, the logic guarantees that only one performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
side receives the token. If one side is earlier than the other in making two processors to swap 4K blocks of Dual-Port SRAM with each other.
the request, the first side to make the request will receive the token. If
bothrequestsarriveatthesametime, theassignmentwillbearbitrarily variable, depending upon the complexity of the software using the
made to one port or the other. semaphore flags. All eight semaphores could be used to divide the
The blocks do not have to be any particular size and can even be
One caution that should be noted when using semaphores is that Dual-Port SRAM or other shared resources into eight parts. Sema-
semaphores alone do not guarantee that access to a resource is phores can even be assigned different meanings on different sides
secure. As with any powerful programming technique, if semaphores rather than being given a common meaning as was shown in the
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
example above.
Semaphores are a useful form of arbitration in systems like disk
handled via the initialization program at power-up. Since any sema- interfaces where the CPU must be locked out of a section of memory
phore request flag which contains a zero must be reset to a one, all during a transfer and the I/O device cannot tolerate any wait states.
semaphores on both sides should have a one written into them at With the use of semaphores, once the two devices has determined
initialization from both sides to assure that they will be free when which memory area was “off-limits” to the CPU, both the CPU and the
needed.
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
UsingSemaphores—SomeExamples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70P35/34L(IDT70P25/24L)’sDual-
Port SRAM. Say for example, the 8K x 18 SRAM was to be divided into
two4Kx18blockswhichweretobededicatedatanyonetimetoservicing
eithertheleftorrightport.Semaphore0couldbeusedtoindicatetheside
whichwouldcontrolthelowersectionofmemory,andSemaphore1could
bedefinedastheindicatorfortheuppersectionofmemory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a zero
in to Semaphore 0. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 4K. Meanwhile the right processor was attempting
togaincontrolofthe resourceaftertheleftprocessor,itwouldreadback
aoneinresponsetothezeroithadattemptedtowriteintoSemaphore0.
Atthispoint,thesoftwarecouldchoosetotryandgaincontrolofthesecond
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5683 drw 21
Figure 4. IDT70P35/34L (IDT70P25/24L) Semaphore Logic
6.42
21
IDT70P35/34L(IDT70P25/24L)
ADVANCED
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information(1)
IDT XXXXX
A
999
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
100-pin TQFP (PN100-1)
100-pin 0.8mm pitch fpBGA (BF100)
100-pin 0.5mm pitch fpBGA(BY100)(1)
PF
BF
BY
,
,
20
25
Commercial Only
Commercial & Industrial
Speed in Nanoseconds
L
Low Power
144K (8K x 18-Bit) 1.8V Dual-Port RAM
72K (4K x 18-Bit) 1.8V Dual-Port RAM
128K (8K x 16-Bit) 1.8V Dual-Port RAM
64K (4K x 16-Bit) 1.8V Dual-Port RAM
5683 drw 22
70P35
70P34
70P25
70P24
NOTE:
1. Available only for IDT70P25/24.
AdvancedDatasheet: Definition
"ADVANCED"datasheetscontaindescriptionsforproductsthatareinearlyrelease.
Datasheet Document History
01/26/04:
02/25/04:
InitialDatasheet
Page 1Corrected standby power from 18µW to 5.4mW for low-power operation
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