IDT70V24L35PFI [IDT]
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM; HIGH -SPEED 3.3V 4K ×16双口静态RAM
| 型号： | IDT70V24L35PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| 文件： | 总22页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
IDT70V24S/L
◆
IDT70V24 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Features
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25/35/55ns(max.)
Low-power operation
◆
◆
◆
◆
– IDT70V24S
Active:400mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V24L
◆
◆
◆
◆
Active:380mW(typ.)
Standby: 660µW (typ.)
Separate upper-byte and lower-byte control for multiplexed
◆
bus compatibility
Functional Block Diagram
R/WR
UBR
R/WL
UBL
LBR
CER
OER
LBL
CEL
OEL
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
I/O0L-I/O7L
BUSY(1,2)
(1,2)
BUSYR
L
A11L
A11R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
A0R
12
12
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
R/WR
WL
R/
SEMR
INTR
SEML
INTL
(2)
(2)
M/S
2911 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
MARCH 2000
1
DSC-2911/8
©2000IntegratedDeviceTechnology,Inc.
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
reads or writes to any location in memory. An automatic power down
TheIDT70V24isahigh-speed4Kx16Dual-PortStaticRAM.The
IDT70V24isdesignedtobeusedasastand-alone64K-bitDual-PortRAM featurecontrolledbyCE permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
orasacombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-more
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in32-bitorwidermemorysystemapplicationsresultsinfull-speed,error-
freeoperationwithouttheneedforadditionaldiscretelogic.
Thisdeviceprovidestwoindependentportswithseparatecontrol,
address,andI/Opinsthatpermitindependent,asyn-chronousaccessfor
Fabricated using IDT’s CMOS high-performance technology,
thesedevices typicallyoperateononly400mWofpower.
The IDT70V24is packagedina ceramic84-pinPGA, an84-Pin
PLCC and a 100-pin Thin Quad Flatpack.
Pin Configurations(1,2,3)
INDEX
11 10
12
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
I/O8L
I/O9L
7L
A
73
72
71
70
69
68
67
6L
A
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10L
I/O
I/O11L
12L
5L
A
4L
A
I/O
3L
A
I/O13L
GND
A2L
A
1L
14L
I/O
A
0L
I/O15L
VCC
66 INTL
IDT70V24J
(4)
L
BUSY
J84-1
65
64
63
GND
GND
84-Pin PLCC
Top View
0R
I/O
I/O
(5)
M/S
1R
R
62 BUSY
I/O2R
VCC
R
61 INT
60
59
58
57
56
55
54
A
0R
3R
I/O
1R
A
I/O4R
I/O5R
I/O6R
A2R
3R
A
29
30
31
32
4R
A
7R
I/O
I/O
A
5R
8R
6R
A
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2911 drw 02
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C
N/C
N/C
1
N/C
N/C
N/C
N/C
A5L
A4L
A3L
A2L
A1L
75
74
2
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
N/C
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A0L
IDT70V24PF
PN100-1
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
N/C
N/C
(4)
100-Pin TQFP
(5)
Top View
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2911 drw 03
6.42
2
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
63
61
60
58
55
54
51
48
46
A11L
44
A9L
45
A10L
43
A8L
41
A6L
38
A3L
35
A0L
31
42
A7L
40
A5L
39
A4L
37
A2L
34
11
10
09
08
07
06
05
04
03
02
01
I/O7L
I/O5L
I/O4L
I/O2L
I/O0L
OE
SEM
LB
L
L
L
L
66
I/O10L
64
62
59
56
49
50
47
I/O8L
I/O6L
I/O3L
I/O1L
N/C
UB
CE
L
67
I/O11L
69
I/O13L
72
I/O15L
75
65
57
53
VCC
52
R/WL
GND
I/O9L
68
I/O12L
71
I/O14L
70
73
VCC
74
33
BUSY
L
INTL
IDT70V24G
G84-3(4)
32
36
A1L
GND
I/O0R
GND
GND
M/S
84-Pin PGA
Top View(5)
76
77
78
VCC
28
29
30
I/O1R
A0R
I/O2R
INT
R
BUSY
R
79
80
26
A2R
23
27
I/O3R
I/O4R
A1R
81
83
7
11
12
25
SEM
R
5R
A
I/O5R
GND
GND
I/O7R
A3R
82
1
2
5
8
10
14
17
20
22
24
W
6R
9R
10R
13R
15R
R
11R
8R
6R
A
4R
I/O
I/O
I/O
I/O
I/O
R/
UB
A
A
A
R
84
3
4
6
9
15
13
16
18
19
21
I/O8R
I/O11R I/O12R I/O14R
N/C
A10R
A9R
A7R
OE
LB
CE
R
R
R
A
B
C
D
E
F
G
H
J
K
L
2911 drw 04
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
WR
Chip Enable
WL
R/
R/
Read/Write Enable
Output Enable
Address
OEL
OER
0L
A
11 L
0R
A
11R
- A
- A
0L
15L
0R
15R
I/O - I/O
SEML
UBL
I/O - I/O
SEMR
UBR
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
LBL
LBR
INT
INT
R
L
BUSYL
BUSYR
Busy Flag
S
M/
Master or Slave Select
Power
CC
V
GND
Ground
2911 tbl 01
6.42
3
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
X
L
I/O8-15
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Mode
Deselected: Power Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
L
L
H
L
H
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
2911 tbl 02
NOTE:
1. A0L — A11L ≠ A0R — A11R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
H
↑
I/O8-15
I/O0-7
Mode
CE
H
X
H
X
L
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
L
L
X
X
X
X
L
↑
L
DATAIN
DATAIN
____
____
X
X
L
____
____
L
X
L
Not Allowed
2911 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
6.42
4
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating Temperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Commercial
Industrial
0OC to +70OC
0V
0V
+
3.3V 0.3V
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
-40OC to +85OC
+
3.3V 0.3V
TBIAS
TSTG
IOUT
2911 tbl 05
NOTES:
Storage
Temperature
1. This is the parameter TA.
DC Output
Current
mA
2911 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
2. VTERM must not exceed Vcc +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period over VTERM > Vcc + 0.3V.
VCC
Supply Voltage
3.0
3.3
3.6
GND Ground
0
0
0
V
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
VCC+0.3(2)
0.8
V
____
-0.3(1)
V
____
Capacitance
(TA = +25°C, f = 1.0MHz)
2911 tbl 06
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
VIN = 3dV
Max. Unit
9
pF
COUT
VOUT = 3dV
11
pF
2911 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V24S
70V24L
Symbol
|ILI|
Parameter
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = +4mA
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
Input Leakage Current
___
___
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
VOL
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2911 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
5
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V24X15
Com'l Only
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
CC
I
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
IL
CE = V , Outputs Open
IH
SEM = V
(3)
MAX
f = f
____
____
____
____
IND
S
L
140
130
225
195
130
125
210
180
SB1
I
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
mA
mA
mA
R
L
IH
CE and CE = V
R
L
IH
SEM = SEM = V
MAX
f = f
(3)
____
____
____
____
MIL &
IND
S
L
20
15
45
40
16
13
45
40
(5)
IH
SB2
I
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
"A"
IL
"B"
CE = V and CE = V
Active Port Outputs Open,
(3)
MAX
f=f
____
____
____
____
MIL &
IND
S
L
80
75
130
115
75
72
125
110
R
L
IH
SEM = SEM = V
SB3
I
L
Full Standby Current
Both Ports CE and
R CC
CE > V - 0.2V,
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
IN
CC
CMOS Level Inputs)
V
V
> V - 0.2V or
< 0.2V, f = 0
____
____
____
____
(4)
MIL &
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
IN
R
L
CC
SEM = SEM > V -0.2V
SB4
I
Full Standby Current
(One Port -
CMOS Level Inputs)
"A"
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE < 0.2V and
(5)
"B"
CC
CE > V - 0.2V
R
L
CC
SEM = SEM > V -0.2V
____
____
____
____
IN
CC IN
> V - 0.2V or V < 0.2V
MIL &
IND
S
L
80
75
130
115
75
70
120
105
V
Active Port Outputs Open,
f = f
(3)
MAX
2911 tbl 09a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Open
SEM = VIH
L
(3)
f = fMAX
IND
S
L
120
115
200
170
120
115
200
170
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
11
25
20
13
11
25
20
mA
mA
mA
mA
CER and CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
MIL &
IND
S
L
13
11
40
35
13
11
40
35
(5)
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
70
65
100
90
70
65
100
90
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
MIL &
IND
S
L
70
65
120
105
70
65
120
105
SEMR = SEML = VIH
Full Standby Current
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
MIL &
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC-0.2V
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
65
60
100
85
65
60
100
85
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEMR = SEML > VCC-0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
MIL &
IND
S
L
65
60
115
100
65
60
115
100
(3)
f = fMAX
2911 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICC DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
6
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
AC Test Conditions
Input Pulse Levels
3.3V
GND to 3.0V
3ns Max.
1.5V
Input Rise/Fall Times
Ω
590
Ω
590
DATAOUT
BUSY
INT
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
1.5V
30pF
Ω
435
Ω
435
5pF*
Figures 1 and 2
2911 tbl 10
,
2911 drw 05
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
,
2911 drw 06
6.42
7
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V24X15
Com'l Only
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
tAA
tACE
Address Access Time
15
15
15
20
20
20
25
25
25
____
____
____
____
____
____
____
____
____
Chip Enable Access Time(3)
Byte Enable Access Time(3)
tABE
ns
Output Enable Access Time(3)
tAOE
tOH
tLZ
10
12
13
ns
ns
ns
ns
ns
ns
ns
____
____
____
Output Hold from Address Change
3
3
3
Output Low-Z Time(1,2)
____
____
____
3
3
3
____
____
____
Output High-Z Time(1,2)
tHZ
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
tPU
tPD
tSOP
tSAA
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
15
20
25
____
____
____
Semaphore Flag Update Pulse (OE or SEM)
10
10
10
Semaphore Address Access(3)
____
____
____
15
20
25
ns
2911 tbl 11a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
tAA
tACE
tABE
tAOE
tOH
tLZ
Address Access Time
35
35
35
55
55
55
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
20
30
____
____
3
3
____
____
3
3
Output High-Z Time(1,2)
15
25
____
____
tHZ
tPU
tPD
tSOP
tSAA
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
35
50
____
____
15
15
____
____
35
55
ns
2911 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
(4)
tABE
UB, LB
R/W
tOH
(1)
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
2911 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation
to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltage(5)
70V24X15
Com'l Only
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
12
0
15
0
20
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
10
12
15
____
____
____
tDH
0
0
0
(1,2)
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
ns
2911 tbl 12a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
25
0
40
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
15
30
____
____
15
25
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
15
25
Output Active from End-of-Write(1,2,4)
0
5
5
0
5
5
____
____
____
____
____
____
SEM Flag Write to Read Time
ns
Flag Contention Window
SEM
2911 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.42
10
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE SEM(9)
or
CE or SEM (9)
(3)
(6)
(2)
tWR
tAS
tWP
W
R/
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2911 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC
ADDRESS
tAW
(9)
or
CE SEM
(3)
(2)
(6)
tWR
tEW
tAS
(9)
or
UB LB
R/
W
tDW
tDH
DATAIN
2911 drw 09
NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for
the entire tEW time.
6.42
11
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tACE
tWR
tAW
tEW
SEM
tSOP
tDW
DATAIN
VALID
DATAOUT
VALID(2)
I/O0
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2911 drw 10
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15)equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
2911 drw 11
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = VIH.
2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag.
6.42
12
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingOemperatureandSupplyVoltageRange(6)
70V24X15
Com'l Ony
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
15
17
17
____
____
____
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
18
30
30
____
____
____
12
15
17
BUSY TIMING (M/S = VIL)
____
____
____
____
____
____
BUSY Input to Write(4)
tWB
tWH
0
0
0
ns
ns
Write Hold After BUSY(5)
12
15
17
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
____
____
____
____
____
30
25
45
35
50
35
ns
ns
2911 tbl 13a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
20
35
____
____
5
5
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
35
40
____
____
25
25
BUSY TIMING (M/S = VIL)
____
____
____
____
BUSY Input to Write(4)
tWB
tWH
0
0
ns
ns
Write Hold After BUSY(5)
25
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
____
____
____
____
60
45
80
65
ns
ns
2911 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write
With Port-To-Port Delay (M/S = VIL)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
6.42
13
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
2911 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
6.42
14
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Slave Write (M/S = VIL)
tWP
R/W
"A"
(3)
tWB
BUSY"B"
R/W"B"
(1)
tWH
(2)
2911 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “slave” version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
"B"
CE
tBAC
tBDC
BUSY"B"
2911 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
2911 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V24X15
Com'l Only
70V24X20
Com'l
& Ind
70V24X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
15
15
20
20
20
20
____
____
____
Interrupt Reset Time
ns
2911 tbl 14a
70V24X35
Com'l
& Ind
70V24X55
Com'l
& Ind
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
____
____
25
25
40
40
____
____
Interrupt Reset Time
ns
2911 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
16
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS(2)
(3)
(4)
tAS
tWR
CE"A"
R/
W"A"
(3)
tINS
INT"B"
2911 drw 16
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
2911 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III Interrupt Flag(1)
Left Port
Right Port
R/WL
L
A11L-A0L
FFF
X
R/WR
X
A11R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INTR
(2)
L
(3)
X
X
X
X
X
L
L
FFF
FFE
X
H
(3)
X
X
X
X
L
L
L
X
X
X
(2)
X
L
L
FFE
H
X
X
X
Reset Left INTL Flag
2911 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
0L 11L
A -A
(1)
(1)
A
0R-A11R
Function
Normal
Normal
Normal
CE
L
CER
X
BUSYL
BUSYR
X
H
X
L
NO MATCH
MATCH
H
H
H
X
H
H
MATCH
H
H
(3)
L
MATCH
(2)
(2)
Write Inhibit
2911 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V24 are push
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2911 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V24.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
6.42
18
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
MASTER
SLAVE
Dual Port
SRAM
CE
CE
Dual Port
SRAM
BUSYL
BUSYR
BUSYL
BUSYR
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSYR
BUSYR
BUSY
BUSY
L
L
BUSYR
BUSYL
2911 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V24 SRAMs.
Functional Description
prevented to a port by tying the BUSY pin for that port LOW.
ThebusyoutputsontheIDT70V24SRAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
The IDT70V24 provides two ports with separate control, address
andI/Opinsthatpermitindependentaccesstoanylocationinmemory.
TheIDT70V24hasanautomaticpowerdownfeaturecontrolledbyCE.
The CE controls on-chip power down circuitry that permits the respec-
tive port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is
permitted.
Width Expansion with BUSY Logic
Master/Slave Arrays
Interrupts
WhenexpandinganIDT70V24SRAMarrayinwidthwhileusingbusy
logic,onemasterpartisusedtodecidewhichsideoftheSRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemaster,usethe
BUSYsignalas awriteinhibitsignal.Thus ontheIDT70V24SRAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
FFE (HEX), where a write is defined as the CE=R/W=VIL per Truth
Table III. The left port clears the interrupt by accessing address
location FFE when CER = OER = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location FFF (HEX) and to clear the interrupt flag (INTR),
the right port must read the memory location FFF. The message (16
bits) at FFE or FFF is user-defined, since it is an addressable SRAM
location.Iftheinterruptfunctionisnotused,addresslocationsFFEand
FFF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table IIII for the interrupt operation.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actualwrite pulse canbe initiatedwitheitherthe R/Wsignalorthe byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
thattheSRAMis“busy”.TheBUSYpincanthenbeusedtostalltheaccess
untiltheoperationon theothersideiscompleted.Ifawriteoperationhas
beenattemp-tedfromthesidethatreceivesaBUSYindication,thewrite
signalisgatedinternallytopreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
Semaphores
The IDT70V24is anextremelyfastDual-Port4Kx16CMOSStatic
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags alloweitherprocessoronthe leftorright
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the otherfromaccessinga portionofthe Dual-PortSRAMoranyother
shared resource.
6.42
19
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare StaticRAM.Eachoftheflagshasauniqueaddresswhichcanbeaccessed
completelyindependentofeachother.Thismeansthattheactivityonthe by either side through address pins A0 – A2. When accessing the
leftportinnowayslows theaccess timeoftherightport.Bothports are semaphores,noneoftheotheraddresspinshasanyeffect.
identicalinfunctiontostandardCMOSStaticRAMandcanbeaccessed
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
to, at the same time with the only possible conflict arising from the iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
simultaneous writing of, or a simultaneous READ/WRITE of, a non- on that side and a one on the other side (see Truth Table V). That
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous semaphorecannowonlybemodifiedbythesideshowingthezero.When
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
in the non-semaphore portion of the Dual-Port SRAM. These devices settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
haveanautomaticpower-downfeaturecontrolledbyCE,theDual-Port ispending)andthencanbewrittentobybothsides.Thefactthattheside
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
intostandbymodewhennotselected.Thisistheconditionwhichisshown communications.(Athoroughdiscussionontheuseofthisfeaturefollows
in Truth Table I where CE and SEM are both HIGH.
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
SystemswhichcanbestusetheIDT70V24containmultipleprocessors storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
or controllers and are typically very high-speed systems which are freedbythefirstside.
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
a performance increase offered by the IDT70V24's hardware sema- thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
phores,whichprovidealockoutmechanismwithoutrequiringcomplex azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
programming.
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
Softwarehandshakingbetweenprocessors offers themaximumin signalsgoactive.Thisservestodisallowthesemaphorefromchanging
system flexibility by permitting shared resources to be allocated in stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
varying configurations. The IDT70V24 does not use its semaphore Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
flags to control any resources through hardware, thus allowing the cause either signal (SEM or OE) to go inactive or the output will never
system designer total flexibility in system architecture.
change.
A sequence WRITE/READ must be used by the semaphore in
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred order to guarantee that no system level contention will occur. A
in either processor. This can prove to be a major advantage in very processor requests access to shared resources by attempting to write
high-speed systems.
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation.On
asubsequentread,theprocessorwillverifythatithas writtensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
sideassoonasaoneiswrittenintothefirstside’srequestlatch.Thesecond
side’sflagwillnowstayLOWuntilitssemaphorerequestlatchiswrittento
aone.Fromthisitiseasytounderstandthat,ifasemaphoreisrequested
andtheprocessorwhichrequesteditnolongerneedstheresource,the
entiresystemcanhangupuntilaoneiswrittenintothatsemaphorerequest
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V24 in a
separate memory space from the Dual-Port SRAM. This address
spaceisaccessedbyplacingaLOWinputontheSEMpin(whichactsas
a chip select for the semaphore flags) and using the other control pins
(Address,OE,andR/W)astheywouldbeusedinaccessingastandard
6.42
20
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
latch.
Once the left side was finished with its task, it would write a one to
The critical case of semaphore timing is when both sides request Semaphore 0 and may then try to gain access to Semaphore 1. If
a single tokenbyattemptingtowrite a zerointoitatthe same time. The Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
semaphore logic is specially designed to resolve this problem. If itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
simultaneous requests are made, the logic guarantees that only one readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
side receives the token. If one side is earlier than the other in making withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
the request, the first side to make the request will receive the token. If 2Kblocks ofDual-PortSRAMwitheachother.
bothrequests arriveatthesametime,theassignmentwillbearbitrarily
made to one port or the other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
One caution that should be noted when using semaphores is that semaphore flags. All eight semaphores could be used to divide the
semaphores alone do not guarantee that access to a resource is Dual-Port SRAM or other shared resources into eight parts. Sema-
secure. As with any powerful programming technique, if semaphores phores can even be assigned different meanings on different sides
are misused or misinterpreted, a software error can easily happen.
rather than being given a common meaning as was shown in the
Initialization of the semaphores is not automatic and must be example above.
handled via the initialization program at power-up. Since any sema-
Semaphores are a useful form of arbitration in systems like disk
phore request flag which contains a zero must be reset to a one, all interfaces where the CPU must be locked out of a section of memory
semaphores on both sides should have a one written into them at during a transfer and the I/O device cannot tolerate any wait states.
initialization from both sides to assure that they will be free when With the use of semaphores, once the two devices has determined
needed.
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
UsingSemaphoresSomeExamples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70V24’sDual-PortSRAM. Saythe
4K x 16 SRAM was to be divided into two 2K x 16 blocks which were to
be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
To take a resource, in this example the lower 2K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 2K. Meanwhile the right processor was
attemptingtogaincontrolofthe resourceaftertheleftprocessor,itwould
read back a one in response to the zero it had attempted to write into
Semaphore0.Atthispoint,thesoftwarecouldchoosetotryandgaincontrol
ofthesecond2Ksectionbywriting,thenreadingazerointoSemaphore
1.Ifitsucceededingainingcontrol,itwouldlockouttheleftside.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2911 drw 19
Figure 4. IDT70V24 Semaphore Logic
6.42
21
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
J
100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Speed in nanoseconds
S
L
Standard Power
Low Power
70V24 64K (4K x 16) 3.3V Dual-Port RAM
2911 drw 20
Datasheet Document History
3/8/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
Changed drawing format
Page 2 TQFP for corrected pinout (no pin 55 was shown)
Page1Changed660mWto660µW
Replaced IDT logo
6/10/99:
8/1/99:
8/30/99:
11/12/99:
3/10/00:
Added 15 and 20ns speed grades
UpgradedDCparameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mVinnotes
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