IDT70V24TL20JI8 [IDT]
Multi-Port SRAM, 4KX16, 20ns, CMOS, CQCC84;
| 型号： | IDT70V24TL20JI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multi-Port SRAM, 4KX16, 20ns, CMOS, CQCC84 静态存储器 |
| 文件： | 总25页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
IDT70V35/34S/L
IDT70V25/24S/L
◆
Features
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆
True Dual-Ported memory cells which allow simultaneous
◆
◆
reads of the same memory location
High-speed access
◆
IDT70V35/34
– Commercial:15/20/25ns (max.)
– Industrial:20ns
◆
◆
◆
IDT70V25/24
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25ns
Low-power operation
◆
◆
◆
◆
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
Active: 415mW (typ.)
Standby: 660µW (typ.)
◆
– IDT70V25/24S
–
IDT70V25/24L
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
Active: 380mW (typ.)
Standby: 660µW (typ.)
Functional Block Diagram
R/W
L
R/W
R
R
UBL
UB
LB
CE
OE
R
LB
CE
OE
L
R
R
L
L
,
(5)
(5)
I/O9R-I/O17R
I/O9L-I/O17L
I/O
Control
I/O
Control
(4)
(4)
I/O0R-I/O8R
I/O0L-I/O8L
(2,3)
L
(2,3)
BUSY
R
BUSY
(1)
12R
(1)
12L
A
A
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
A
0R
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
R
CE
OE
L
L
R
R
R/W
L
SEM
R
SEM
INTL
L
(3)
(3)
INTR
M/S
5624 drw 01
NOTES:
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70V25/24.
5. I/O8x - I/O15x for IDT70V25/24.
OCTOBER 2004
1
DSC-5624/5
©2004IntegratedDeviceTechnology,Inc.
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V35/34 (IDT70V25/24) is a high-speed 8/4K x 18 (8/4K featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
x16) Dual-Port Static RAM. The IDT70V35/34 (IDT70V25/24) is de- a very low standby power mode.
signedtobeusedasastand-aloneDual-PortRAMorasacombination
FabricatedusingIDT’sCMOShigh-performancetechnology,these
MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory devices typically operate on only 430mW (IDT70V35/34) and 400mW
systemapplicationsresultsinfull-speed,error-freeoperationwithoutthe (IDT70V25/24) of power.
needforadditionaldiscretelogic.
The IDT70V35/34 (IDT70V25/24) is packaged in a plastic 100-pin
This device provides two independent ports with separate control, ThinQuadFlatpack. TheIDT70V25/24ispackagedinaceramic84-pin
address,andI/Opinsthatpermitindependent,asynchronousaccessfor PGA and 84-Pin PLCC.
reads or writes to any location in memory. An automatic power down
PinConfigurations(1,2,3,4)
06/24/04
Index
100 99 98 9796 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
Vss
N/C
N/C
N/C
N/C
75
74
2
3
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
4
5
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O15L
I/O16L
IDT70V35/34PF
INT
L
(5)
PN100-1
VDD
BUSY
Vss
M/S
L
Vss
I/O0R
I/O1R
I/O2R
100-Pin TQFP
(6)
Top View
BUSY
R
INT
R
VDD
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
5624 drw 02
NOTES:
1. A12 is a NC for IDT70V34.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.422
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3,4)(con't)
06/24/04
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
75
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N/C
N/C
N/C
3
4
N/C
5
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
I/O10L
I/O11L
I/O12L
I/O13L
6
7
8
VSS
9
I/O14L
I/O15L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70V25/24PF
PN100-1(4)
INT
L
BUSY
L
V
V
DD
SS
100-Pin TQFP
Top View(5)
V
SS
M/S
BUSY
I/O0R
I/O1R
I/O2R
R
INT
R
A
A
A
A
A
0R
VDD
1R
2R
3R
4R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5624 drw 03
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3,4)(con't)
06/11/04
63
61
60
58
55
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
I/O7L
I/O5L
I/O4L
I/O2L
I/O0L
A
11L
A
10L
A
7L
5L
OE
L
SEM
L
LBL
66
I/O10L
67
I/O11L
69
I/O13L
72
I/O15L
75
64
62
59
56
49
50
47
44
43
41
40
(1)
12L
I/O8L
I/O6L
I/O3L
I/O1L
A
A
9L
A
8L
A
UBL
CEL
65
57
53
52
39
V
SS
V
DD
I/O9L
A
6L
3L
0L
R/W
L
A
4L
2L
68
I/O12L
71
I/O14L
70
38
37
A
A
73
33
35
34
BUSY
L
A
VDD
INT
L
IDT70V25/24
G
74
32
31
36
G84-3(4)
V
SS
V
SS
VSS
I/O0R
M/S
A
1L
84-Pin PGA
Top View(5)
76
77
78
28
29
30
I/O1R
V
DD
I/O2R
A
0R
INT
R
BUSY
R
79
80
26
27
I/O3R
A2R
I/O4R
A
1R
3R
81
83
7
8
11
12
23
25
VSS
SEMR
A
5R
I/O5R
VSS
I/O7R
I/O9R
A
82
1
2
5
10
14
17
20
22
24
I/O6R
I/O10R I/O13R I/O15R R/W
R
A11R
A
8R
A
6R
9R
A
4R
7R
UB
R
84
3
4
6
9
15
13
16
18
19
21
(1)
I/O8R
I/O11R I/O12R I/O14R
A12R
A10R
A
A
OER
LBR
CER
A
B
C
D
E
F
G
H
J
K
L
5624 drw 04
Index
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.442
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3,4)(con't)
06/08/04
INDEX
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
I/O8L
I/O9L
A
A
A
A
A
A
A
A
7L
6L
5L
4L
3L
2L
1L
0L
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O10L
I/O11L
I/O12L
I/O13L
V
SS
I/O14L
I/O15L
IDT70V25/24J
J84-1(4)
INT
L
BUSY
L
V
DD
SS
84-Pin PLCC
Top View(5)
V
SS
V
I/O0R
I/O1R
I/O2R
M/S
BUSY
R
INT
R
V
DD
A
A
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
1R
2R
3R
4R
5R
6R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
,
5624 drw 05
NOTES:
1. A12 is a NC for IDT70V24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
5
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R
L
R/W
R
Read/Write Enable
Output Enable
L
OE
R
(1)
(1)
A
0L - A12L
I/O0L - I/O17L
SEM
UB
LB
INT
BUSY
A
0R - A12R
Address
(2)
(2)
I/O0R - I/O17R
Data Input/Output
Semaphore Enable
L
SEM
UB
LB
INT
BUSY
M/S
R
(3)
Upper Byte Select
L
R
NOTES:
(4)
Lower Byte Select
L
R
1. A12 is a NC for IDT70V34 and for IDT70V24.
2. I/O0x - I/O15x for IDT70V25/24.
3. Upper Byte Select controls pins 9-17 for IDT70V35/34 and controls pins 8-15
for IDT70V25/24.
4. Lower Byte Select controls pins 0-8 for IDT70V35/34 and controls pins 0-7
for IDT70V25/24.
Interrupt Flag
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3V)
V
DD
VSS
Ground (0V)
5624 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
(3)
(2)
R/W
X
X
L
I/O9-17
I/O0-8
Mode
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
High-Z
High-Z
DATAIN
High-Z
DATAIN
High-Z
High-Z
Deselected: Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
H
High-Z
L
L
H
L
H
DATAIN
DATAIN
High-Z
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
DATAOUT
DATAOUT
High-Z
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
5624 tbl 02
NOTES:
1. A0L-A12L ≠ A0R-A12R for IDT70V35/34 and A0L-A11L ≠ A0R-A11R for IDT70V25/24.
2. Outputs for IDT70V25/24 are I/O0x-I/O7x.
3. Outputs for IDT70V25/24 are I/O8x-I/O15x.
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
(1)
(1)
R/W
H
H
↑
I/O9-17
I/O0-8
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
CE
H
X
H
X
L
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
L
L
X
X
X
X
L
Write I/O into Semaphore Flag
0
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
↑
____
____
X
X
L
Not Allowed
Not Allowed
____
____
L
X
L
5624 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
6.462
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
VDD
(2)
V
TERM
Te rminal Vo ltag e
with Respect
to GND
-0.5 to +4.6
V
Commercial
0OC to +70OC
0V
0V
3.3V
3.3V
+
0.3V
T
BIAS
Te mp e rature
Under Bias
-55 to +125
-65 to +150
oC
oC
Industrial
-40OC to +85OC
+
0.3V
5624 tbl 05
NOTE:
Storage
Te mp e rature
TSTG
1. This is the parameter TA. This is the "instant on" case temperature.
T
JN
Junction Temperature
+150
50
oC
DC Output
Current
mA
IOUT
5624 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
Typ.
Max.
3.6
0
Unit
V
V
DD
SS
IH
IL
3.3
V
0
0
V
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
____
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(2)
V
____
V
-0.3(1)
0.8
V
Capacitance(1) (TA = +25°C, f = 1.0MHz)
5624 tbl 06
NOTES:
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
CIN
V
9
pF
(2)
C
OUT
V
10
pF
5624 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ꢀ.3Vꢁ
70V35/34/25/24S
70V35/34/25/24L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
DD = 3.6V, VIN = 0V to VDD
___
___
___
___
|
Output Leakage Currentt(1)
Output Low Voltage
10
5
CE = VIH, VOUT = 0V to VDD
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
5624 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
6.42
7
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V35/34(1) (VDD = 3.3V ꢀ.3Vꢁ
70V35/34X15
Com'l Only
70V35/34X20
Com'l
70V35/34X25
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
140
130
225
195
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
mA
mA
mA
CE
SEM
f = fMAX
R
and CE
L
= VIH
R
= SEML = VIH
(3)
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
15
45
40
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
80
75
130
115
SEM
R
= SEML = VIH
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
L
and
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
R
V
SEINM
V
____
____
____
____
____
____
____
____
< 0.2V, f = 0(4)
MIL &
IND
S
L
1.0
0.2
15
5
R
= SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE < 0.2V and
CE"BA"" > VDD - 0.2V
(5)
SEM
R
= SEML > VDD - 0.2V
____
____
____
____
MIL &
IND
S
L
80
75
130
115
V
IN > VDD - 0.2V or VIN < 0.2V
____
____
____
____
Active Port Outputs Disabled,
(3)
f = fMAX
5624 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
AC Test Conditions
3.3V
3.3V
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
1.5V
5pF*
435Ω
30pF
435Ω
Figures 1 and 2
,
5624 tbl 10
5624 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test
Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
tPU
tPD
I
CC
SB
50%
50%
I
,
5624 drw 07
6.482
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range for 70V25/24(1) (VDD = 3.3V ꢀ.3Vꢁ
70V25/24X15
Com'l Only
70V25/24X20
Com'l
70V25/24X25
Com'l
& Ind
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Open
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
IND
S
L
140
130
225
195
125
180
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
mA
mA
mA
CE
SEM
f = fMAX
R
and CE
L
= VIH
R
= SEM
L = VIH
(3)
____
____
____
____
____
____
MIL &
IND
S
L
20
15
45
40
13
40
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
SEM
____
____
____
____
____
____
MIL &
IND
S
L
80
75
130
115
R
= SEML = VIH
72
110
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
L
and
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
R
V
(4)
____
____
____
____
____
____
MIL &
IND
S
L
1.0
0.2
15
5
VIN < 0.2V, f = 0
0.2
5
SEM = SEM > VDD - 0.2V
R
L
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE"A" < 0.2V and
(5)
CE"B" > VDD - 0.2V
SEM = SEM > VDD - 0.2V
IN > VDD - 0.2V or VIN < 0.2V
R
L
____
____
____
____
____
____
MIL &
IND
S
L
80
75
130
115
V
70
105
Active Port Outputs Open,
(3)
f = fMAX
5624 tbl 09a
70V25/24X35
Com'l
70V25/24X55
Com'l
& Ind
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Open
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
11
25
20
13
11
25
20
mA
mA
mA
mA
CE
SEM
f = fMAX
R
and CE
L
= VIH
R
= SEML = VIH
(3)
____
____
____
____
____
____
____
____
MIL &
IND
S
L
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
70
65
100
90
70
65
100
90
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(3)
f=fMAX
SEM
____
____
____
____
____
____
____
____
MIL &
IND
S
L
R
= SEML = VIH
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
L
and
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
R
V
V
SEINM
____
____
____
____
____
____
____
____
< 0.2V, f = 0(4)
MIL &
IND
S
L
R
= SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
65
60
100
85
65
60
100
85
CE"A" < 0.2V and
(5)
CE"B" > VDD- 0.2V
SEM = SEM > VDD - 0.2V
IN > VDD - 0.2V or VIN < 0.2V
R
L
MIL &
IND
S
L
V
____
____
____
____
____
____
____
____
Active Port Outputs Open,
(3)
f = fMAX
5624 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
9
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRangefor70V35/34(4)
70V35/34X15
Com'l Only
70V35/34X20
Com'l
70V35/34X25
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
t
Address Access Time
15
15
15
20
20
20
25
25
25
____
____
____
____
____
____
____
____
____
Chip Enable Access Time(3)
Byte Enable Access Time(3)
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
t
10
12
13
____
____
____
t
Output Hold from Address Change
3
3
3
____
____
____
Output Low-Z Time(1,2)
t
3
3
3
____
____
____
Output High-Z Time(1,2)
t
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
t
15
20
25
____
____
____
t
10
10
10
____
____
____
t
15
20
25
ns
5624 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
t
ABE
UB, LB
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
5624 drw 08
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.1402
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRangefor70V25/24(4)
70V25/24X15
Com'l Only
70V25/24X20
70V25/24X25
Com'l
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
t
Address Access Time
15
15
15
20
20
20
25
25
25
Chip Enable Access Time(3)
Byte Enable Access Time(3)
____
____
____
____
____
____
____
____
____
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
t
10
12
13
____
____
____
t
3
3
3
____
____
____
t
3
3
3
____
____
____
Output High-Z Time(1,2)
t
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
t
15
20
25
____
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
10
____
____
____
Semaphore Address Access(3)
t
15
20
25
ns
5624 tbl 11a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
35
35
35
55
55
55
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
t
20
30
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
15
25
____
____
t
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
t
35
50
____
____
t
15
15
____
____
t
35
55
ns
5624 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
6.42
11
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V35/34(5)
70V35/34X15
Com'l Only
70V35/34X20
Com'l
70V35/34X25
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
15
____
____
____
t
10
12
15
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
5624 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.1422
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage for 70V25/24(5)
70V25/24X15
Com'l Only
70V25/24X20
Com'l
70V25/24X25
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
15
____
____
____
t
10
12
15
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
5624 tbl 12a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
25
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
30
____
____
t
15
25
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
15
25
t
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
5624 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for
the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.42
13
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM (9)
CE or SEM (9)
R/W
(3)
WR
(2)
(6)
t
tAS
tWP
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
5624 drw 09
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
CE or SEM(9)
UB or LB(9)
t
AW
(3)
(6)
(2)
t
WR
t
EW
tAS
R/W
t
DW
tDH
DATAIN
5624 drw 10
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or UB or LB.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. tEW must be met for either condition.
6.1442
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
WR
tACE
tAW
t
EW
SEM
t
SOP
t
DW
DATAOUT
VALID(2)
DATAIN
VALID
I/O0
t
AS
tWP
tDH
R/W
t
AOE
t
SWRD
OE
Write Cycle
Read Cycle
5624 drw 11
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
5624 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.42
15
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRangefor70V35/34(6)
70V35/34X15
Com'l Ony
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Dis able Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
18
30
30
(5)
____
____
____
t
Write Hold After BUSY
12
15
17
BUSY TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5624 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
MATCH
t
WP
R/W"A"
tDH
tDW
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
t
BAA
t
BDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
NOTES:
5624 drw 13
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
6.1462
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
TemperatureandSupply VoltageRangefor70V25/24(6)
70V25/24X15
Com'l Ony
70V25/24X20
70V25/24X25
Com'l
Com'l
& Ind
& Ind
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
18
30
30
t
Write Hold After BUSY(5)
12
15
17
____
____
____
BUSY TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
ns
ns
tWH
12
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5624 tbl 13a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
20
35
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
35
40
t
Write Hold After BUSY(5)
25
25
____
____
BUSY TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
60
45
80
65
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5624 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part number indicates power rating (S or L).
6.42
17
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
t
WP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
tWH
(2)
R/W"B"
,
5624 drw 14
NOTES:
1. tWH must be met for both master BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
5624 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
NOTES:
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
5624 drw 16
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.1482
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
TemperatureandSupply VoltageRangefor70V35/34(1)
70V35/34X15
Com'l Only
70V35/34X20
70V35/34X25
Com'l Only
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
15
15
20
20
20
20
____
____
____
t
Interrupt Reset Time
ns
5624 tbl 14
AC Electrical Characteristics Over the Operating
TemperatureandSupply VoltageRangefor70V25/24(1)
70V25/24X15
Com'l Only
70V25/24X20
70V25/24X25
Com'l
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
15
15
20
20
20
20
____
____
____
t
Interrupt Reset Time
ns
5624 tbl 14a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
25
25
40
40
____
____
t
Interrupt Reset Time
ns
5624 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
19
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
CE"A"
INTERRUPT SET ADDRESS (2)
(3)
AS
(4)
t
tWR
R/W"A"
INT"B"
(3)
tINS
5624 drw 17
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
5624 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.2402
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
(4)
Right Port
(4)
12R-A0R
R/W
L
A12L-A0L
R/W
R
A
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OEL
INT
L
CE
R
OER
INTR
(2)
L
L
X
X
L
X
X
X
L
1FFF(4)
X
X
X
X
L
L
X
X
L
X
L
R
(3)
X
X
X
1FFF(4)
1FFE(4)
X
H
R
(3)
X
X
L
L
X
X
X
X
L
(2)
X
1FFE(4)
H
X
L
5624 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A12 is a NC for IDT70V34 and for IDT70V24, therefore Interrupt Addresses are FFF and FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
(4)
A
12L-A0L
(1)
(1)
A
12R-A0R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
MATCH
H
(3)
MATCH
Note(2)
Note(2)
Write Inhibit
5624 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V35/34 (IDT70V25/24) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A12 is a NC for IDT70V34 and for IDT70V24. Address comparison will be for A0 - A11.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left(2)
D0
- D17 Right(2)
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5624 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V35/34 (IDT70V25/24).
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70V35/34) and (I/O0-I/O15 for IDT70V25/24). These eight semaphores
are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables.
6.42
21
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
SLAVE
Dual Port
SRAM
CE
MASTER
Dual Port
SRAM
BUSY
R
BUSY
R
BUSY
L
BUSY
L
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSY
R
BUSY
R
BUSYR
BUSY
L
BUSYL
BUSY
L
5624 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V35/34 (IDT70V25/24) SRAMs.
FunctionalDescription
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V35/34 (IDT70V25/24) SRAM in
master mode, are push-pull type outputs and do not require pull up
resistorstooperate.IftheseSRAMsarebeingexpandedindepth,then
theBUSYindicationfortheresultingarrayrequirestheuseofanexternal
ANDgate.
TheIDT70V35/34(IDT70V25/24)providestwoportswithseparate
control,addressandI/Opinsthatpermitindependentaccessforreadsor
writestoanylocationinmemory.TheIDT70V35/34(IDT70V25/24)has
anautomaticpowerdownfeaturecontrolledbyCE.TheCEcontrolson-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE HIGH). When a port is enabled,
accesstotheentirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX)(FFEforIDT70V34andIDT70V24), where a write is definedas
theCER=R/WR=VIL perTruthTableIII.Theleftportclearstheinterrupt
Width Expansion with Busy Logic
Master/SlaveArrays
When expanding an IDT70V35/34 (IDT70V25/24) SRAM array in
ontheIDT70V35andIDT70V25byanaddress location1FFE(FFEfor widthwhileusingBUSYlogic,onemasterpartisusedtodecidewhichside
IDT70V34andIDT70V24)accesswhenCEL=OEL=VIL,R/WLisa"don't of the SRAM array will receive a BUSY indication, and to output that
care".Likewise,therightportinterruptflag(INTR)issetwhentheleftport indication. Anynumberofslaves tobe addressedinthe same address
writestomemorylocation1FFFforIDT70V35andIDT70V25(HEX)(FFF rangeasthemaster,usetheBUSYsignalasawriteinhibitsignal.Thus
forIDT70V34andIDT70V24)andtoclearthe interruptflag(INTR), the ontheIDT70V35/34(IDT70V25/24)SRAMtheBUSYpinisanoutputif
right port must read the memory location 1FFF for IDT70V35 and thepartisusedasamaster(M/Spin=VIH),andtheBUSYpinisaninput
IDT70V25(FFFforIDT70V34andIDT70V24). The message (16bits) if the part used as a slave (M/S pin = VIL) as shown in Figure 3.
at 1FFE or 1FFF for IDT70V35 and IDT70V25 (FFE or FFF for
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
IDT70V34 and IDT70V24) is user-defined, since it is an addressable decisioncouldresultwithonemasterindicatingBUSYononesideofthe
SRAMlocation.Iftheinterruptfunctionisnotused,addresslocations1FFE arrayandanothermasterindicatingBUSYononeothersideofthearray.
and1FFFforIDT70V35andIDT70V25(FFEandFFFforIDT70V34and Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
IDT70V24)arenotusedasmailboxes,butaspartoftherandomaccess inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
memory.RefertoTruthTableIIIfortheinterruptoperation.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheSRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheSRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT70V35/34(IDT70V25/24)is anextremelyfastDual-Port8/
TheuseofBUSYlogicisnotrequiredordesirableforallapplications. 4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether locationsdedicatedtobinarysemaphoreflags.Theseflagsalloweither
anduse anyBUSYindicationas aninterruptsource toflagthe eventof processorontheleftorrightsideoftheDual-PortSRAMtoclaimaprivilege
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis overtheotherprocessorforfunctionsdefinedbythesystemdesigner’s
6.2422
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
a chip select for the semaphore flags) and using the other control pins
(Address,OE,andR/W)astheywouldbeusedinaccessingastandard
staticRAM.Eachoftheflagshasauniqueaddresswhichcanbeaccessed
by either side through address pins A0 – A2. When accessing the
semaphores,noneoftheotheraddresspinshasanyeffect.
software.Asanexample,thesemaphorecanbeusedbyoneprocessor
toinhibittheotherfromaccessingaportionoftheDual-PortSRAMorany
other shared resource.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbeaccessed
atthesametimewiththeonlypossibleconflictarisingfromthesimultaneous
writingof,orasimultaneousREAD/WRITEof,anon-semaphorelocation.
Semaphoresareprotectedagainstsuchambiguoussituationsandmay
be used by the system program to avoid any conflicts in the non-
semaphore portion of the Dual-Port SRAM. These devices have an
automatic power-down feature controlled byCE, the Dual-Port SRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected.Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT70V35/34(IDT70V25/24)contain
multiple processors or controllers and are typically very high-speed
systems which are software controlled or software intensive. These
systemscanbenefit fromaperformanceincreaseofferedbytheIDT70V35/
34 (IDT70V25/24)'s hardware semaphores, which provide a lockout
mechanismwithoutrequiringcomplexprogramming.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT70V35/34(IDT70V25/24)doesnotuseitssema-
phoreflagstocontrolanyresourcesthroughhardware,thusallowingthe
systemdesignertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecond side’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requestedandthe processorwhichrequesteditnolongerneeds the
resource,theentiresystemcanhangupuntilaoneis writtenintothat
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortSRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst,hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
TheeightsemaphoreflagsresidewithintheIDT70V35/34(IDT70V25/
24)inaseparatememoryspacefromtheDual-PortSRAM.Thisaddress
spaceisaccessedbyplacingaLOWinputontheSEMpin(whichactsas
6.42
23
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
semaphorerequestlatch.Thecriticalcaseofsemaphoretimingiswhen control,itwouldlockouttheleftside.
bothsidesrequestasingletokenbyattemptingtowriteazerointoitatthe
Once the left side was finished with its task, it would write a one to
same time. The semaphore logic is specially designed to resolve this Semaphore 0 and may then try to gain access to Semaphore 1. If
problem.Ifsimultaneousrequestsaremade,thelogicguaranteesthatonly Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
onesidereceivesthetoken.Ifonesideisearlierthantheotherinmaking itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
therequest,thefirstsidetomaketherequestwillreceivethetoken.Ifboth readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
requestsarriveatthesametime,theassignmentwillbearbitrarilymade withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
to one port or the other.
4Kblocks ofDual-PortSRAMwitheachother.
One caution that should be noted when using semaphores is that
The blocks do not have to be any particular size and can even be
semaphoresalonedonotguaranteethataccesstoaresourceissecure. variable, depending upon the complexity of the software using the
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
ormisinterpreted, a software errorcaneasilyhappen.
PortSRAMorothersharedresourcesintoeightparts.Semaphorescan
Initializationofthesemaphoresisnotautomaticandmustbehandled evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest given a common meaning as was shown in the example above.
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth Semaphores are a useful form of arbitration in systems like disk
sidesshouldhaveaonewrittenintothematinitializationfrombothsides interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
to assure that they will be free when needed.
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
been performed, both processors can access their assigned RAM
segmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
mayberesponsibleforbuildingandupdatingadatastructure.Theother
processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
processorreadsanincompletedatastructure,amajorerrorconditionmay
exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
itandthenisabletogoinandupdatethedatastructure.Whentheupdate
is completed, the data structure block is released. This allows the
interpretingprocessortocomebackandreadthecompletedatastructure,
therebyguaranteeingaconsistentdatastructure.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resource markers for the IDT70V35/34 (IDT70V25/24)’s Dual-Port
SRAM.Saythe8Kx18SRAMwastobedividedintotwo4Kx18blocks
whichweretobededicatedatanyonetimetoservicingeithertheleftor
rightport.Semaphore0couldbeusedtoindicatethesidewhichwould
controlthelowersectionofmemory,andSemaphore1couldbedefined
astheindicatorfortheuppersectionofmemory.
Totakearesource,inthisexamplethelower4KofDual-PortSRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
backratherthana one), the leftprocessorwouldassume controlofthe
lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the
softwarecouldchoosetotryandgaincontrolofthesecond4Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5624 drw 20
Figure 4. IDT70V35/34 (IDT70V25/24) Semaphore Logic
6.2442
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
OrderingInformation(1)
Industrial and Commercial Temperature Ranges
A
IDT XXXXX
A
999
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Step
Blank Commercial (0°C to +70°C)
I(1)
Industrial (-40°C to +85°C)
PF
G
J
100-pin TQFP (PN100-1) 70V35/34/25/24
84-Pin PGA (G84-3)
70V25/24
70V25/24
84-Pin PLCC (J84-1)
,
15
20
25
25
35
55
Commercial Only - 70V35/34/25/24
Commercial & Industrial - 70V35/34/25/24
Commercial Only - 70V35/34
,
Speed in Nanoseconds
Commercial & Industrial - 70V25/24
Commercial Only - 70V25/24
Commercial Only - 70V25/24
S
L
Standard Power
Low Power
Blank
T
No stepping designation
Current Stepping
144K (8K x 18-Bit) 3.3V Dual-Port RAM
72K (4K x 18-Bit) 3.3V Dual-Port RAM
128K (8K x 16-Bit) 3.3V Dual-Port RAM
64K (4K x 16-Bit) 3.3V Dual-Port RAM
70V35
70V34
70V25
70V24
5624 drw 21a
NOTES:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
DatasheetDocumentHistory
06/08/00:
08/09/01:
InitialPublicOffering
Page 1 Corrected I/O numbering
Page 5-7, 10&12 RemovedIndustrialtemperature range offeringfor25ns fromDC&ACElectricalCharacteristics
Page17 RemovedIndustrialtemperaturerangeofferingfor25nsspeedfromtheorderinginformation
AddedIndustrialtemperatureofferingfootnote
07/02/02:
06/22/04:
Page 2 Addeddate revisionforpinconfiguration
Added 70V34 to datasheet (4K x 18)
Consolidated70V25/24datasheets (8/4Kx16)into70V35/34(8/4Kx18)datasheet
RemovedPreliminarystatusfromdatasheet
Page 2 & 3 Changed naming convention from VCC to VDD and from GND to VSS for PN100 packages
Page7 UpdatedConditionsinCapacitancetable
Page7 AddedJunctionTemperaturetoAbsoluteMaximumRatingstable
Page 9, 11, 13, 17 &, 19 Added DC and AC Electrical Characteristics tables for 70V25/24 data
Page21& 22 ChangedInterruptflagtable,footnotes andInterrupts texttoreflect70V25/24data
Page 1 & 15 Replaced old logo with new TM logo
10/28/04:
Page25 Addedsteppingindicatortoorderinginformation
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
25
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