IDT70V261S35PF9_技术文档

HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

IDT70V261S/L

bus compatibility

ꢀeatures

◆

IDT70V261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP, Thin Quad Plastic Flatpack

Industrial temperature range (-40°C to +85°C) is available

for selected speed

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:25/35/55ns (max.)

– Industrial:25ns (max.)

Low-power operation

◆

– IDT70V261S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V261L

◆

Active: 300mW (typ.)

Standby: 660µW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

ꢀunctional Block Diagram

R/

UBL

L

W

R/

R

UBR

W

LBL

CEL

OEL

LB_R

CER

OER

I/O8L-I/O15L

I/O8R-I/O15R

I/O0R-I/O7R

I/O

Control

I/O

Control

I/O0L-I/O7L

(1,2)

BUSYL

BUSYR

A13R

A0R

A13L

A0L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

14

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CER

OER

R/W

R

CEL

OEL

R/

W

L

SEMR

INTR

SEM_L

INTL

(2)

M/

S

3040 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

DECEMBER 2001

1

DSC-3040/8

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Description

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

a very low standby power mode.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typically operate on only 300mW of power.

TheIDT70V261isahigh-speed16Kx16Dual-PortStaticRAM.The

IDT70V261isdesignedtobeusedasastand-alone256K-bitDual-Port

RAMorasacombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-

more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM

approach in 32-bit or wider memory system applications results in full-

speed,error-freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

The IDT70V261 is packaged in a 100-pin Thin Quad Flatpack.

Pin Configurations^(1,2,3)

12/11/01

Index

86

76

85 84 83 82 81 80 79 78 77

100 99 98 97 96 95 94 93 92 91 90 89 88 87

1

2

3

4

5

6

7

8

9

N/C

A6L

75

N/C

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

N/C

5L

A

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

N/C

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT70V261PF

(4)

PN100-1

100-Pin TQFP

(5)

Top View

BUSYR

INTR

A0R

A1R

2R

A

3R

A

4R

A

5R

N/C

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

,

3040 drw 02

NOTES:

Pin Names

Left Port

1. All V^CCpins must be connected to power supply.

2. All GND pins must be connected to ground supply.

Right Port

Names

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

CE^L

CE^R

W^R

Chip Enable

W^L

R/

Read/Write Enable

Output Enable

Address

OE^L

0L

OE^R

13L

15L

0R

A

13R

- A

A

- A

0L

0R

15R

I/O - I/O

Data Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Busy Flag

SEM^L

SEM^R

L

UB

R

UB

LB^L

LB^R

BUSY^R

S

BUSY^L

M/

Master or Slave Select

Power

CC

V

GND

Ground

3040 tbl 01

6.242

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

X

L

I/O^8-15

High-Z

DATA^IN

High-Z

DATA^IN

I/O^0-7

High-Z

DATA^IN

High-Z

Mode

Deselected: Power-Down

CE

H

X

L

OE

X

L

UB

X

H

L

LB

X

H

L

SEM

H

Both Bytes Deselected: Power-Down

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

H

L

H

L

H

L

H

L

H

X

L

H

L

H

DATA^OUT

High-Z

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

OUT

DATA

L

H

L

H

L

H

DATA^OUT

High-Z

DATA^OUT

High-Z

X

H

X

Outputs Disabled

3040 tbl 02

NOTE:

1. A^0L— A13L ≠ A0R — A13R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs⁽¹⁾

Outputs

R/W

H

↑

I/O^8-15

I/O^0-7

Mode

Read Data in Semaphore Flag

Write I/O⁰into Semaphore Flag

Not Allowed

CE

H

X

H

X

L

OE

L

UB

X

H

X

H

L

LB

X

H

X

H

X

L

SEM

L

DATA^OUT

DATA^IN

DATA^OUT

DATA^IN

L

X

L

DATA^IN

↑

____

X

L

____

L

X

L

Not Allowed

3040 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

3

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings⁽¹⁾

Maximum Operating Temperature

andSupplyVoltage⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Unit

Grade

GND

Vcc

(2)

Ambient Temperature

0^OC to +70^OC

V^TERM

Terminal Voltage

with Respect

to GND

-0.5 to +4.6

V

+

Commercial

Industrial

0V

3.3V 0.3

T^BIAS

T^STG

I^OUT

-40^OC to +85^OC

3.3V 0.3

Te mp e rature

Under Bias

-55 to +125

-65 to +150

50

^oC

+

3040 tbl 05

NOTES:

Storage

Te mp e rature

1. This is the parameter T^A. This is the "instant on" case temperature.

DC Output

Current

mA

3040 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating

Conditions⁽²⁾

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

2. V^TERMmust not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.

VCC

Supply Voltage

3.0

3.3

3.6

GND Ground

0

V

VIH

VIL

Input High Voltage

Input Low Voltage

2.2

VCC+0.3⁽²⁾

0.8

V

____

-0.3⁽¹⁾

V

____

Capacitance⁽¹⁾(TA = +25°C, f = 1.0MHz)

3040 tbl 06

Conditions^{(2 )}

Max. Unit

NOTES:

Symbol

Parameter

Input Capacitance

Output Capacitance

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 0.3V.

C^IN

V^IN= 3dV

9

pF

C^OUT

V^OUT= 3dV

10

pF

3040 tbl 07

NOTES:

1. This parameter is determined by device characterization but is not production

tested. TQFP package only.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3v)

70V261S

70V261L

Symbol

|I^LI|

Parameter

Test Conditions

Min.

Max.

10

Min.

Max.

5

Unit

µA

V

(1)

___

Input Leakage Current

V^CC= 3.6V, V^IN= 0V to V^CC

___

|I^LO|

Output Leakage Current

Output Low Voltage

Output High Voltage

IH OUT

CC

10

5

CE = V , V = 0V to V

V^OL

I^OL= +4mA

0.4

___

V^OH

I^OH= -4mA

2.4

V

3040 tbl 08

NOTE:

1. At V^CC= 2.0V, input leakages are undefined.

6.442

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VCC = 3.3V ± 0.3V)

70V261X25

Com'l

70V261X35

Com'l Only

70V261X55

Com'l Only

& Ind

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

I^CC

Dynamic Operating

Current

(Both Ports Active)

S

L

100

170

140

90

140

120

90

140

120

mA

CE = V^IL, Outputs Disabled

SEM = V^IH

(3)

f = f^MAX

____

IND

S

L

100

200

185

mA

I^SB1

I^SB2

I^SB3

I^SB4

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

IND

S

L

14

12

30

24

12

10

30

24

12

10

30

24

CE^R= CE^L= V^IH

SEM^R= SEM^L= V^IH

(3)

f = f^MAX

____

S

L

14

12

60

50

(5)

Standby Current

(One Port - TTL

Level Inputs)

COM'L

IND

S

L

50

95

85

45

87

75

45

87

75

CE^"A"= V^ILand CE^"B"= V^IH

Active Port Outputs Disabled,

(3)

f=f^MAX

____

S

L

50

130

105

SEM^R= SEM^L= V^IH

Full Standby Current

(Both Ports -

CMOS Level Inputs)

Both Ports CE^Land

CE^R> V^CC- 0.2V,

COM'L

IND

S

L

1.0

0.2

6

3

1.0

0.2

6

3

1.0

0.2

6

3

V^IN> V^CC- 0.2V or

____

V^IN< 0.2V, f = 0⁽⁴⁾

S

L

1.0

0.2

6

3

SEM^R= SEM^L> V^CC- 0.2V

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

IND

S

L

60

90

80

55

85

74

55

85

74

CE^"A"< 0.2V and

(5)

CE^"B"> V^CC- 0.2V

SEM^R= SEM^L> V^CC- 0.2V

V^IN> V^CC- 0.2V or V^IN< 0.2V

Active Port Outputs Disabled,

____

S

L

60

125

90

(3)

f = f^MAX

3040 tbl 09

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. V^CC= 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of

GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

5

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

3.3V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

1.5V

590Ω

Ω

590

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

1.5V

30pF

5pF*

435Ω

435

Ω

Figures 1 and 2

3040 tbl 10

3040 drw 04

3040 drw 03

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

Timing of Power-Up Power-Down

CE

t^PU

t^PD

ICC

ISB

,

3040 drw 05

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

70V261X25

Com'l

& Ind

70V261X55

Com'l Only

70V261X35

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

tRC

Read Cycle Time

25

35

55

ns

____

tAA

Address Access Time

25

35

55

Chip Enable Access Time⁽³⁾

____

tACE

tABE

tAOE

tOH

Byte Enable Access Time⁽³⁾

Output Enable Access Time

15

20

30

____

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

tLZ

3

Output High-Z Time^(1,2)

15

20

25

____

tHZ

tPU

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

tPD

25

35

50

____

tSOP

tSAA

15

____

35

45

65

ns

3040 tbl 11

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

6.642

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE

(4)

tAOE

OE

(4)

tABE

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

3040 drw 0

t_BDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

70V261X25

70V261X35

Com'l Only

70V261X55

Com'l Only

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

Write Cycle Time

25

20

0

35

30

0

55

45

0

ns

WC

t

EW

AW

AS

Chip Enable to End-of-Write⁽³⁾

Addres s Valid to End-of-Write

Addres s Se t-up Time ⁽³⁾

Write Pulse Width

t

20

0

25

0

40

0

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

20

30

____

t

15

20

25

____

t

0

Write Enable to Output in High-Z^(1,2)

Output Activ e fro m E nd-o f-Write ^{(1, 2,4)}

SEM Flag Write to Read Time

15

20

25

____

t

____

t

0

5

0

5

0

5

____

t

ns

SEM Flag Conte ntion Window

3040 tbl 12

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual t^DHwill always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

7

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

tWP

tAS

tWR

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

3040 drw 07

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing^(1,5)

tWC

ADDRESS

t_AW

CE or SEM⁽⁹⁾

(3)

(6)

(2)

tAS

tWR

t_EW

(9)

or

UB LB

R/

W

tDW

tDH

DATAIN

3040 drw 08

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the

bus for the required t^DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

6.842

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

OH

t

SAA

t

A0-A2

VALID ADDRESS

tACE

tWR

tAW

tEW

SEM

tSOP

tDW

DATAIN

VALID

DATAOUT

VALID⁽²⁾

0

I/O

tAS

tWP

DH

t

R/W

tSWRD

tAOE

OE

Write Cycle

Read Cycle

3040 drw 09

NOTES:

1. CE = V^IHor UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. “DATA^OUTVALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

(2)

SIDE

"A"

R/W"A"

SEM"A"

SPS

t

A0"B"-A2"B"

MATCH

(2)

SIDE

"B"

R/W"B"

"B"

SEM

3040 drw 10

NOTES:

1. D^OR= DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W^"A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If t^SPSis not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

9

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁶⁾

70V261X25

Com'l

70V261X35

Com'l Only

70V261X55

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = VIH)

____

tBAA

tBDA

tBAC

tBDC

tAPS

tBDD

tWH

25

35

45

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Match

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

25

35

45

____

5

____

BUSY Disable to Valid Data⁽³⁾

35

40

50

(5)

____

Write Hold After BUSY

20

25

BUSY INPUT TIMING (M/S = VIL)

____

BUSY Input to Write⁽⁴⁾

tWB

0

ns

(5)

tWH

Write Hold After BUSY

20

25

PORT-TO-PORT DELAY TIMING

Write Pulse to Data Delay⁽¹⁾

Write Data Valid to Read Data Delay⁽¹⁾

55

50

65

60

85

80

ns

____

tWDD

tDDD

ns

2945 tbl 13

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. "X" in part number indicates power rating (S or L).

Timing Waveform of write with Port-to-Port Read and BUSY^(2,4,5)

t_WC

MATCH

ADDR_"A"

t_WP

R/

W

"A"

t_DW

t_DH

VALID

DATA_{IN "A"}

(1)

t_APS

MATCH

ADDR_"B"

t_BAA

t_BDA

t_BDD

BUSY"B"

t_WDD

VALID

DATA_{OUT "B"}

(3)

t_DDD

NOTES:

3040 drw 11

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. If M/S = V^IL(SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

61.402

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

tWP

R/W"A"

WB

t

BUSY"B"

(1)

WH

t

R/W"B"

(2)

3040 drw 12

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾

ADDR_"A"

ADDRESSES MATCH

and _"B"

CE"A"

(2)

t_APS

CE"B"

t_BAC

t_BDC

BUSY"B"

3040 drw 13

Waveform of BUSY Arbitration Cycle Controlled by

Address Match Timing⁽¹⁾

ADDR"A"

ADDR_"B"

ADDRESS "N"

(2)

t_APS

MATCHING ADDRESS "N"

t_BAA

t_BDA

"B"

BUSY

3040 drw 14

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.

11

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

70V261X25

Com'l

& Ind

70V261X35

Com'l Only

70V261X55

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

AS

t

Address Set-up Time

0

ns

t

WR

Write Re cove ry Time

Interrupt Set Time

0

____

t

IN S

25

30

35

40

45

____

t

IN R

Inte rrupt Reset Time

ns

3040 tbl 14

NOTES:

1. 'X' in part number indicates power rating (S or L).

Waveform of Interrupt Timing⁽¹⁾

t_WC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR_"A"

(3)

(4)

t_AS

t_WR

CE"A"

R/

W"A"

(3)

t_INS

INT"B"

3040 drw 15

t_RC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR_"B"

(3)

t_AS

"B"

CE

OE"B"

(3)

t_INR

INT"B"

3040 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal is asserted last.

4. Timing depends on which enable signal is de-asserted first.

61.422

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Truth Table III Interrupt ꢀlag⁽¹⁾

Left Port

Right Port

R/W^L

L

A13L-A0L

3FFF

X

R/W^R

X

A13R-A0R

X

Function

Set Right INT^RFlag

Reset Right INT^RFlag

Set Left _INTLFlag

CE^L

L

OE^L

X

INT^L

X

CE^R

X

OE^R

X

INT^R

(2)

L

(3)

X

L

3FFF

3FFE

X

H

(3)

X

L

X

(2)

X

L

3FFE

H

X

Reset Left INT^LFlag

3040 tbl 15

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

Truth Table IV

Address BUSY Arbitration

Inputs

Outputs

A^0L-A^13L

A^0R-A^13R

(1)

Function

Normal

CE^L

X

CE^R

X

BUSY^L

H

BUSY^R

NO MATCH

MATCH

H

X

H

X

H

MATCH

H

(3)

L

MATCH

(2)

Write Inhibit

3040 tbl 16

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V261 are push

pull, not open drain outputs. On slaves the BUSY^Xinput internally inhibits writes.

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. V^IHif the inputs to the opposite port became stable after the address and

enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D¹⁵Left

D⁰- D¹⁵Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

3040 tbl 17

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V261.

2. There are eight semaphore flags written to via I/O⁰and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

3. CE = V^IH, SEM = VIL to access the semaphore. Refer to the Semaphore Read/Write Control Truth Table.

13

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

write operations can be prevented to a port by tying the BUSY pin for

that port LOW.

The BUSY outputs on the IDT70V261 RAM in master mode, are

push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

ꢀunctional Description

The IDT70V261 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70V261 has an automatic power down

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted.

Width Expansion with Busy Logic

Master/Slave Arrays

Interrupts

When expanding an IDT70V261 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSYindication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70V261 SRAM the BUSY pin is an output if the part is used as a

master (M/S pin = VIH), and the BUSY pin is an input if the part used

as a slave (M/S pin = VIL) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

splitdecisioncouldresultwithonemasterindicatingBUSYononeside

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for part of

the other word.

If the user chooses the interrupt function, a memory location (mail

boxormessagecenter)is assignedtoeachport. Theleftportinterrupt

flag (INT^L) is asserted when the right port writes to memory location

3FFE (HEX), where a write is defined as CE^R= R/WR = VIL per Truth

Table III. The left port clears the interrupt through access of address

location 3FFE when CE^L= OEL = VIL, R/W is a "don't care". Likewise,

the right port interrupt flag (INTR) is asserted when the left port writes

to memory location 3FFF (HEX) and to clear the interrupt flag (INTR),

the right port must read the memory location 3FFF. The message (8

bits) at 3FFE or 3FFF is user-defined since it is an addressable SRAM

location. If the interrupt function is not used, address locations 3FFE

and3FFFarenotusedasmailboxes,butaspartoftherandomaccess

memory. Refer to Truth Table III for the interrupt operation.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actualwrite pulse canbe initiatedwitheitherthe R/W signalorthe byte

enables. Failure to observe this timing can result in a glitched internal

write inhibit signal and corrupted data in the slave.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAMhave accessedthe same locationatthe same time. Italsoallows

one of the two accesses to proceed and signals the other side that the

RAMis “busy”. The BUSYpincanthenbe usedtostallthe access until

the operation on the other side is completed. If a write operation has

been attemptedfromthe side thatreceives aBUSYindication, the write

signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs

together and use any busy indication as an interrupt source to flag an

illegal or illogical operation. If the write inhibit function of BUSY logic

is not desirable, the BUSY logic can be disabled by placing the part in

slave mode with the M/S pin. Once in slave mode the BUSY pin

operates solely as a write inhibit input pin. Normal operation can be

programmed by tying the BUSY pins HIGH. If desired, unintended

Semaphores

TheIDT70V261isafastDual-Port16Kx16CMOSStaticRAMwith

anadditional8addresslocationsdedicatedtobinarysemaphoreflags.

These flags allow either processor on the left or right side of the Dual-

Port SRAM to claim a privilege over the other processor for functions

defined by the system designer’s software. As an example, the

semaphore can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port SRAM or any other shared

resource.

The Dual-Port SRAM features a fast access time, and both ports

are completelyindependentofeachother. This means thatthe activity

on the left port in no way slows the access time of the right port. Both

ports are identical in function to standard CMOS Static RAM and can

be read from, or written to, at the same time with the only possible

conflict arising from the simultaneous writing of, or a simultaneous

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic power-down

feature controlled by CE, the Dual-Port SRAM enable, and SEM, the

semaphoreenable.TheCEandSEM pinscontrolon-chippowerdown

circuitrythatpermits the respective porttogointostandbymode when

notselected.ThisistheconditionwhichisshowninTruthTableIwhere

CE and SEM are both HIGH.

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY_L

BUSY_R

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY_R

BUSY_L

BUSY_R

BUSY_L

,

3040 drw 17

Figure 3. Busy and chip enable routing for both width and depth expansion

with IDT70V261 RAMs.

61.442

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Systems which can best use the IDT70V261 contain multiple ough discussion on the use of this feature follows shortly.) A zero

processors or controllers and are typically very high-speed systems written into the same location from the other side will be stored in the

which are software controlled or software intensive. These systems semaphore request latch for that side until the semaphore is freed by

can benefit from a performance increase offered by the IDT70V261's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

L PORT

R PORT

Softwarehandshakingbetweenprocessors offers themaximumin

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V261 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

3040 drw 18

Figure 4. IDT70V261 Semaphore Logic

How the Semaphore ꢀlags Work

The semaphore logic is a set of eight latches which are indepen-

the first side.

Whena semaphore flagis read, its value is spreadintoalldata bits

dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag, so that a flag that is a one reads as a one in all data bits and a flag

or token, from one port to the other to indicate that a shared resource containinga zeroreads as allzeros. The readvalue is latchedintoone

is in use. The semaphores provide a hardware assist for a use side’s output register when that side's semaphore select (SEM) and

assignmentmethodcalled“TokenPassingAllocation.”Inthis method, output enable (OE) signals go active. This serves to disallow the

thestateofasemaphorelatchisusedasatokenindicatingthatshared semaphore from changing state in the middle of a read cycle due to a

resource is in use. If the left processor wants to use this resource, it write cycle from the other side. Because of this latch, a repeated read

requests the token by setting the latch. This processor then verifies its of a semaphore in a test loop must cause either signal (SEM or OE) to

success in setting the latch by reading it. If it was successful, it go inactive or the output will never change.

proceeds to assume control over the shared resource. If it was not

A sequence WRITE/READ must be used by the semaphore in

successful in setting the latch, it determines that the right side order to guarantee that no system level contention will occur. A

processor has set the latch first, has the token and is using the shared processor requests access to shared resources by attempting to write

resource. The left processor can then either repeatedly request that a zero into a semaphore location. If the semaphore is already in use,

semaphore’s status or remove its request for that semaphore to the semaphore request latch will contain a zero, yet the semaphore

perform another task and occasionally attempt again to gain control of flag will appear as one, a fact which the processor will verify by the

the token via the set and test sequence. Once the right side has subsequent read (see Truth Table V). As an example, assume a

relinquished the token, the left side should succeed in gaining control. processorwritesazerototheleftportatafreesemaphorelocation.On

The semaphore flags are active LOW. A token is requested by asubsequentread,theprocessorwillverifythatithas writtensuccess-

writing a zero into a semaphore latch and is released when the same fully to that location and will assume control over the resource in

side writes a one to that latch.

question. Meanwhile, if a processor on the right side attempts to write

The eight semaphore flags reside within the IDT70V261 in a a zero to the same semaphore flag it will fail, as will be verified by the

separate memory space from the Dual-Port SRAM. This address factthataonewillbereadfromthatsemaphoreontherightsideduring

space is accessed by placing a LOW input on the SEM pin (which acts subsequent read. Had a sequence of READ/WRITE been used

as a chip select for the semaphore flags) and using the other control instead, system contention problems could have occurred during the

pins (Address, OE, and R/W) as they would be used in accessing a gap between the read and write cycles.

standard Static RAM. Each of the flags has a unique address which

It is important to note that a failed semaphore request must be

can be accessed by either side through address pins A0 – A2. When followed by either repeated reads or by writing a one into the same

accessing the semaphores, none of the other address pins has any

effect.

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag low and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

secondside’s flagwillnowstayLOWuntilits semaphore requestlatch

is written to a one. From this it is easy to understand that, if a

semaphore is requested and the processor which requested it no

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel

is written into an unused semaphore location, that flag will be set to a

zero on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero.

When a one is written into the same location from the same side, the

flag will be set to a one for both sides (unless a semaphore request

fromtheothersideispending)andthencanbewrittentobybothsides.

The fact that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what makes

semaphore flags useful in interprocessor communications. (A thor-

15

6.42

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

longer needs the resource, the entire system can hang up until a one

is written into that semaphore request latch.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

The critical case of semaphore timing is when both sides request Semaphore 1 was still occupied by the right side, the left side could

a single tokenbyattemptingtowrite a zerointoitatthe same time. The undo its semaphore request and perform other tasks until it was able

semaphore logic is specially designed to resolve this problem. If to write, then read a zero into Semaphore 1. If the right processor

simultaneous requests are made, the logic guarantees that only one performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe

side receives the token. If one side is earlier than the other in making two processors to swap 8K blocks of Dual-Port RAM with each other.

the request, the first side to make the request will receive the token. If

bothrequests arriveatthesametime,theassignmentwillbearbitrarily variable, depending upon the complexity of the software using the

made to one port or the other. semaphore flags. All eight semaphores could be used to divide the

The blocks do not have to be any particular size and can even be

One caution that should be noted when using semaphores is that Dual-Port RAM or other shared resources into eight parts. Sema-

semaphores alone do not guarantee that access to a resource is phores can even be assigned different meanings on different sides

secure. As with any powerful programming technique, if semaphores rather than being given a common meaning as was shown in the

are misused or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be

example above.

Semaphores are a useful form of arbitration in systems like disk

handled via the initialization program at power-up. Since any sema- interfaces where the CPU must be locked out of a section of memory

phore request flag which contains a zero must be reset to a one, all during a transfer and the I/O device cannot tolerate any wait states.

semaphores on both sides should have a one written into them at With the use of semaphores, once the two devices has determined

initialization from both sides to assure that they will be free when which memory area was “off-limits” to the CPU, both the CPU and the

needed.

I/O devices could access their assigned portions of memory continu-

ously without any wait states.

Semaphores are also useful in applications where no memory

“WAIT” state is available on one or both sides. Once a semaphore

handshake has been performed, both processors can access their

assigned RAM segments at full speed.

UsingSemaphoresSomeExamples

Perhaps the simplest application of semaphores is their applica-

tionas resourcemarkers fortheIDT70V261’s Dual-PortRAM.Saythe

16K x 16 RAM was to be divided into two 8K x 16 blocks which were

to be dedicated at any one time to servicing either the left or right port.

Semaphore 0 could be used to indicate the side which would control

thelowersectionofmemory,andSemaphore1couldbedefinedasthe

indicator for the upper section of memory.

Totakearesource,inthis examplethelower8KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore 0. If this task were successfully completed (a zero was

read back rather than a one), the left processor would assume control

of the lower 8K. Meanwhile the right processor was attempting to gain

controlofthe resourceaftertheleftprocessor,itwouldreadbackaone

in response to the zero it had attempted to write into Semaphore 0. At

this point, the software could choose to try and gain control of the

second 8K section by writing, then reading a zero into Semaphore 1.

If it succeeded in gaining control, it would lock out the left side.

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

case, block arbitration is very important. For this application one

processor may be responsible for building and updating a data

structure. The other processor then reads and interprets that data

structure. If the interpreting processor reads an incomplete data

structure, a major error condition may exist. Therefore, some sort of

arbitration must be used between the two different processors. The

building processor arbitrates for the block, locks it and then is able to

goinandupdatethedatastructure.Whentheupdateiscompleted,the

data structure blockis released. This allows the interpretingprocessor

to come back and read the complete data structure, thereby guaran-

teeing a consistent data structure.

61.462

IDT70V261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Ordering Information

IDT XXXXX

A

999

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

PF

100-pin TQFP (PN100-1)

Commercial & Industrial

Commercial Only

25

35

55

Speed in nanoseconds

S

L

Standard Power

Low Power

70V261 256K (16K x 16) 3.3V Dual-Port RAM w/ Interrupt

3040 drw 19

NOTE:

1. For other speeds, packages and powers contact your sales office.

Datasheet Document History

3/25/99:

Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 Addedadditionalnotestopinconfigurations

Changeddrawingformat

Page 1 Changed660mWto660µW

Replaced IDT logo

6/10/99:

8/30/99:

11/12/99:

6/7/00:

Page 4 Increatedstoragetemperatureparameter

ClarifiedTAParameter

Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Changed±200mVto0mVinnotes

12/01/01:

Page 2 Addeddaterevisiontopinconfigurations

Page 5 AddedI-tempvaluesfor25nstoDCElectricalCharacteristics

Pages 4, 5, 6, 7, 10&12 RemovedI-tempfootnotes fromalltables

Page 17 AddedI-tempofferinginorderinginformation

Page 1 & 17 Replaced TM logo with ® logo

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

17

6.42


型号：	IDT70V261S35PF9
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 16KX16, 35ns, CMOS, PQFP100, PLASTIC, TQFP-100 静态存储器内存集成电路
文件：	总17页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT70V261S35PF9 [IDT]

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