IDT70V26L35J_技术文档

IDT70V26S/L

HIGH-SPEED 3.3V

16K x 16 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

IDT70V26 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆

– Commercial: 25/35/55ns (max.)

Low-power operation

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 84-pin PGA and PLCC

◆

– IDT70V26S

Active: 300mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V26L

Active: 300mW (typ.)

Standby: 660µW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

R/WL

UBL

R/WR

UBR

LBL

CEL

OEL

LBR

CER

OER

I/O8L-I/O15L

I/O0L-I/O7L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0R-I/O7R

(1,2)

BUSYL

(1,2)

BUSYR

A13L

A13R

Address

MEMORY

ARRAY

Address

Decoder

A0L

A0R

14

ARBITRATION

SEMAPHORE

LOGIC

CEL

CER

SEMR

SEML

M/

1

S

2945 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs are non-tri-stated push-pull.

JUNE 2000

DSC 2945/13

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70V26 is a high-speed 16K x 16 Dual-Port Static RAM. address, and I/O pins that permit independent, asynchronous access

The IDT70V26is designedtobe usedas a stand-alone 256K-bitDual- for reads or writes to any location in memory. An automatic power

PortRAMorasacombinationMASTER/SLAVEDual-PortRAMfor32- down feature controlled by CE permits the on-chip circuitry of each

bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port port to enter a very low standby power mode.

RAM approach in 32-bit or wider memory system applications results

in full-speed, error-free operation without the need for additional devices typically operate on only 300mW of power.

discrete logic. The IDT70V26 is packaged in a ceramic 84-pin PGA and

This device provides two independent ports with separate control, 84-Pin PLCC.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

Pin Configurations^(1,2,3)

INDEX

11 10 9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

74

I/O8L

I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

A8L

7L

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A

73

72

71

70

69

68

67

A6L

A5L

A4L

A3L

A2L

A1L

IDT70V26J

J84-1⁽⁴⁾

A0L

66

65

64

63

62

61

60

59

58

57

56

55

54

BUSYL

GND

M/S

84-Pin PLCC

Top View⁽⁵⁾

GND

I/O0R

I/O1R

I/O2R

VCC

BUSYR

A0R

A1R

A2R

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

A

3R

A4R

A5R

A6R

A7R

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

2945 drw 02

NOTES:

1. All V^CCpins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

2

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

63

61

60

58

55

54

51

48

46

A12L

44

45

42

11

10

09

08

07

06

05

04

03

02

01

A_8L

A_11L

I/O_7L

I/O_5L

I/O_4L

I/O_2L

I/O_0L

OEL

SEML

LBL

66

I/O10L

64

62

59

56

49

50

47

43

40

39

37

A_6L

A_9L

A_10L

I/O8L

I/O6L

I/O3L

I/O1L

A_13L

UBL

CEL

67

65

57

53

52

41

A_7L

R/

WL

GND

V_CC

A_5L

I/O_11L

I/O_9L

69

I/O13L

72

68

38

A_3L

A_4L

I/O_12L

71

73

VCC

74

33

35

34

A0L

36

A_1L

I/O_15L

BUSYL

I/O_14L

IDT70V26G

G84-3

(4)

75

70

32

31

GND

A_2L

I/O0R

GND

M/

S

GND

84-Pin PGA

Top View

(5)

76

77

78

28

29

30

V_CC

I/O_1R

A_1R

A_0R

I/O_2R

BUSYR

79

80

26

A3R

27

A_2R

I/O3R

I/O_4R

81

83

7

11

12

23

25

A_4R

A_6R

SEMR

I/O_5R

I/O_7R

GND

82

1

3

2

5

8

10

14

17

20

22

24

A_9R

A_7R

A_5R

A_12R

I/O_6R

I/O_9RI/O_10RI/O_13RI/O_15RR/

WR

UBR

84

4

6

9

15

13

16

18

19

21

I/O_8RI/O_11RI/O_12RI/O_14R

OER

LBR

CER

A_11R

A_10R

A_13R

A_8R

A

B

C

D

E

F

G

H

J

K

L

2945 drw 03

Index

NOTES:

1. All V^CCpins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Names

Left Port

Right Port

Names

Chip Enable

CE^L

CE^R

W^L

W^R

R/

Read/Write Enable

Output Enable

Address

OE^L

0L

OE^R

13L

0R

13R

- A

A

- A

A

0L

15L

0R

15R

I/O - I/O

SEM^L

UB^L

I/O - I/O

SEM^R

UB^R

Data Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Busy Flag

LB^L

LB^R

BUSY^L

BUSY^R

S

M/

Master or Slave Select

Power

CC

V

GND

Ground

2945 tbl 01

6.42

3

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

X

L

I/O^8-15

High-Z

DATA^IN

High-Z

DATA^IN

I/O^0-7

High-Z

DATA^IN

High-Z

Mode

Deselected: Power-Down

CE

H

X

L

OE

X

L

UB

X

H

L

LB

X

H

L

SEM

H

Both Bytes Deselected: Power-Down

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

H

L

H

L

H

L

H

L

H

X

L

H

L

H

DATA^OUT

High-Z

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

OUT

DATA

L

H

L

H

L

H

DATA^OUT

High-Z

DATA^OUT

High-Z

X

H

X

Outputs Disabled

2945 tbl 02

NOTE:

1. A0L — A13L≠ A0R — A13R

Truth Table II Semaphore Read/Write Control⁽¹⁾

Inputs⁽¹⁾

Outputs

R/W

H

↑

I/O^8-15

I/O^0-7

Mode

Read Data in Semaphore Flag

Write I/O⁰into Semaphore Flag

Not Allowed

CE

H

X

H

X

L

OE

L

UB

X

H

X

H

L

LB

X

H

X

H

X

L

SEM

L

DATA^OUT

DATA^IN

DATA^OUT

DATA^IN

L

X

L

DATA^IN

↑

____

X

L

____

L

X

L

Not Allowed

2945 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

6.42

4

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings⁽¹⁾

Maximum Operating Temperature

and Supply Voltage^(1,2)

Symbol

Rating

Commercial

& Industrial

Unit

Grade

GND

Vcc

(2)

Ambient Temperature

0^OC to +70^OC

V^TERM

Terminal Voltage

with Respect

to GND

-0.5 to +4.6

V

+

3.3V 0.3

Commercial

Industrial

0V

-40^OC to +85^OC

3.3V 0.3

Temperature

Under Bias

-55 to +125

-65 to +150

50

^oC

+

T^BIAS

T^STG

I^OUT

2945 tbl 05

NOTES:

Storage

Temperature

1. This is the parameter T^A. This is the "instant on" case temperature.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

DC Output

Current

mA

2945 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating

Conditions⁽²⁾

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

2. V^TERMmust not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.

V^CC

Supply Voltage

3.0

3.3

3.6

GND Ground

0

V^CC+ 0.3⁽²⁾

0.8

V

____

V^IH

V^IL

Input High Voltage

Input Low Voltage

2.0

V

-0.3⁽¹⁾

V

____

Capacitance⁽¹⁾(TA = +25°C, f = 1.0MHz)

2945 tbl 06

NOTES:

Symbol

C^IN

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

Max. Unit

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 0.3V.

V^IN= 3dV

9

pF

C^OUT

V^OUT= 3dV

10

pF

2945 tbl 07

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

70V26S

70V26L

Symbol

|I^LI|

Parameter

Test Conditions

Min.

Max.

10

Min.

Max.

5

Unit

µA

V

(1)

___

Input Leakage Current

V^CC= 3.6V, V^IN= 0V to V^CC

___

|I^LO|

Output Leakage Current

Output Low Voltage

Output High Voltage

IH OUT

CC

10

5

CE = V , V = 0V to V

V^OL

I^OL= +4mA

0.4

___

V^OH

I^OH= -4mA

2.4

V

2945 tbl 08

NOTE:

1. At V^CC< 2.0V, input leakages are undefined.

6.42

5

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6)(VCC = 3.3V ± 0.3V)

70V26X25

Com'l Only

70V26X35

Com'l Only

70V26X55

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating

Current

(Both Ports Active)

S

L

100

170

140

90

140

120

90

140

120

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

____

IND

S

L

mA

ISB1

ISB2

ISB3

ISB4

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

IND

S

L

14

12

30

24

12

10

30

24

12

10

30

24

CE^R= CE^L= VIH

SEM^R= SEM^L= VIH

(3)

f = fMAX

____

S

L

(5)

Standby Current

(One Port - TTL

Level Inputs)

COM'L

IND

S

L

50

95

85

45

87

75

45

87

75

CE^"A"= VIL and CE^"B"= VIH

Active Port Outputs Disabled,

(3)

f=fMAX

____

S

L

SEM^R= SEM^L= VIH

Full Standby Current

(Both Ports -

CMOS Level Inputs)

Both Ports CE^Land

CE^R> VCC - 0.2V,

COM'L

IND

S

L

1.0

0.2

6

3

1.0

0.2

6

3

1.0

0.2

6

3

VIN > VCC - 0.2V or

____

VIN < 0.2V, f = 0⁽⁴⁾

S

L

SEM^R= SEM^L> VCC - 0.2V

Full Standby Current

(One Port -

CMOS Level Inputs)

COM'L

IND

S

L

60

90

80

55

85

74

55

85

74

CE^"A"< 0.2V and

(5)

CE^"B"> VCC - 0.2V

SEM^R= SEM^L> VCC - 0.2V

VIN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled,

____

S

L

(3)

f = fMAX

2945 tbl 09

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. V^CC= 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of

GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

3.3V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

1.5V

590Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

30pF

435Ω

5pF*

435Ω

1.5V

Figures 1 and 2

2945 tbl 10

2945 drw 05

2945 drw 04

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

* Including scope and jig.

6.42

6

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range^(4,5)

70V26X25

Com'l Only

70V26X35

Com'l Only

70V26X55

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

Read Cycle Time

25

35

55

ns

____

t^AA

Address Access Time

25

35

55

Chip Enable Access Time⁽³⁾

____

t^ACE

t^ABE

t^AOE

t^OH

Byte Enable Access Time⁽³⁾

Output Enable Access Time

15

20

30

____

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

t^LZ

3

Output High-Z Time^(1,2)

15

20

25

____

t^HZ

t^PU

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t^PD

25

35

50

____

t^SOP

t^SAA

15

____

35

45

65

ns

2945 tbl 11

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

5. Industrial temperature: for specific speeds, packages and powers contact your sales office.

Timing of Power-Up Power-Down

CE

t^PU

t^PD

ICC

ISB

50%

,

2945 drw 06

6.42

7

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE

OE

(4)

tAOE

tABE

(4)

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

BUSYOUT

(2)

tHZ

(3,4)

2945 drw 07

tBDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no

relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage^(5,6)

70V26X25

Com'l Only

70V26X35

Com'l Only

70V26X55

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time

25

20

0

35

30

0

55

45

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t^WP

t^WR

t^DW

t^HZ

20

0

25

0

40

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

15

20

30

____

15

20

25

____

t^DH

t^WZ

0

(1,2)

____

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4 )}

SEM Flag Write to Read Time

SEM Flag Contention Window

15

20

25

____

OW

t

0

5

0

5

0

5

____

t^SWRD

t^SPS

ns

2945 tbl 12

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and

temperature, the actual t^DHwill always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

6.42

8

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

AW

t

CE or SEM⁽⁹⁾

(3)

(2)

(6)

tWR

AS

t

WP

t

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

2945 drw 08

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing^(1,5)

t_WC

ADDRESS

t_AW

(9)

or

CE SEM

(6)

(3)

(2)

t_WR

t_EW

t_AS

(9)

or

UB LB

R/

W

t_DW

t_DH

DATA_IN

2945 drw 09

NOTES:

1. R/W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the

bus for the required t^DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.

9. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

6.42

9

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tOH

tSAA

VALID ADDRESS

tACE

A0-A2

tWR

tAW

tEW

tWP

SEM

tSOP

tDW

IN

VALID

OUT

DATA

(2)

DATA

I/O0

VALID

tAS

tDH

R/W

tSWRD

tAOE

OE

Write Cycle

Read Cycle

2945 drw 10

NOTES:

1. CE = V^IHor UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATA^OUTVALID' represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A^0"A"-A^2"A"

MATCH

SIDE⁽²⁾

"A"

R/W

SEM"A"

t^SPS

A^0"B"-A^2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

2945 drw 11

NOTES:

1. D^OR= DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"^A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If t^SPSis not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

6.42

10

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range^(6,7)

70V26X25

Com'l Only

70V26X35

Com'l Only

70V26X55

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = V^IH)

____

t^BAA

t^BDA

t^BAC

t^BDC

t^APS

t^BDD

t^WH

25

35

45

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Match

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

25

35

45

____

5

____

BUSY Disable to Valid Data⁽³⁾

35

40

50

Write Hold After BUSY⁽⁵⁾

20

25

____

BUSY INPUT TIMING (M/S = VIL)

BUSY Input to Write⁽⁴⁾

____

t^WB

0

ns

t^WH

PORT-TO-PORT DELAY TIMING

t^WDD

Write Pulse to Data Delay⁽¹⁾

t^DDD

Write Data Valid to Read Data Delay⁽¹⁾

Write Hold After BUSY⁽⁵⁾

20

25

____

55

50

65

60

85

80

ns

2945 tbl 13

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part number indicates power rating (S or L).

7. Industrial temperature: for specific speeds, packages and powers contact your sales office.

Timing Waveform of Write with Port-to-Port Read and BUSY^(2,4,5)

tWC

MATCH

ADDR"A"

R/W"A"

tWP

tDW

t_DH

VALID

DATA_{IN "A"}

(1)

tAPS

MATCH

tWDD

ADDR"B"

tBAA

tBDA

tBDD

BUSY_"B"

VALID

DATA_{OUT "B"}

(3)

t_DDD

NOTES:

2945 drw 12

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. If M/S = V^IL(SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

6.42

11

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY

tWP

R/W"A"

tWB

BUSY"B"

(1)

tWH

R/W"B"

(2)

2945 drw 13

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾

ADDR_"A"

ADDRESSES MATCH

and _"B"

CE"A"

(2)

tAPS

"B"

CE

t_BAC

t_BDC

BUSY"B"

2945 drw 14

Waveformof BUSY Arbitration Cycle Controlled by Address Match Timing⁽¹⁾

ADDR"A"

ADDR_"B"

BUSY"B"

ADDRESS "N"

(2)

t_APS

MATCHING ADDRESS "N"

t_BAA

t_BDA

2945 drw 15

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.

6.42

12

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table III Address BUSY

Arbitration

Inputs

Outputs

A^0L-A^13L

^0R-A^13R

(1)

A

Function

Normal

CE

L

CE^R

X

BUSY^L

H

BUSY^R

X

H

X

L

NO MATCH

MATCH

H

X

H

MATCH

H

L

MATCH

(2)

Write Inhibit⁽³⁾

2945 tbl 14

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V26 are push

pull, not open drain outputs. On slaves the BUSY^Xinput internally inhibits writes.

2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable

inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when

BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table IV Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D¹⁵Left

D⁰- D¹⁵Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2945 tbl 15

NOTE:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V26.

2. There are eight semaphore flags written to via I/O⁰and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.

3. CE = V^IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Functional Description

The IDT70V26 provides two ports with separate control, address RAMis “busy”. The BUSYpincanthenbe usedtostallthe access until

and I/O pins that permit independent access for reads or writes to any the operation on the other side is completed. If a write operation has

location in memory. The IDT70V26 has an automatic power down been attempted from the side that receives a BUSY indication, the

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry write signal is gated internally to prevent the write from proceeding.

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs

memory array is permitted.

The use of BUSY logic is not required or desirable for all applica-

togetheranduse anyBUSYindicationas aninterruptsource toflagan

illegal or illogical operation. If the write inhibit function of BUSYlogic is

not desirable, the BUSY logic can be disabled by placing the part in

slave mode with the M/S pin. Once in slave mode the BUSY pin

operates solely as a write inhibit input pin. Normal operation can be

programmed by tying the BUSY pins HIGH. If desired, unintended

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAMhave accessedthe same locationatthe same time. Italsoallows

one of the two accesses to proceed and signals the other side that the

6.42

13

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

write operations can be prevented to a port by tying the BUSY pin for are completelyindependentofeachother. This means thatthe activity

that port LOW. on the left port in no way slows the access time of the right port. Both

The BUSY outputs on the IDT 70V26 RAM in master mode, are ports are identical in function to standard CMOS Static RAM and can

push-pull type outputs and do not require pull up resistors to operate. be read from, or written to, at the same time with the only possible

If these RAMs are being expanded in depth, then the BUSYindication conflict arising from the simultaneous writing of, or a simultaneous

for the resulting array requires the use of an external AND gate.

READ/WRITE of, a non-semaphore location. Semaphores are pro-

tected against such ambiguous situations and may be used by the

system program to avoid any conflicts in the non-semaphore portion

of the Dual-Port SRAM. These devices have an automatic power-

downfeaturecontrolledbyCE,theDual-PortSRAMenable,andSEM,

the semaphore enable. The CE and SEM pins control on-chip power

downcircuitrythatpermits the respective porttogointostandbymode

when not selected. This is the condition which is shown in Truth Table

I where CE and SEM are both HIGH.

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT70V26 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive aBUSY indication, and to output that indication. Any

Systems which can best use the IDT70V26 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V26's

hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY

L

BUSY

R

Softwarehandshakingbetweenprocessors offers themaximumin

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70V26 does not use its semaphore

flags to control any resources through hardware, thus allowing the

system designer total flexibility in system architecture.

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY

R

BUSY

L

BUSY

R

BUSYL

2945 drw 16

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

Figure 3. Busy and chip enable routing for both width and depth expansion

with IDT70V26 RAMs.

number of slaves to be addressed in the same address range as the

master use the BUSY signal as a write inhibit signal. Thus on the

IDT70V26 SRAM the BUSY pin is an output if the part is used as a

master (M/S pin = H), and the BUSY pin is an input if the part used as

a slave (M/S pin = L) as shown in Figure 3.

If two or more master parts were used when expanding in width, a

splitdecisioncouldresultwithonemasterindicatingBUSYononeside

of the array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part

of a word and inhibit the write operations from the other port for word.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actualwrite pulse canbe initiatedwitheitherthe R/W signalorthe byte

enables. Failure to observe this timing can result in a glitched internal

write inhibit signal and corrupted data in the slave.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignmentmethodcalled“TokenPassingAllocation.”Inthis method,

thestateofasemaphorelatchisusedasatokenindicatingthatshared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

Semaphores

The IDT70V26 is an extremely fast Dual-Port 16K x 16 CMOS

Static RAM with an additional 8 address locations dedicated to binary

semaphore flags. These flags alloweitherprocessoronthe leftorright

side of the Dual-Port SRAM to claim a privilege over the other

processor for functions defined by the system designer’s software. As

an example, the semaphore can be used by one processor to inhibit

the otherfromaccessinga portionofthe Dual-PortSRAMoranyother

shared resource.

The eight semaphore flags reside within the IDT70V26 in a

separate memory space from the Dual-Port SRAM. This address

space is accessed by placing a LOW input on the SEM pin (which acts

as a chip select for the semaphore flags) and using the other control

pins (Address, OE, and R/W) as they would be used in accessing a

The Dual-Port SRAM features a fast access time, and both ports

6.42

14

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

standard Static RAM. Each of the flags has a unique address which semaphore is requested and the processor which requested it no

can be accessed by either side through address pins A0 – A2. When longer needs the resource, the entire system can hang up until a one

accessing the semaphores, none of the other address pins has any is written into that semaphore request latch.

effect.

The critical case of semaphore timing is when both sides request

When writing to a semaphore, only data pin D0 is used. If a LOW a single tokenbyattemptingtowrite a zerointoitatthe same time. The

level is written into an unused semaphore location, that flag will be set semaphore logic is specially designed to resolve this problem. If

to a zero on that side and a one on the other side (see Truth Table IV). simultaneous requests are made, the logic guarantees that only one

That semaphore can now only be modified by the side showing the side receives the token. If one side is earlier than the other in making

zero. When a one is written into the same location from the same side, the request, the first side to make the request will receive the token. If

the flagwillbe settoa one forbothsides (unless a semaphore request bothrequests arriveatthesametime,theassignmentwillbearbitrarily

fromtheothersideispending)andthencanbewrittentobybothsides. made to one port or the other.

The fact that the side which is able to write a zero into a semaphore

One caution that should be noted when using semaphores is that

subsequently locks out writes from the other side is what makes semaphores alone do not guarantee that access to a resource is

semaphore flags useful in interprocessor communications. (A thor- secure. As with any powerful programming technique, if semaphores

ough discussion on the use of this feature follows shortly.) A zero are misused or misinterpreted, a software error can easily happen.

written into the same location from the other side will be stored in the

semaphore request latch for that side until the semaphore is freed by handled via the initialization program at power-up. Since any sema-

the first side. phore request flag which contains a zero must be reset to a one, all

Initialization of the semaphores is not automatic and must be

Whena semaphore flagis read, its value is spreadintoalldata bits semaphores on both sides should have a one written into them at

so that a flag that is a one reads as a one in all data bits and a flag initialization from both sides to assure that they will be free when

containinga zeroreads as allzeros. The readvalue is latchedintoone needed.

side’s output register when that side's semaphore select (SEM) and

output enable (OE) signals go active. This serves to disallow the

UsingSemaphoresSomeExamples

Perhaps the simplest application of semaphores is their applica-

tion as resource markers for the IDT70V26’s Dual-Port RAM. Say the

16K x 16 RAM was to be divided into two 8K x 16 blocks which were

to be dedicated at any one time to servicing either the left or right port.

semaphore from changing state in the middle of a read cycle due to a

write cycle from the other side. Because of this latch, a repeated read

of a semaphore in a test loop must cause either signal (SEM or OE) to

go inactive or the output will never change.

A sequence WRITE/READ must be used by the semaphore in

Semaphore 0 could be used to indicate the side which would control

order to guarantee that no system level contention will occur. A

thelowersectionofmemory,andSemaphore1couldbedefinedasthe

processor requests access to shared resources by attempting to write

indicator for the upper section of memory.

a zero into a semaphore location. If the semaphore is already in use,

Totakearesource,inthisexamplethelower8Kof Dual-PortRAM,

the semaphore request latch will contain a zero, yet the semaphore

the processor on the left port could write and then read a zero in to

flag will appear as one, a fact which the processor will verify by the

Semaphore 0. If this task were successfully completed (a zero was

subsequent read (see Truth Table IV). As an example, assume a

read back rather than a one), the left processor would assume control

processorwritesazerototheleftportatafreesemaphorelocation.On

of the lower 8K. Meanwhile the right processor was attempting to gain

asubsequentread,theprocessorwillverifythatithas writtensuccess-

controlofthe resourceaftertheleftprocessor,itwouldreadbackaone

fully to that location and will assume control over the resource in

in response to the zero it had attempted to write into Semaphore 0. At

question. Meanwhile, if a processor on the right side attempts to write

this point, the software could choose to try and gain control of the

a zero to the same semaphore flag it will fail, as will be verified by the

second 8K section by writing, then reading a zero into Semaphore 1.

factthataonewillbereadfromthatsemaphoreontherightsideduring

If it succeeded in gaining control, it would lock out the left side.

subsequent read. Had a sequence of READ/WRITE been used

Once the left side was finished with its task, it would write a one to

instead, system contention problems could have occurred during the

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

L PORT

R PORT

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag low and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other

side as soon as a one is written into the first side’s request latch. The

second side’s flag will now stay low until its semaphore request latch

is written to a one. From this it is easy to understand that, if a

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

D0

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

2945 drw 17

Figure 4. IDT70V26 Semaphore Logic

6.42

15

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

undo its semaphore request and perform other tasks until it was able ously without any wait states.

to write, then read a zero into Semaphore 1. If the right processor

Semaphores are also useful in applications where no memory

performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe “WAIT” state is available on one or both sides. Once a semaphore

two processors to swap 8K blocks of Dual-Port RAM with each other. handshake has been performed, both processors can access their

The blocks do not have to be any particular size and can even be assigned RAM segments at full speed.

variable, depending upon the complexity of the software using the

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

semaphore flags. All eight semaphores could be used to divide the case, block arbitration is very important. For this application one

Dual-Port RAM or other shared resources into eight parts. Sema- processor may be responsible for building and updating a data

phores can even be assigned different meanings on different sides structure. The other processor then reads and interprets that data

rather than being given a common meaning as was shown in the structure. If the interpreting processor reads an incomplete data

example above.

structure, a major error condition may exist. Therefore, some sort of

Semaphores are a useful form of arbitration in systems like disk arbitration must be used between the two different processors. The

interfaces where the CPU must be locked out of a section of memory building processor arbitrates for the block, locks it and then is able to

during a transfer and the I/O device cannot tolerate any wait states. goinandupdatethedatastructure.Whentheupdateiscompleted,the

With the use of semaphores, once the two devices has determined data structure blockis released. This allows the interpretingprocessor

which memory area was “off-limits” to the CPU, both the CPU and the to come back and read the complete data structure, thereby guaran-

I/O devices could access their assigned portions of memory continu- teeing a consistent data structure.

6.42

16

IDT70V26S/L

High-Speed 16K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Ordering Information

IDT XXXXX

A

999

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

Commercial (0 C to +70 C)

°

(1)

I

Industrial (-40°C to +85°C)

G

J

84-pin PGA (G84-3)

84-pin PLCC (J84-1)

Commercial Only

25

35

55

Speed in nanoseconds

S

L

Standard Power

Low Power

70V26 256K (16K x 16) 3.3V Dual-Port RAM

2945 drw 18

NOTE:

1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

Datasheet Document History

3/25/99:

Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 and 3 Added additional notes to pin configurations

Changed drawing format

Page 1 RemovedPreliminary

Page 1 Changed660mWto660µW

Replaced IDT logo

6/10/99:

8/6/99:

8/30/99:

11/12/99:

6/6/00:

Page 5 Increasedstoragetemperatureparameter

ClarifiedTAparameter

Page 6 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Changed±200mVto0mVinnotes

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

17


型号：	IDT70V26L35J
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM 高速3.3V 16K ×16双口静态RAM
文件：	总17页 (文件大小：145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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