IDT70V3589S166BFGI [IDT]
Dual-Port SRAM, 64KX36, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FBGA-208;
| 型号： | IDT70V3589S166BFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 64KX36, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FBGA-208 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3599/89S
Features:
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
◆
◆
High-speed data access
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
GridArray(BGA)
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHzoperation(12Gbps bandwidth)
– Fast 3.6ns clock to data out
◆
◆
◆
◆
◆
◆
◆
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
◆
◆
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
BE3R
BE3L
BE2L
BE1L
BE0L
BE2R
BE1R
BE0R
FT/PIPE
L
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
FT/PIPE
R
1/0
1/0
R/WL
R/WR
CE0L
CE0R
1
1
CE1R
CE1L
0
0
B
W
0
B
W
1
B B
B
B
B
B
1/0
1/0
W W W
W
W W
2
L
3
L
3
R
2
R
1
R
0
R
L
L
OE
R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
,
1d 0d 1c 0c
1b 0b 1a 0a
0a 1a 0b 1b
0c 1c 0d 1d
d c b a
0/1
0/1
FT/PIPE
L
FT/PIPER
abcd
128K x 36
MEMORY
ARRAY
I/O0L - I/O35L
I/O0R - I/O35R
Din_L
Din_R
,
CLKR
CLKL
(1)
(1)
A
A
A
16L
16R
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
0R
ADDR_R
ADDR_L
REPEAT
ADS
CNTEN
L
REPEAT
ADS
CNTEN
R
R
L
R
L
5617 tbl 01
TDI
TCK
TMS
TRST
JTAG
TDO
NOTE:
1. A16 is a NC for IDT70V3589.
JULY 2008
1
DSC 5617/7
©2008 IntegratedDeviceTechnology,Inc.
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V3599/89is ahigh-speed128/64Kx36bitsynchronous or bidirectional data flow in bursts. An automatic power down feature,
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlledbyCE0andCE1, permits the on-chipcircuitryofeachportto
allowsimultaneousaccessofanyaddressfrombothports.Registerson enter a very low standby power mode.
control, data, and address inputs provide minimal setup and hold
The70V3599/89cansupportanoperatingvoltageofeither3.3Vor
times. The timing latitude provided by this approach allows systems 2.5Vononeorbothports,controllablebytheOPTpins.Thepowersupply
tobedesignedwithveryshortcycletimes.Withaninputdataregister,the forthe core ofthe device (VDD)remains at3.3V.
IDT70V3599/89hasbeenoptimizedforapplicationshavingunidirectional
PinConfiguration(1,2,3,4,5)
06/28/02
A1
A2
A3
A6
A7
A8
A9
BE1L
A11
A12
A13
A14
A17
A4
A5
A10
A15
A16
IO19L IO18L
V
SS
A
16L(1)
A
12L
A
8L
CLK
L
CNTEN
L
A4L
A0L
V
SS
TDO
NC
VDD
OPT
L
I/O17L
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
I/O20R
V
SS I/O18R
A
13L
A
9L
ADS
L
A
5L
6L
3L
A
1L
I/O15R
TDI
NC
BE2L
V
SS
V
SS
VDDQR I/O16L
C1
C6
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
V
DDQL
A
14L
I/O19R
VDDQR PL/FT
L
NC
A
10L BE3L CE1L
V
SS R/W
L
A
A
2L
I/O15L
VDD I/O16R
VSS
D1
D2
D6
D9
D11
REPEATL
D3
D5
D7
D8
D10
D12
D13
D14 D15
D16
D17
D4
I/O22L
V
SS
A
11L
V
DD
I/O21L
A
15L
A
7L BE0L
OE
L
A
V
DD I/O17R
V
DDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
V
DDQR I/O21R
I/O12L
V
SS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
V
DDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
V
SS
G1
I/O26L
G2
G4
G14
G15
G16
G3
G17
V
SS
I/O24R
H4
I/O9L
V
DDQL I/O10L
I/O25L
I/O11R
H3
H1
H2
H16
H17
H14
H15
70V3599/89BF
BF-208(6)
V
DDQR I/O25R
VDD I/O26R
VSS I/O10R
VDD IO9R
J1
J2
J3 J4
J14
J15
J16
J17
V
DDQL
VDD
V
SS
V
SS
V
SS
V
DD
VSS
VDDQR
208-Pin fpBGA
Top View(7)
K2
K4
K15
K16
K1
K3
K14
K17
V
SS
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
VSS
L3
L4
L15
L16
L17
L1
L2
L14
VDDQR I/O27L
I/O7L
VSS
I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
DDQR
M14
M15
V
DDQL I/O29L I/O30R
V
SS
I/O5R V
V
SS
I/O6L
N16
N17
N4
N15
N1
N2
P2
N3
N14
I/O4R I/O5L
DDQL
I/O30L
V
I/O31L
V
SS I/O31R
I/O3R
P1
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P17
P6
P13
A16R(1)
A4R
I/O32R I/O32L
VDDQR I/O35R TRST
A
12R
A
8R BE1R
VDD CLK
R
CNTEN
R
I/O2L I/O3L
V
SS I/O4L
R5
R6
R7
R8
R9
R10
R11
R16
R1 R2
R3
R4
R12
R13
R14
R17
R15
NC
A
13R
A
9R
BE2R CE0R
V
SS ADS
R
I/O1R
V
DDQL
VSS I/O33L I/O34R TCK
A5R
A
1R
V
SS
DDQR
V
T2
I/O34L
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
T7
T10
T11
T12
T13
T14
V
DDQL
TMS NC
I/O33R
BE3R CE1R
I/O0R
V
SS I/O2R
A
14R
A
10R
V
SS R/W
R
A
6R
A2R
VSS
U1
U2
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
U16
U15
V
SS I/O35L PL/FT
R
NC
A
15R
A
11R
A
7R
I/O1L
V
DD
OE
R
A
3R
A0R
V
DD
I/O0L
OPT
R
,
5617 drw 02c
NOTES:
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4,5) (con't.)
70V3599/89BC
BC-256(6)
256-Pin BGA
Top View(7)
06/28/02
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
CNTEN
L
A
5L
A
2L
A
0L
NC
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
10L
A
REPEAT
L
A4L
A
1L
NC
A
15L
BE3L
R/W
L
VDD I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
(1)
I/O18R
A
13L
A
I/O19L
V
SS
A
16L
A
BE1L BE0L CLK
L
ADS
L
A
6L
A
3L
I/O16L
OPT
L
I/O17R
D1
D2
D6
DDQL
D9
D11
DDQR
D3
D5
VDDQL
L
D7
DDQR
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
V
VDDQL
V
VDDQL
I/O20L
V
V
DDQR
VDDQR
VDD I/O15R I/O15L I/O16R
PIPE/FT
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
SS
SS
V
SS
V
SS
SS
SS
V
SS
V
SS
V
DD
V
DD
V
DDQR
I/O21R I/O21L I/O22L
V
DDQL
I/O13L
I/O14R
I/O14L
F7
F1 F2 F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
V
SS
VDD
V
VSS
V
SS
I/O23L I/O22R I/O23R
G1
VSS
VDDQR I/O12R I/O13R I/O12L
V
VDD
V
DDQL
G5
H5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14 G15 G16
G11
I/O24R
V
SS
SS
SS
I/O24L
V
DDQR
V
V
V
SS
SS
I/O25L
I/O10L I/O11L I/O11R
H16
VSS
V
SS
VSS
V
DDQL
VSS
H11
H12
H13
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
V
SS
VSS
VDDQL
I/O10R
V
SS
VSS
V
V
SS
SS
I/O9R IO9L
V
VSS
I/O26R
V
DDQR
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL
V
V
SS
V
SS
VSS
VSS
VDDQR
V
VSS
V
SS
I/O8R
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
L5
K7
K9
K11
K2
K4
K15
K16
K1
K3
K14
V
SS
V
SS
V
SS
SS
VSS
VDDQR
I/O29L
VDDQL
V
SS
DD
V
SS
V
SS
V
SS
I/O6L I/O7L
I/O29R
I/O28L
I/O6R
L7
L8
M8
N8
L11
L12
L13
L3
L4
L6
L9
L10
L15
L16
L1
L2
L14
V
SS
V
SS
V
SS
V
DD
VDDQL
I/O30R
V
DDQR
V
V
SS
V
SS
V
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
DD
VDD
VDDQL
I/O32R I/O32L I/O31L
V
DDQR
I/O4L
I/O3R I/O3L
N12
N16
N13
N4
N5
N6
DDQR
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
VDD
I/O2R
I/O1R
VDDQR
V
VDDQL
VDDQR
VDDQR
V
DDQL
PIPE/FT
R
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
(1)
I/O35R I/O34L TMS
A
16R
A13R
A
7R BE1R BE0R CLK
R
ADSR
A6R
I/O0L I/O0R I/O1L
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
REPEAT
R
NC
I/O35L NC TRST NC
A
4R
A1R OPT
R
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
TCK
NC
NC
NC
A14R
BE2R CE1R
NC
NC
A
11R
A
8R
OER
CNTEN
R
A
5R
A2R
A0R
5617 drw 02d
NOTES:
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
,
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4,5) (con't.)
06/28/02
I/O16L
156
1
2
3
4
5
6
I/O19L
I/O19R
I/O20L
I/O20R
I/O16R
155
I/O15L
154
I/O15R
153
V
V
SS
V
DDQL
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DDQL
VSS
I/O14L
I/O14R
I/O13L
I/O13R
7
8
9
I/O21L
I/O21R
I/O22L
I/O22R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V
V
SS
V
DDQR
DDQR
VSS
I/O12L
I/O12R
I/O11L
I/O11R
I/O23L
I/O23R
I/O24L
I/O24R
V
V
SS
V
DDQL
DDQL
VSS
I/O10L
I/O10R
I/O9L
I/O25L
I/O25R
I/O26L
I/O26R
I/O9R
V
V
V
V
V
V
V
V
SS
V
DDQR
SS
DD
DD
SS
SS
DDQL
SS
DDQR
DD
70V3599/89DR
V
V
V
V
(6)
DD
DR-208
SS
SS
V
SS
V
DDQL
208-Pin PQFP
V
I/O8R
I/O8L
I/O7R
I/O7L
I/O27R
I/O27L
I/O28R
I/O28L
(7)
Top View
V
V
SS
V
DDQR
DDQR
VSS
I/O6R
I/O6L
I/O5R
I/O5L
I/O29R
I/O29L
I/O30R
I/O30L
V
V
SS
V
DDQL
DDQL
VSS
I/O4R
I/O4L
I/O3R
I/O3L
I/O31R
I/O31L
I/O32R
I/O32L
V
V
SS
V
DDQR
DDQR
VSS
I/O2R
I/O2L
I/O1R
I/O1L
I/O33R
I/O33L
I/O34R
I/O34L
,
5617 drw 02a
NOTES:
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 28mm x 28mm x 3.5mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
4
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
Chip Enables(5)
CE0L
R/W
OE
,
CE1L
CE0R, CE1R
L
R/W
R
Read/Write Enable
Output Enable
L
OE
R
(1)
(1)
A
0L - A16L
A0R - A16R
Address
I/O0L - I/O35L
CLK
I/O0R - I/O35R
CLK
Data Input/Output
Clock
L
R
PL/FT
ADS
CNTEN
REPEAT
BE0L - BE3L
L
PL/FT
ADS
CNTEN
REPEAT
BE0R - BE3R
R
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
L
R
L
R
(4)
Counter Repeat
L
R
(5)
Byte Enables (9-bit bytes)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(2)
NOTES:
(2,3)
1. A16 is a NC for IDT70V3589.
OPTL
OPTR
Option for selecting VDDQX
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
(2)
VDD
Power (3.3V)
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
V
SS
Ground (0V)
TDI
TDO
TCK
TMS
TRST
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5617 tbl 01
6.42
5
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3,4)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
↑
CE
1
R/W
X
X
X
L
MODE
OE
CE
0
BE
3
BE
2
BE
1
BE0
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
X
↑
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
↑
X
DIN
Write to Byte 0 Only
↑
X
H
H
H
L
L
DIN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
↑
X
H
H
L
L
DIN
High-Z
High-Z
↑
X
H
H
L
L
DIN
High-Z
High-Z
↑
X
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
↑
X
H
L
H
L
L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
↑
X
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
Read Byte 0 Only
↑
L
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
↑
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
↑
L
H
H
L
DOUT
High-Z
High-Z
↑
L
H
H
L
DOUT
High-Z
High-Z
↑
L
H
L
High-Z
DOUT
D
OUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
High-Z Outputs Disabled
↑
L
L
H
L
H
L
DOUT
DOUT
High-Z
↑
L
L
DOUT
DOUT
DOUT
DOUT
↑
H
L
L
L
L
High-Z
High-Z
High-Z
↑
5617 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
(3)
ADS CNTEN REPEAT(6)
CLK
↑
I/O
(4)
X
An
An
X
X
X
An
An
X
X
X
H
L
D
I/O(0)
Counter Reset to last valid ADS load
(4)
L
H
D
I/O (n) External Address Used
I/O(p) External Address Blocked—Counter disabled (Ap reused)
DI/O(p+1) Counter Enabled—Internal Address generation
↑
Ap
Ap
Ap
H
H
H
H
D
↑
(5)
Ap + 1
L
↑
5617 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
6
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
RecommendedDCOperating
TemperatureandSupplyVoltage(1)
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
Max.
3.45
2.6
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
V
DD
DDQ
SS
IH
3.15 3.3
3.3V
3.3V
+
+
150mV
150mV
V
2.4
0
2.5
V
Industrial
0V
V
0
V
5617 tbl 04
(2)
____
V
DDQ + 100mV
Input High Voltage
1.7
V
V
NOTES:
(Address & Control Inputs)
1. This is the parameter TA. This is the "instant on" case temperature.
(3)
(2)
____
____
V
IH
Input High Voltage - I/O
1.7
V
DDQ + 100mV
V
VIL
Input Low Voltage
-0.3(1)
0.7
V
5617 tbl 05a
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPTpinforthatportmustbesettoVIL (0V),andVDDQX forthatportmustbesupplied
as indicated above.
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
& Industrial
Unit
(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
V
TERM
RecommendedDCOperating
Conditions with VDDQ at 3.3V
(3)
Temperature Under Bias
-55 to +125
oC
T
BIAS
STG
JN
OUT
oC
oC
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
3.45
3.45
0
Unit
V
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
V
DD
DDQ
SS
IH
T
V
V
I
50
mA
V
0
0
V
5617 tbl 06
NOTES:
(2)
____
Input High Voltage
(Address & Control Inputs)
2.0
VDDQ + 150mV
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
(3)
(3)
(2)
____
____
V
IH
Input High Voltage - I/O
2.0
V
DDQ + 150mV
V
VIL
Input Low Voltage
-0.3(1)
0.8
V
5617 tbl 05b
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
7
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
CIN
VIN = 3dV
8
pF
(3)
OUT
C
VOUT = 3dV
10.5
pF
5617 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3599/89S
Symbol
Parameter
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
Min.
Max.
10
Unit
µA
µA
V
Input Leakage Current(1)
___
___
___
|ILI|
(1)
|ILO
OL (3.3V) Output Low Voltage(2)
OH (3.3V) Output High Voltage(2)
OL (2.5V) Output Low Voltage(2)
OH (2.5V) Output High Voltage(2)
|
Output Leakage Current
10
CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
V
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5617 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
6.42
8
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3599/89S166 70V3599/89S133
Com'l
& Ind
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
370
Max.
500
Typ.(4)
320
320
115
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
mA
mA
mA
CE
L
and CER= VIL,
Outputs Disabled,
S
S
S
S
S
S
400
480
160
195
290
350
____
____
(1)
IND
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH,
Outputs Disabled,
f = fMAX
COM'L
IND
125
200
____
____
(1)
115
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
250
350
220
220
____
____
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports Outputs Disabled
L and CER > VDDQ - 0.2V,
IN > VDDQ - 0.2V or VIN < 0.2V,
COM'L
IND
S
S
S
S
15
30
15
15
30
40
CE
V
f = 0
____
____
(2)
(5)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
IN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
(1)
COM'L
IND
250
350
220
220
290
350
V
____
____
f = fMAX
5617 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
9
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
833Ω
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
DATAOUT
1.5V/1.25V
5pF*
770Ω
Figures 1 and 2
5617 tbl 10
,
3.3V
590Ω
5pF*
50Ω
50Ω
,
DATAOUT
DATAOUT
1.5V/1.25
10pF
435Ω
(Tester)
5617 drw 03
Figure 1. AC Output Test load.
,
5617 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
∆tCD
(Typical, ns)
3
2
•
1
•
•
•
,
20.5
50
80 100
200
30
-1
Capacitance (pF)
5617 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
10
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3599/89S166
Com'l Only
70V3599/89S133
Com'l
& Ind
Symbol
Parameter
Min.
20
Max.
Min.
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Clock Cycle Time (Flow-Through)
(1)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Clock Cycle Time (Pipelined)
6
7.5
7
t
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
6
t
6
7
t
2.1
2.1
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
2.6
2.6
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
t
t
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
t
Input Data Hold Time
t
ADS Setup Time
t
ADS Hold Time
t
CNTEN Setup Time
____
____
____
____
____
____
t
CNTEN Hold Time
t
REPEAT Setup Time
t
0.5
0.5
REPEAT Hold Time
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
4.0
4.2
____
____
t
1
1
t
1
3.6
12
1
4.2
15
____
____
t
____
____
t
3.6
4.2
____
____
t
1
1
1
1
1
1
t
3
3
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
tCO
5
6
ns
5617 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
6.42
11
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE1
t
SB
tHB
t
t
(5)
BEn
R/W
tHW
tSW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2 (5)
(1)
tCKLZ
t
OHZ
tOLZ
(1)
OE
tOE
5617 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
(3)
CE1
tSB
tHB
tHB
BEn
tSB
R/W
tSW
tHW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
tCKLZ
tDC
tOHZ
tOLZ
OE(1)
tOE
5617 drw 07
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
12
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q0
A2
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA tHA
A6
A5
A4
A3
A0
A1
tSC tHC
CE0(B2)
tSC tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5617 drw 08
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
t
DC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
tSC
tHC
(1)
(1)
t
CD1
t
CKHZ
t
CD1
(1)
tCKHZ
D4
DATAOUT(B2)
D2
(1)
t
CKLZ
tCKLZ
5617 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3599/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
13
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
t
SW
SA
t
HW
HA
t
t
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
tDC
5617 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
t
CO
t
CD1
R/W "B"
t
HW
HA
t
SW
t
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
t
CD1
VALID
VALID
tDC
t
DC
5617 drw 11
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
14
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE
CE
BE
0
1
n
t
SC
tHC
tSB
tHB
tSW tHW
R/W
tSW tHW
ADDRESS(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
5617 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
tSW tHW
R/W
tSW tHW
ADDRESS(3)
DATAIN
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
t
SA
tHA
t
SD
tHD
Dn + 2
tCD2
tCD2
tCKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
5617 drw 13
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
15
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD1
t
CD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
t
DC
t
CKLZ
t
DC
t
CKHZ
NOP(5)
READ
WRITE
6517 drw 14
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(2)
tCYC1
CH1
t
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
tSW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
CD1
tDC
t
CD1
t
CD1
t
(1)
Qn + 4
Qn
DATAOUT
t
CKLZ
t
DC
t
OHZ
OE
READ
WRITE
READ
5617 drw 15
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
16
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
t
SCN tHCN
tCD2
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qx
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5617 drw 16
Timing Waveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
t
SAD
tHAD
ADS
tSCN
tHCN
CNTEN
t
CD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
5617 drw 17
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
17
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5617 drw 18
Timing Waveform of Counter Repeat(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
LAST ADS +1
An
An + 1
tSW tHW
R/W
ADS
t
SAD
tHAD
CNTEN
tSCN tHCN
tSRPT
tHRPT
REPEAT
tSD
tHD
D0
DATAIN
(5)
QLAST+1
Qn
QLAST
DATAOUT
EXECUTE (6)
REPEAT
READ
LAST ADS
ADDRESS
READ
ADDRESS n
READ
ADDRESS n+1
WRITE
READ
LAST ADS
LAST ADS
ADDRESS
ADDRESS + 1
5617 drw 19
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, BEn = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
18
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
The IDT70V3599/89 provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70V3599/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3599/89 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding72-bitsorwider.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3599/89s for depth
expansionconfigurations. Twocycles arerequiredwith CE0 LOWand
CE1HIGHtore-activatetheoutputs.
(1)
A17/A16
IDT70V3599/89
IDT70V3599/89
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3599/89
IDT70V3599/89
CE1
CE1
CE0
CE0
BE,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
ADS,
REPEAT,
CNTEN
5617 drw 20
Figure 4. Depth and Width Expansion with IDT70V3599/89
NOTE:
1. A17 is for IDT70V3599, A16 is for IDT70V3589.
6.42
19
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
TRST
,
5617 drw 21
t
JRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70V3599/89
Max.
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Units
ns
____
____
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
t
ns
t
40
ns
(1)
____
t
3
ns
(1)
____
t
3
ns
____
____
t
50
ns
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
5617 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
20
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x0312(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
IDRegister Indicator Bit (Bit 0)
5617 tbl 13
NOTE:
1. Device ID for IDT70V3589 is 0x0313.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5617 tbl 14
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the by pass registe r (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0011
0001
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
5617 tbl 15
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
21
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
IDT XXXXX
A
999
A
A
Process/
Temperature
Range
Device
Type
Power Speed
Package
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(1)
Green
BF
DR
BC
208-pin fpBGA (BF-208)
208-pin PQFP (DR-208)
256-pin BGA (BC-256)
166
133
Commercial Only
Commercial & Industrial
Speed in Megahertz
S
Standard Power
70V3599 4Mbit (128K x 36-Bit) Synchronous Dual-Port RAM,
70V3589 2Mbit (64K x 36-Bit) Synchronous Dual-Port RAM
5617 drw 22
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your local sales office.
IDT Clock Solution for IDT70V3599/89 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT
PLL
Clock Device
IDT Dual-Port
Part Number
Input Duty
Cycle
Requirement
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
3.3/2.5
I/O
70V3599/89
LVTTL
8pF
40%
166
75ps
IDT5V2528
5617 tbl16a
6.42
22
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory:
06/02/00:
07/12/00:
07/30/01:
InitialPublicOffering
Addedmuxtofunctionalblockdiagram
ChangedmaximumvalueforJTAGACElectricalCharacteristicsfortJCD from20nsto25ns
Page 20
Page 9
AddedIndustrialTemperatureDCParameters
11/20/01:
Page 2, 3 & 4
Addeddaterevisionforpinconfigurations
Page 11
Page 1 & 22
Page 10
ChangedtOE valueinACElectricalCharacteristics,pleaserefertoErrata#SMEN-01-05
Replaced TM logo with ® logo
ChangedACTestConditionsInputRise/FallTimes
Consolidatedmultipledevicesintoonedatasheet
AddedDCDcapabilityforPipelinedOutputs
07/01/02:
Page 1 & 5
Page 7
Clarified TBIAS and added TJN
Page 9
ChangedDCElectricalParameters
Page 11
RemovedClockRise&FallTimefromACElectricalCharacteristicsTable
RemovedPreliminarystatus
05/19/03:
01/10/06:
Page 11
Page 22
Page 1
AddedByteEnableSetupTime&ByteEnableHoldTimetoACElecctricalCharacteristicsTable
AddedIDTClockSolutionTable
Addedgreenavailabilitytofeatures
Page 5
Page 22
Page 9
Changedfootnote 2forTruthTable IfromADS, CNTEN, REPEAT=VIH toADS, CNTEN, REPEAT=X
Addedgreenindicatortoorderinginformation
Corrected a typo in the DC Chars table
07/25/08:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
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