IDT70V9389L9PFGI8

更新时间:2024-10-30 04:25:20
品牌:IDT
描述:Application Specific SRAM, 64KX18, 20ns, CMOS, PQFP100

IDT70V9389L9PFGI8 概述

Application Specific SRAM, 64KX18, 20ns, CMOS, PQFP100

IDT70V9389L9PFGI8 数据手册

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HIGH-SPEED 3.3V  
64K x18/x16  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
IDT70V9389/289L  
Features:  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6/7.5/9/12ns(max.)  
Industrial:9ns (max.)  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
Low-power operation  
IDT70V9389/289L  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
LVTTL- compatible, single 3.3V (±0.3V) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 128-pin Thin Quad Flatpack (TQFP) and  
100-pin Thin Quad Flatpack (TQFP)  
Green parts available, see ordering information  
Active:500mW(typ.)  
Standby: 1.5mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
FunctionalBlockDiagram  
R/  
W
R
R/  
W
L
L
UB  
R
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
OE  
L
LB  
OE  
R
L
R
1b 0b  
0a 1a  
1a 0a  
a
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
FT/PIPER  
b
a
(1)  
(2)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(1)  
(1)  
I/O0R-I/O8R  
I/O0L-I/O8L  
A
15R  
A
15L  
0L  
L
L
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
MEMORY  
ARRAY  
A
0R  
CLK  
CLK  
ADS  
CNTEN  
R
R
ADS  
CNTEN  
R
L
CNTRST  
R
CNTRST  
L
4856 drw 01  
NOTE:  
1. I/O0X - I/O7X for IDT70V9289.  
2. I/O8X - I/O15X for IDT70V9289.  
JUNE 2008  
1
©2008IntegratedDeviceTechnology,Inc.  
DSC-4856/5  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Description:  
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit  
Withaninputdataregister,theIDT70V9389/289hasbeenoptimized  
synchronous Dual-Port RAM. The memory array utilizes Dual-Port forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An  
memorycellstoallowsimultaneousaccessofanyaddressfrombothports. automaticpowerdownfeature,controlledbyCE0andCE1, permitsthe  
Registersoncontrol,data,andaddressinputsprovideminimalsetupand on-chip circuitry of each port to enter a very low standby power mode.  
holdtimes.Thetiminglatitudeprovidedbythisapproachallowssystems Fabricated using IDTs CMOS high-performance technology, these  
tobedesignedwithveryshortcycletimes.  
devices typicallyoperate ononly500mWofpower.  
PinConfiguration(1,2,3)  
03/28/03  
I/O12R  
I/O11R  
1
2
3
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
NC  
NC  
NC  
NC  
V
SS  
NC  
I/O10R  
4
5
6
7
8
A9R  
A8R  
I/O9R  
I/O8R  
A7R  
A6R  
A5R  
A4R  
A3R  
A2R  
I/O7R  
V
DD  
9
10  
I/O6R  
I/O5R  
I/O4R  
92  
91  
90  
89  
88  
87  
86  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
V
SS  
A
A
1R  
0R  
I/O3R  
V
DD  
NC  
I/O2R  
I/O1R  
I/O0R  
CNTEN  
R
CLK  
R
70V9389PRF  
PK-128-1(4)  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
ADS  
R
V
SS  
V
SS  
V
DD  
V
DD  
I/O0L  
I/O1L  
ADS  
L
128-Pin TQFP  
Top View(5)  
CLK  
L
V
SS  
CNTEN  
L
23  
24  
25  
26  
I/O2L  
I/O3L  
NC  
A
A
A
A
A
A
A
A
0L  
1L  
2L  
3L  
4L  
V
SS  
I/O4L  
I/O5L  
I/O6L  
I/O7L  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
5L  
6L  
7L  
V
DD  
I/O8L  
I/O9L  
I/O10L  
NC  
A
A
8L  
9L  
NC  
NC  
NC  
NC  
V
DD  
I/O11L  
I/O12L  
4856 drw 02  
NOTES:  
1. All VDD pins must be connected to power supply.  
2. All VSS pins must be connected to ground.  
3. Package body is approximately 14mm x 20mm x 1.4mm.  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part-marking.  
6.42  
2
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
PinConfigurations(1,2,3)(con't.)  
03/28/03  
INDEX  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
1
A
9L  
A
A
8R  
9R  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
2
A10L  
A11L  
A12L  
A13L  
A14L  
A15L  
A
A
A
A
A
A
LB  
UB  
CE0R  
CE1R  
CNTRST  
R/W  
V
OE  
FT/PIPE  
I/O17R  
V
10R  
11R  
12R  
13R  
14R  
15R  
3
4
5
6
7
8
LB  
UB  
CE0L  
L
L
9
R
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
R
70V9389PF  
PN100-1(4)  
CE1L  
CNTRST  
L
R
R/W  
OE  
L
100-Pin TQFP  
Top View(5)  
R
L
V
DD  
SS  
,
FT/PIPE  
L
R
I/O17L  
I/O16L  
R
V
SS  
SS  
I/O15L  
I/O14L  
I/O13L  
I/O12L  
I/O11L  
I/O10L  
I/O16R  
I/O15R  
I/O14R  
I/O13R  
I/O12R  
I/O11R  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
4856 drw 02a  
NOTES:  
1. All VDD pins must be connected to power supply.  
2. All VSS pins must be connected to ground.  
3. Package body is approximately 14mm x 14mm x 1.4mm  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part-marking.  
6.42  
3
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
PinConfigurations(1,2,3)(con't.)  
03/28/03  
I/O10R  
I/O9R  
1
2
3
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
NC  
NC  
NC  
NC  
V
SS  
NC  
I/O8R  
4
5
6
7
8
A9R  
A8R  
NC  
NC  
I/O7R  
A7R  
A6R  
A5R  
A4R  
A3R  
A2R  
V
DD  
9
10  
I/O6R  
I/O5R  
I/O4R  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
V
SS  
A
A
1R  
0R  
I/O3R  
V
DD  
NC  
I/O2R  
I/O1R  
I/O0R  
CNTEN  
R
R
R
CLK  
70V9289PRF  
PK-128-1(4)  
ADS  
V
SS  
V
SS  
V
DD  
V
DD  
I/O0L  
I/O1L  
ADS  
L
128-Pin TQFP  
Top View(5)  
CLK  
L
V
SS  
CNTEN  
L
I/O2L  
I/O3L  
NC  
A
A
A
A
A
A
A
A
0L  
1L  
2L  
3L  
4L  
V
SS  
I/O4L  
I/O5L  
I/O6L  
I/O7L  
27  
28  
29  
30  
31  
32  
33  
34  
35  
5L  
6L  
7L  
V
DD  
NC  
NC  
I/O8L  
NC  
A
A
8L  
9L  
NC  
NC  
NC  
NC  
V
DD  
36  
37  
38  
I/O9L  
65  
I/O10L  
4856 drw 02b  
NOTES:  
1. All VDD pins must be connected to power supply.  
2. All VSS pins must be connected to ground.  
3. Package body is approximately 14mm x 20mm x 1.4mm.  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part-marking.  
6.42  
4
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
PinConfigurations(1,2,3)(con't.)  
03/28/03  
Index  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
A
A
A
A
A
A
A
NC  
NC  
LB  
9R  
1
A
9L  
75  
74  
10R  
11R  
12R  
13R  
14R  
15R  
2
A10L  
A11L  
A12L  
A13L  
A14L  
A15L  
3
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
4
5
6
7
8
NC  
NC  
LB  
UB  
CE0L  
9
R
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
L
IDT70V9289PF  
PN100-1  
UB  
CE0R  
CE1R  
CNTRST  
R
L
(4)  
CE1L  
100-Pin TQFP  
.
R
(5)  
CNTRST  
L
Top View  
V
SS  
VDD  
R/W  
OE  
FT/PIPE  
R
R/W  
OE  
FT/PIPE  
L
L
L
R
R
V
SS  
V
SS  
I/O15L  
I/O14L  
I/O13L  
I/O12L  
I/O11L  
I/O10L  
I/O15R  
I/O14R  
I/O13R  
I/O12R  
I/O11R  
I/O10R  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
4856 drw 02c  
NOTES:  
1. All VDD pins must be connected to power supply.  
2. All VSS pins must be connected to ground.  
3. Package body is approximately 14mm x 14mm x 1.4mm  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part-marking.  
6.42  
5
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
PinNames  
Left Port  
Right Port  
Names  
Chip Enables(3)  
CE0L, CE1L  
R/W  
OE  
0L - A15L  
I/O0L - I/O17L  
CLK  
CE0R, CE1R  
R/W  
OE  
0R - A15R  
I/O0R - I/O17R  
CLK  
L
R
Read/Write Enable  
Output Enable  
Address  
L
R
A
A
(1)  
(1)  
Data Input/Output  
Clock  
L
R
Upper Byte Select(2)  
UB  
LB  
ADS  
CNTEN  
CNTRST  
FT/PIPE  
L
UB  
LB  
ADS  
CNTEN  
CNTRST  
FT/PIPE  
R
(2)  
Lower Byte Select  
L
R
Address Strobe Enable  
Counter Enable  
L
R
L
R
Counter Reset  
L
R
Flow-Through / Pipeline  
Power (3.3V)  
L
R
NOTE:  
1. I/O0X - I/O15X for IDT70V9289.  
V
DD  
2. LB and UB are single buffered regardless of state of FT/PIPE.  
3. CEo and CE1 are single buffered when FT/PIPE = VIL,  
CEo and CE1 are double buffered when FT/PIPE = VIH,  
i.e. the signals take two cycles to deselect.  
VSS  
Ground (0V)  
4856 tbl 01  
Truth Table I—Read/Write and Enable Control(1,2,3)  
Upper Byte  
Lower Byte  
(7)  
MODE  
(6)  
CLK  
CE (5)  
1
R/W  
X
X
X
L
I/O9-17  
I/O0-8  
(5)  
OE  
X
X
X
X
X
X
L
CE  
0
UB(4)  
X
X
H
L
LB(4)  
X
X
H
H
L
H
X
L
L
L
L
L
L
L
L
X
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
DATAIN  
DATAIN  
High-Z  
DATAOUT  
DATAOUT  
High-Z  
DeselectedPower Down  
DeselectedPower Down  
Both Bytes Deselected  
Write to Upper Byte Only  
Write to Lower Byte Only  
Write to Both Bytes  
H
H
H
H
H
H
H
H
DIN  
H
L
L
High-Z  
DATAIN  
DATAOUT  
High-Z  
L
L
L
H
L
H
H
H
X
Read Upper Byte Only  
Read Lower Byte Only  
Read Both Bytes  
L
H
L
L
L
DATAOUT  
High-Z  
H
X
L
L
Outputs Disabled  
4856 tbl 02  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. ADS, CNTEN, CNTRST = X.  
3. OE is an asynchronous input signal.  
4. LB and UB are single buffered regardless of state of FT/PIPE.  
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.  
6. I/O8 - I/O15 for IDT70V9289.  
7. I/O0 - I/O7 for IDT70V9289.  
6.42  
6
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Truth Table II—Address Counter Control(1,2)  
Previous Internal  
MODE  
External  
Address  
Internal Address  
(3)  
Address  
Used  
CLK  
I/O  
ADS  
CNTEN CNTRST  
(4)  
X
An  
An  
X
X
X
0
X
X
X
H
L
D
I/O(0)  
Counter Reset to Address 0  
(4)  
An  
L
H
D
I/O(n)  
External Address Loaded into Counter  
Ap  
Ap  
Ap  
H
H
H
H
D
I/O(p)  
External Address BlockedCounter disabled (Ap reused)  
(5)  
Ap + 1  
L
DI/O(p+1) Counter EnabledInternal Address generation  
4856 tbl 03  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.  
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.  
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.  
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.  
RecommendedOperating  
RecommendedDCOperating  
Conditions  
TemperatureandSupplyVoltage(1)  
Symbol  
Parameter  
Supply Voltage  
Ground  
Min.  
Typ.  
Max.  
3.6  
0
Unit  
V
Ambient  
Grade  
Commercial  
Temperature(2)  
0OC to +70OC  
-40OC to +85OC  
GND  
0V  
VDD  
V
DD  
SS  
IH  
IL  
3.0  
3.3  
3.3V  
3.3V  
+
0.3V  
V
0
0
V
Industrial  
0V  
+
0.3V  
(2)  
____  
V
Input High Voltage  
Input Low Voltage  
2.0  
VDD+0.3V  
V
4856 tbl 04  
____  
NOTES:  
V
-0.3(1)  
0.8  
V
1. This is the parameter TA. This is the "instant on" case temperature.  
4856 tbl 05  
NOTES:  
1. VIL > -1.5V for pulse width less than 10 ns.  
2. VTERM must not exceed VDD +0.3V.  
AbsoluteMaximumRatings(1)  
Capacitance(1)  
(TA = +25°C, f = 1.0MHZ)  
Symbol  
Rating  
Commercial  
& Industrial  
Unit  
Symbol  
Parameter  
Input Capacitance  
Output Capacitance  
Conditions(2)  
Max. Unit  
(2)  
V
TERM  
Terminal Voltage  
with Respect to  
GND  
-0.5 to +4.6  
V
CIN  
VIN = 3dV  
9
pF  
(3)  
OUT  
(3)  
TBIAS  
Te mp e rature  
Under Bias  
-55 to +125  
-65 to +150  
oC  
oC  
oC  
C
VOUT = 3dV  
10  
pF  
4856 tbl 07  
NOTES:  
TSTG  
Storage  
Te mp e rature  
1. These parameters are determined by device characterization, but are not  
production tested.  
2. 3dV references the interpolated capacitance when the input and output switch  
from 0V to 3V or from 3V to 0V.  
TJN  
Junction Temperature  
DC Output Current  
+150  
50  
IOUT  
mA  
3. COUT also references CI/O.  
4856 tbl 06  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated  
in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns  
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.  
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.  
6.42  
7
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)  
70V9389/289L  
Symbol  
|ILI  
|ILO  
Parameter  
Test Conditions  
Min.  
Max.  
5
Unit  
µA  
µA  
V
(1)  
___  
___  
___  
|
Input Leakage Current  
Output Leakage Current  
Output Low Voltage  
VDD = 3.6V, VIN = 0V to VDD  
|
5
CE = VIH or CE  
OL = +4mA  
OH = -4mA  
1 = VIL, VOUT = 0V to VDD  
VOL  
I
0.4  
___  
VOH  
Output High Voltage  
I
2.4  
V
4856 tbl 08  
NOTE:  
1. At VDD < 2.0V input leakages are undefined.  
DC Electrical Characteristics Over the Operating  
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)  
70V9389/289L6(6)  
Com'l Only  
70V9389/289L7  
Com'l Only  
70V9389/289L9  
Com'l & Ind  
70V9389/289L12  
Com'l Only  
Symbol  
Parameter  
Test Condition  
= VIL  
Version  
COM'L  
Typ.(4)  
Max.  
Typ.(4)  
Max.  
Typ.(4)  
Max.  
230  
240  
65  
Typ.(4)  
Max.  
Unit  
IDD  
Dynamic Operating  
Current (Both  
Ports Active)  
mA  
L
L
L
L
L
L
220  
280  
200  
250  
175  
180  
40  
150  
200  
CE  
L
and CE  
R
,
Outputs Disabled,  
____  
(1)  
____  
____  
____  
____  
____  
IND  
f = fMAX  
ISB1  
Standby Current  
(Both Ports - TTL  
Level Inputs)  
mA  
mA  
COM'L  
IND  
60  
85  
50  
75  
30  
50  
CEL  
= CE  
R
= VIH  
(1)  
f = fMAX  
____  
____  
____  
____  
____  
____  
50  
70  
ISB2  
Standby  
COM'L  
IND  
145  
185  
130  
165  
110  
145  
95  
130  
CE"A" = VIL and  
(5)  
Current (One  
Port - TTL  
Level Inputs)  
CE"B" = VIH  
Active Port Outputs Disabled,  
____  
____  
____  
____  
____  
____  
110  
0.4  
0.4  
100  
155  
2
(1)  
f=fMAX  
ISB3  
Full Standby  
Current (Both  
Ports - CMOS  
Level Inputs)  
Both Ports CE  
CE > VDD - 0.2V,  
IN > VDD - 0.2V or  
IN < 0.2V, f = 0(2)  
L
and  
mA  
mA  
COM'L  
IND  
L
L
0.4  
2
0.4  
2
0.4  
2
R
V
V
____  
____  
____  
____  
____  
____  
2
ISB4  
Full Standby  
Current (One  
Port - CMOS  
Level Inputs)  
COM'L  
IND  
L
L
145  
180  
130  
160  
140  
90  
125  
CE"A" < 0.2V and  
(5)  
CE"B" > VDD - 0.2V  
IN > VDD - 0.2V or  
IN < 0.2V, Active Port,  
Outputs Disabled, f = fMAX  
V
V
____  
____  
____  
____  
____  
____  
100  
155  
(1)  
4856 tbl 09  
NOTES:  
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input  
levels of GND to 3V.  
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.  
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ).  
5. CEX = VIL means CE0X = VIL and CE1X = VIH  
CEX = VIH means CE0X = VIH or CE1X = VIL  
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V  
CEX > VDD - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V  
"X" represents "L" for left port or "R" for right port.  
6. This speed grade available in PK-128 package only.  
6.42  
8
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
AC Test Conditions  
Input Pulse Levels  
GND to 3.0V  
3ns Max.  
Input Rise/Fall Times  
Input Timing Reference Levels  
Output Reference Levels  
Output Load  
1.5V  
1.5V  
Figures 1, 2, and 3  
4856 tbl 10  
3.3V  
3.3V  
590  
590Ω  
DATAOUT  
DATAOUT  
30pF  
435Ω  
5pF*  
435Ω  
.
.
4856 drw 03  
4856 drw 04  
Figure 2. Output Test Load  
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).  
*Including scope and jig.  
Figure 1. AC Output Test load.  
8
7
6
5
- 10pF is the I/O capacitance  
of this device, and 30pF is the  
AC Test Load Capacitance  
tCD  
tCD  
(Typical, ns)  
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200  
Capacitance (pF)  
-1  
.
4856 drw 05  
Figure 3. Typical Output Derating (Lumped Capacitive Load).  
6.42  
9
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
AC Electrical Characteristics Over the Operating Temperature Range  
(Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)  
70V9389/289L6(4)  
Com'l Only  
70V9389/289L7  
Com'l Only  
70V9389/289L9  
Com'l & Ind  
70V9389/289L12  
Com'l Only  
Symbol  
Parameter  
Clock Cycle Time (Flow-Through)(2)  
Min.  
19  
Max.  
Min.  
22  
Max.  
Min.  
25  
15  
12  
12  
6
Max.  
Min.  
30  
20  
12  
12  
8
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
____  
t
CYC1  
CYC2  
CH1  
CL1  
CH2  
CL2  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
Clock Cycle Time (Pipelined)(2)  
Clock High Time (Flow-Through)(2)  
Clock Low Time (Flow-Through)(2)  
10  
12  
t
6.5  
6.5  
4
7.5  
7.5  
5
t
(2)  
t
Clock High Time (Pipelined)  
t
Clock Low Time (Pipelined)(2)  
Clock Rise Time  
4
5
6
8
____  
____  
____  
____  
tR  
3
3
3
3
____  
____  
____  
____  
tF  
Clock Fall Time  
3
3
3
3
____  
____  
____  
____  
t
SA  
HA  
SC  
HC  
SB  
HB  
SW  
HW  
SD  
HD  
SAD  
HAD  
SCN  
HCN  
SRST  
HRST  
OE  
OLZ  
OHZ  
CD1  
CD2  
DC  
CKHZ  
CKLZ  
Address Setup Time  
Address Hold Time  
Chip Enable Setup Time  
Chip Enable Hold Time  
Byte Enable Setup Time  
Byte Enable Hold Time  
R/W Setup Time  
3.5  
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
t
3.5  
0
t
t
3.5  
0
t
t
3.5  
0
t
R/W Hold Time  
t
Input Data Setup Time  
Input Data Hold Time  
ADS Setup Time  
3.5  
0
t
t
3.5  
0
t
ADS Hold Time  
t
3.5  
0
CNTEN Setup Time  
CNTEN Hold Time  
t
t
3.5  
CNTRST Setup Time  
CNTRST Hold Time  
Output Enable to Data Valid  
t
0
0
1
1
____  
____  
____  
____  
t
6.5  
7.5  
9
12  
(1)  
____  
____  
____  
____  
t
Output Enable to Output Low-Z  
2
2
2
2
(1)  
t
Output Enable to Output High-Z  
1
7
1
7
1
7
1
7
____  
____  
____  
____  
t
Clock to Data Valid (Flow-Through)(2)  
15  
18  
20  
25  
(2)  
____  
____  
____  
____  
t
Clock to Data Valid (Pipelined)  
6.5  
7.5  
9
12  
____  
____  
____  
____  
t
Data Output Hold After Clock High  
2
2
2
2
2
2
2
2
2
2
2
2
(1)  
t
Clock High to Output High-Z  
9
9
9
9
(1)  
____  
____  
____  
____  
t
Clock High to Output Low-Z  
Port-to-Port Delay  
____  
____  
____  
____  
____  
____  
____  
____  
t
CWDD  
Write Port Clock High to Read Data Delay  
Clock-to-Clock Setup Time  
24  
9
28  
10  
35  
15  
40  
15  
ns  
tCCS  
ns  
4856 tbl 11  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-  
tion, but is not production tested.  
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply  
when FT/PIPE = VIL for that port.  
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.  
4. This speed grade available in PK-128 package only.  
6.42  
10  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of Read Cycle for  
Flow-Through Output (FT/PIPE"X" = VIL)(3,7)  
t
CYC1  
t
CH1  
t
CL1  
CLK  
CE  
0
t
SC  
tHC  
t
SC  
tHC  
CE1  
t
SB  
tHB  
t
HB  
UB, LB  
tSB  
R/  
W
t
SW  
SA  
t
HW  
HA  
t
t
ADDRESS(5)  
DATAOUT  
An  
An + 1  
An + 2  
An + 3  
t
DC  
(1)  
t
CD1  
t
CKHZ  
Qn  
Qn + 1  
Qn + 2  
(1)  
OHZ  
(1)  
t
DC  
t
CKLZ  
t
(1)  
t
OLZ  
OE(2)  
..  
t
OE  
4856 drw 06  
Timing Waveform of Read Cycle for Pipelined Operation  
(FT/PIPE"X" = VIH)(3,7)  
tCYC2  
tCH2  
tCL2  
CLK  
CE  
0
t
SC  
tHC  
t
SC  
t
HC  
HB  
(4)  
CE1  
t
SB  
tHB  
t
tSB  
(6)  
UB, LB  
R/W  
tHW  
tSW  
tHA  
tSA  
ADDRESS(5)  
DATAOUT  
An  
An + 1  
An + 2  
Qn  
An + 3  
(1 Latency)  
tDC  
tCD2  
(6)  
Qn + 1  
Qn + 2  
(1)  
tCKLZ  
(1)  
t
OHZ  
(1)  
tOLZ  
OE(2)  
tOE  
4856 drw 07  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.  
3. ADS = VIL, CNTEN and CNTRST = VIH.  
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.  
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers  
are for reference use only.  
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).  
7. "X' here denotes Left or Right port. The diagram is with respect to that port.  
6.42  
11  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of a Bank Select Pipelined Read(1,2)  
t
CYC2  
tCH2  
tCL2  
CLK  
ADDRESS(B1)  
CE0(B1)  
t
SA  
tHA  
A6  
A5  
A4  
A3  
A
2
A
0
A1  
tSC  
tHC  
t
SC  
tHC  
(3)  
tCD2  
tCKHZ  
tCD2  
tCD2  
Q
0
Q3  
Q
1
DATAOUT(B1)  
ADDRESS(B2)  
(3)  
(3)  
tDC  
tCKLZ  
tCKHZ  
t
DC  
tSA  
tHA  
A6  
A5  
A4  
A3  
A2  
A
0
A1  
tSC  
tHC  
CE0(B2)  
tSC  
tHC  
(3)  
tCD2  
tCKHZ  
tCD2  
DATAOUT(B2)  
Q4  
Q2  
(3)  
(3)  
tCKLZ  
tCKLZ  
4856 drw 08  
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)  
CLK "A"  
tSW  
tHW  
R/W "A"  
ADDRESS "A"  
DATAIN "A"  
CLK "B"  
t
SA  
MATCH  
SD HD  
VALID  
tHA  
NO  
MATCH  
t
t
(6)  
tCCS  
tCD1  
R/W "B"  
tHW  
tSW  
t
HA  
tSA  
NO  
MATCH  
ADDRESS "B"  
DATAOUT "B"  
MATCH  
(6)  
t
CD1  
tCWDD  
VALID  
VALID  
tDC  
t
DC  
4856 drw 09  
NOTES:  
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9389 or IDT70V9289 for this waveform, and are setup for depth expansion  
in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.  
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.  
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.  
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.  
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.  
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.  
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".  
6.42  
12  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)  
tCYC2  
tCH2  
tCL2  
CLK  
CE0  
tSC  
tHC  
CE1  
tSB  
tHB  
UB, LB  
tSW tHW  
R/W  
tSW tHW  
(4)  
An + 4  
An + 3  
An  
SA  
An +1  
An + 2  
An + 2  
ADDRESS  
t
tHA  
t
SD  
tHD  
DATAIN  
Dn + 2  
(1)  
(1)  
tCKLZ  
tCD2  
tCD2  
(2)  
tCKHZ  
Qn + 3  
Qn  
DATAOUT  
READ  
NOP(5)  
WRITE  
READ  
4856 drw 10  
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)  
t
CYC2  
tCH2  
tCL2  
CLK  
CE0  
tSC  
tHC  
CE1  
tSB  
tHB  
UB, LB  
t
SW tHW  
R/W  
tSW  
t
HW  
(4)  
An + 4  
An  
An +1  
An + 2  
An + 3  
Dn + 3  
An + 5  
ADDRESS  
t
SA  
tHA  
t
SD  
tHD  
DATAIN  
Dn + 2  
(1)  
CKLZ  
tCD2  
tCD2  
t
(2)  
Qn  
Qn + 4  
DATAOUT  
(1)  
OHZ  
t
OE  
READ  
WRITE  
READ  
4856 drw 11  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.  
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".  
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for  
reference use only.  
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.  
6.42  
13  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)  
t
CYC1  
tCH1  
tCL1  
CLK  
CE  
0
1
tSC  
tHC  
CE  
tSB  
tHB  
UB, LB  
t
SW tHW  
R/W  
tSW tHW  
(4)  
An + 4  
An  
An + 3  
An +1  
An + 2  
An + 2  
ADDRESS  
tSA  
tHA  
t
SD  
t
HD  
DATAIN  
Dn + 2  
t
CD1  
tCD1  
tCD1  
tCD1  
(2)  
Qn + 3  
Qn  
READ  
Qn + 1  
DATAOUT  
(1)  
(1)  
tDC  
tCKLZ  
tDC  
t
CKHZ  
NOP(5)  
READ  
WRITE  
4856 drw 12  
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)  
tCYC1  
tCH1  
tCL1  
CLK  
CE  
0
1
tSC  
tHC  
CE  
tSB  
tHB  
UB, LB  
tSW tHW  
tSW tHW  
R/W  
(4)  
An + 5  
An  
An + 4  
An +1  
An + 2  
An + 3  
Dn + 3  
ADDRESS  
DATAIN  
t
SA  
tHA  
t
SD tHD  
Dn + 2  
tOE  
tDC  
t
CD1  
tCD1  
tCD1  
(2)  
Qn + 4  
Qn  
DATAOUT  
(1)  
CKLZ  
(1)  
t
tDC  
tOHZ  
OE  
READ  
WRITE  
READ  
4856 drw 13  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.  
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".  
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for  
reference use only.  
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.  
6.42  
14  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of Pipelined Read with Address Counter Advance(1)  
t
CYC2  
t
CH2  
tCL2  
CLK  
t
SA  
tHA  
An  
ADDRESS  
tSAD tHAD  
ADS  
t
SAD tHAD  
CNTEN  
tSCN tHCN  
t
CD2  
Qn + 2(2)  
Qn + 3  
Qx - 1(2)  
Qn + 1  
Qn  
Qx  
DATAOUT  
tDC  
READ  
EXTERNAL  
ADDRESS  
READ  
WITH  
COUNTER  
COUNTER  
HOLD  
READ WITH COUNTER  
4856 drw 14  
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)  
t
CYC1  
tCH1  
tCL1  
CLK  
tSA  
tHA  
An  
ADDRESS  
t
SAD tHAD  
t
SAD  
tHAD  
ADS  
tSCN  
tHCN  
CNTEN  
tCD1  
Qn + 3(2)  
Qx(2)  
Qn + 4  
Qn + 1  
Qn + 2  
Qn  
DATAOUT  
t
DC  
READ  
WITH  
COUNTER  
READ  
EXTERNAL  
ADDRESS  
READ WITH COUNTER  
COUNTER  
HOLD  
4856 drw 15  
NOTES:  
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.  
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data  
output remains constant for subsequent clocks.  
6.42  
15  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
Timing Waveform of Write with Address Counter Advance  
(Flow-Through or Pipelined Outputs)(1)  
t
CYC2  
tCH2  
tCL2  
CLK  
tSA  
tHA  
An  
ADDRESS  
INTERNAL(3)  
ADDRESS  
An(7)  
An + 4  
An + 2  
An + 1  
An + 3  
tSAD tHAD  
ADS  
CNTEN(7)  
tSD tHD  
Dn + 4  
Dn + 1  
Dn + 3  
Dn  
Dn + 1  
Dn + 2  
DATAIN  
WRITE  
EXTERNAL  
ADDRESS  
WRITE  
WITH COUNTER  
WRITE  
COUNTER HOLD  
WRITE WITH COUNTER  
4856 drw 16  
Timing Waveform of Counter Reset (Pipelined Outputs)(2)  
t
CYC2  
tCH2  
tCL2  
CLK  
tSA tHA  
ADDRESS(4)  
An + 2  
An  
An + 1  
INTERNAL(3)  
ADDRESS  
Ax(6)  
0
1
An  
An + 1  
tSW tHW  
R/W  
ADS  
t
t
SAD  
SCN  
tHAD  
CNTEN  
tHCN  
tSRST  
tHRST  
CNTRST  
tSD  
tHD  
D
0
DATAIN  
(5)  
Qn  
Q1  
Q0  
DATAOUT  
COUNTER(6)  
RESET  
WRITE  
ADDRESS 0  
READ  
ADDRESS 0  
READ  
READ  
READ  
ADDRESS 1  
ADDRESS n ADDRESS n+1  
NOTES:  
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.  
CE0, UB, LB = VIL; CE1 = VIH.  
4856 drw 17  
2.  
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.  
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.  
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.  
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles  
are shown here simply for clarification.  
7. CNTEN = VIL advances Internal Address from An’ to An +1. The transition shown indicates the time required for the counter to advance.  
The ‘An +1’ Address is written to during this cycle.  
6.42  
16  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
FunctionalDescription  
Depth and Width Expansion  
TheIDT70V9389/289providesatruesynchronousDual-PortStatic  
TheIDT70V9389/289featuresdualchipenables(refertoTruthTable  
RAMinterface.Registeredinputsprovideminimalset-upandholdtimes I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-  
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare mentsforexternallogic.Figure4illustrateshowtocontrolthevarioiuschip  
clocked on the rising edge of the clock signal, however, the self-timed enables in order to expand two devices in depth.  
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock  
signal.  
The IDT70V9389/289 can also be used in applications requiring  
expandedwidth,asindicatedinFigure4.Sincethebanksareallocated  
An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive  
bus interfacing. Counter enable inputs are also provided to staff the theinputsignalsforthevariousdevicesasrequiredtoallowfor36/32-bit  
operationoftheaddresscountersforfastinterleavedmemoryapplications. orwiderapplications.  
CE0=VIH orCE1=VILforoneclockcyclewillpowerdowntheinternal  
circuitrytoreducestaticpowerconsumption.Multiplechipenablesallow  
easierbankingofmultipleIDT70V9389/289'sfordepthexpansioncon-  
figurations.WhenthePipelinedoutputmodeisenabled,twocyclesare  
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.  
A
16  
IDT70V9389/289  
Control Inputs  
CE  
0
1
IDT70V9389/289  
Control Inputs  
CE  
0
1
CE  
V
DD  
V
DD  
CE  
IDT70V9389/289  
Control Inputs  
IDT70V9389/289  
Control Inputs  
CE  
1
0
CE  
1
0
CE  
CE  
CNTRST  
CLK  
ADS  
CNTEN  
R/W  
4856 drw 18  
LB, UB  
OE  
Figure 4. Depth and Width Expansion with IDT70V9389/289  
6.42  
17  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
OrderingInformation  
IDT XXXXX  
A
99  
A
A
A
Device  
Type  
Power Speed  
Package  
Process/  
Temperature  
Range  
Blank  
I (1)  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
G(2)  
Green  
128-pin TQFP (PK128-1)  
100-pin TQFP (PN100-1)  
PRF  
PF  
Commercial Only(3)  
Commercial Only  
Commercial & Industrial  
6
7
9
Speed in nanoseconds  
12  
Commercial Only  
L
Low Power  
70V9389 1152K (64K x 18-Bit) Synchronous Dual-Port RAM  
70V9289 1024K (64K x 16-Bit) Synchronous Dual-Port RAM  
4856 drw 19  
NOTES:  
1. Industrial temperature range is available.  
For specific speeds, packages and powers contact your sales office.  
2. Green parts available. For specific speeds, packages and powers contact your local sales office.  
3. This speed grade available in PK-128 package only.  
IDT Clock Solution for IDT70V9389/289 Dual-Port  
Dual-Port I/O Specitications  
Dual-Port Clock Specifications  
IDT  
PLL  
Clock Devices  
IDT  
Non-PLL Clock  
Devices  
IDT Dual-Port Part  
Number  
Input Duty  
Maximum  
Cycle  
Input  
Capacitance  
Jitter  
Tolerance  
Voltage  
I/O  
Frequency  
Requirement  
FCT3805  
FCT3805D/E  
FCT3807  
IDT2305  
IDT2308  
IDT2309  
70V9389/289  
3.3  
LVTTL  
9pF  
40%  
100  
150ps  
FCT3807D/E  
4856 tbl12  
6.42  
18  
IDT70V9389/289L  
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM  
Industrial & Commercial Temperature Ranges  
DatasheetDocumentHistory  
09/30/99:  
11/12/99:  
06/23/00:  
InitialPublicRelease  
Replaced IDT logo  
ChangedinformationinTruthTableII  
Increasedstoragetemperatureparameters  
ClarifiedTAparameter  
Page 3  
Page 4  
Page 5  
DCElectricalparameters–changedwordingfrom"open"to"disabled"  
Changed±200mVto0mVinnotes  
04/09/03:  
Consolidatedmultipledevicesintoonedatasheet  
Changednamingconventions fromVCC toVDD andfromGNDtoVss  
AddedPN-100TQFPpinconfiguration  
AddedPN-100TQFPavailabilityandorderinginformation  
Addeddaterevisiontopinconfigurations  
Page 3 & 5  
Page 1 & 18  
Page 2 - 5  
Page 7  
AddedjunctiontemperaturetoAbsoluteMaximumRatingsTable  
AddedAmbientTemperaturefootnote  
Page 8, 10 & 18 Added 6ns speed grade  
Page 8  
AddedupdatedDCpowernumberstotheDCElectricalCharacteristicsTable  
Page 10  
Added6nsspeedACtimingnumbersandchangedtOE tobeequaltotCD2 intheACElectricalCharacteristics  
Table  
Page 18  
Page 1& 19  
Page 1  
AddedIDTClockSolutionTable  
Removed"Preliminary"status  
Addedgreenavailabilitytofeatures  
Addedgreenindicatortoorderinginformation  
01/10/06:  
06/03/08:  
Page 18  
Page 8, 10 & 18 Designated 6ns speed grade available in PK-128 package only  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
408-284-2794  
DualPortHelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
6.42  
19  

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