IDT71128S20Y8 [IDT]

Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;


型号：	IDT71128S20Y8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器光电二极管内存集成电路
文件：	总8页 (文件大小：79K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CMOS Static RAM

1 Meg (256K x 4-Bit)

Revolutionary Pinout

IDT71128

Description

Features

◆

The IDT71128 is a 1,048,576-bit high-speed static RAM

organized as 256K x 4. It is fabricated using IDT’s high-perfor-

mance, high-reliability CMOS technology. This state-of-the-art

technology, combined with innovative circuit design techniques,

provides a cost-effective solution for high-speed memory needs.

The JEDEC centerpower/GND pinout reduces noise generation

and improves system performance.

256K x 4 advanced high-speed CMOS static RAM

◆

JEDEC revolutionary pinout (center power/GND) for

reduced noise.

Equal access and cycle times

◆

— Commercial and Industrial: 12/15/20ns

One Chip Select plus one Output Enable pin

Bidirectional inputs and outputs directly

◆

The IDT71128 has an output enable pin which operates as fast

as 6ns, with address access times as fast as 12ns available. All

bidirectional inputs and outputs of the IDT71128 are TTL-compat-

ible and operation is from a single 5V supply. Fully static asyn-

chronous circuitry is used; no clocks or refreshes are required for

operation.

TTL-compatible

Low power consumption via chip deselect

Available in a 32-pin 400 mil Plastic SOJ.

◆

The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.

Functional Block Diagram

1,048,576-BIT

MEMORY

ARRAY

ADDRESS

DECODER

A17

I/O0 - I/O3

I/O CONTROL

CONTROL

LOGIC

3483 drw 01

FEBRUARY 2001

DSC-3483/09

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Pin Configuration

Absolute Maximum Ratings⁽¹⁾

Symbol

Rating

Value

Unit

A17

A16

A15

A14

A13

(2)

TERM

Terminal Voltage with

Respect to GND

-0.5 to +7.0⁽²⁾

^oC

Operating Temperature

0 to +70

BIAS

Temperature

Under Bias

-55 to +125

I/O3

GND

VCC

I/O2

A12

A11

A10

SO32-3

I/O0

VCC

GND

I/O1

STG

Storage

-55 to +125

^oC

Temperature

Power Dissipation

DC Output Current

1.25

OUT

3483 tbl 02

NOTES:

1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause

permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation

ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational

sections of this specification is not implied. Exposure to absolute maximum rating

conditionsforextendedperiodsmayaffectreliability.

3483 drw 02

2. VTERMmustnotexceedVcc+0.5V.

SOJ

Top View

Capacitance

(TA = +25°C, f = 1.0MHz, SOJ package)

Truth Table^(1,2)

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

I/O

Function

DATA^OUTRead Data

CI/O

DATA^INWrite Data

3483 tbl 03

NOTE:

High-Z Output Disabled

High-Z Deselected - Standby (I^SB)

1. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.

(3)

High-Z Deselected - Standby (I^SB1)

V^HC

Recommended Operating

Temperature and Supply Voltage

3483 tbl 01

NOTES:

1. H = VIH, L = VIL, x = Don't care.

2. VLC = 0.2V, VHC = VCC -0.2V.

3. Other inputs ≥VHC or ≤VLC.

Grade

Temperature

0°C to +70°C

–40°C to +85°C

GND

Commercial

Industrial

5.0V ± 10%

3483 tbl 04

Recommended DC Operating

Conditions

Symbol

Parameter

Min.

Typ.

Max.

5.5

Unit

V^CC

Supply Voltage

4.5

5.0

GND

Ground

____

Input High Voltage

Input Low Voltage

2.2

+0.5

V^IL

-0.5⁽¹⁾

0.8

____

3483 tbl 05

NOTE:

1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.

6.422

IDT 71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

Symbol

|ILI|

Parameter

Input Leakage Current

Test Conditions

VCC = Max., VIN = GND to VCC

VCC = Max., CS = VIH, VOUT = GND to VCC

IOL = 8mA, VCC = Min.

Min.

Max.

Unit

µA

___

|ILO|

Output Leakage Current

Output Low Voltage

Output High Voltage

VOL

0.4

___

VOH

IOH = -4mA, VCC = Min.

2.4

3483 tbl 06

DC Electrical Characteristics⁽¹⁾

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

71128S12

71128S15

Com'l.

71128S20

Symbol

Parameter

Dynamic Operating Current

Com'l.

Ind.

Com'l.

Ind.

Unit

155

150

145

(2)

CS < V^IL, Outputs Open, V^CC= Max., f = f^MAX

Standby Power Supply Current (TTL Level)

(2)

MAX

CS > V , Outputs Open, V = Max., f = f

Full Standby Power Supply Current (CMOS Level)

SB1

(2)

CS > V , Outputs Open, V = Max., f = 0

V < V or V > V

3483 tbl 07

NOTES:

1. Allvaluesaremaximumguaranteedvalues.

2. fMAX =1/tRC (alladdress inputs are cyclingatfMAX); f=0means noaddress inputlines are changing.

AC Test Conditions

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

3ns

1.5V

See Figure 1 and 2

3483 tbl 08

AC Test Loads

480Ω

255Ω

OUT

DATA

OUT

DATA

5pF*

255Ω

30pF

3483 drw 04

3483 drw 03

*Including jig and scope capacitance.

Figure 1. AC Test Load

Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

6.42

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)

71128S12

71128S15

71128S20

Symbol

READ CYCLE

t^RC

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

Read Cycle Time

____

t^AA

Address Access Time

____

t^ACS

Chip Select Access Time

Chip Select to Output in Low-Z

(1)

____

t^CLZ

(1)

Chip Deselect to Output in High-Z

Output Enable to Output Valid

t^CHZ

____

t^OE

(1)

____

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

Output Hold from Address Change

Chip Select to Power-Up Time

Chip Deselect to Power-Down Time

t^OLZ

(1)

t^OHZ

____

t^OH

(1)

____

t^PU

(1)

____

tPD

WRITE CYCLE

____

t^WC

t^AW

t^CW

t^AS

Write Cycle Time

Address Valid to End of Write

Chip Select to End of Write

Address Set-up Time

Write Pulse Width

t^WP

t^WR

t^DW

t^DH

Write Recovery Time

Data Valid to End-of-Write

Data Hold Time

(1)

____

Output active from End-of-Write

t^OW

(1)

Write Enable to Output in High-Z

t^WHZ

3483 tbl 09

NOTE:

1. This parameterguaranteedwiththeACload(Figure2)bydevicecharacterization,butis notproductiontested.

6.442

IDT 71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle No. 1⁽¹⁾

tRC

ADDRESS

(5)

OLZ

(3)

ACS

(5)

tOHZ

CLZ

(5)

CHZ

HIGH IMPEDANCE

DATAOUT

DATAOUT VALID

CC SUPPLY

CURRENT

3483 drw 05

Timing Waveform of Read Cycle No. 2^{(1, 2, 4)}

ADDRESS

DATAOUT VALID

DATAOUT

PREVIOUS DATAOUT VALID

3483 drw 06

NOTES:

1. WE is HIGH for Read Cycle.

2. Deviceiscontinuouslyselected,CSisLOW.

3. AddressmustbevalidpriortoorcoincidentwiththelaterofCStransitionLOW;otherwisetAAisthelimitingparameter.

4. OEisLOW.

5. Transitionismeasured±200mVfromsteadystate.

6.42

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^{(1, 2, 4)}

ADDRESS

tAW

(2)

tWR

tWP

(5)

tCHZ

(5)

tWHZ

tOW

HIGH IMPEDANCE

(3)

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

3483 drw 07

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)^{(1, 4)}

tWC

ADDRESS

tWR

tCW

tDW

tDH

DATAIN

DATAIN VALID

3483 drw 08

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. OEis continuouslyHIGH. DuringaWEcontrolledwritecyclewithOELOW,tWP mustbegreaterthanorequaltotWHZ+tDW toallowtheI/Odriverstoturnoffanddatatobeplaced

onthe bus forthe requiredtDW. If OEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is the specifiedtWP.

3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.

4. IftheCSLOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahighimpedancestate. CSmustbeactiveduringthetCW writeperiod.

5. Transitionismeasured±200mVfromsteadystate.

6.462

IDT 71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Ordering Information

IDT

71128

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

400-mil SOJ (SO32-3)

Speed in nanoseconds

3483 drw 09

6.42

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Datasheet Document History

8/5/99

Updated to new format

Removed military entries from DC table

Pg. 3

Pg. 4

Pg. 6

Pg. 8

Removed Note 1, renumbered notes and footnotes

Added Datasheet Document History

8/13/99

9/30/99

2/18/00

3/14/00

8/09/00

02/01/01

Pg. 1, 3, 4, 7

Pg. 3

Added12ns,15ns,and20nsindustrialtemperaturespeedgradeofferings

ReviseISBforIndustrialTemperatureofferingstomeetcommericalspecifications

RevisedISBtoaccomidatespeedfunctionality

Notrecommendedfornewdesigns

Removed"Notrecommendedfornewdesigns"

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for Tech Support:

800-345-7015 or 408-727-6116 sramhelp@idt.com

fax: 408-492-8674

www.idt.com

800-544-7726, x4033

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.482

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