IDT71215S12PF [IDT]
BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the PentiumO Processor; BiCMOS工艺StaticRAM 240K （ 16K ×15位） CACHE - TAG RAM对于PentiumO处理器
| 型号： | IDT71215S12PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the PentiumO Processor |
| 文件： | 总14页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
IDT71215
For the Pentium Processor
Integrated Device Technology, Inc.
This high-speed MATCH signal, with tADM as fast as 8ns,
provides the fastest possible enabling of secondary cache
accesses.
FEATURES:
• 16K x 15 Configuration
– 12 TAG Bits
The three separate I/O status bits (VLD, DTY, and WT) can
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET pin, when held LOW at a rising clock edge, will reset
all status bits in the array for easy invalidation of all Tag
addresses.
The IDT71215 also provides the option for Burst Ready
(BRDY) generation within the cache tag itself, based upon
MATCH, VLD bit, WT bit, and external inputs provided by the
user. This can significantly simplify cache controller logic and
minimize cache decision time. Match and Read operations
are both asynchronous in order to provide the fastest access
times possible, while Write operations are synchronous for
ease of system timing.
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range
• BRDY circuitry included inside the Cache-Tag for highest
speed operation
• Asynchronous Read/Match operation with Synchronous
Write and Reset operation
• Separate WE for the TAG bits and the Status bits
• Separate OE for the TAG bits, the Status bits, and BRDY
• Synchronous RESET pin for invalidation of all Tag entries
• Dual Chip selects for easy depth expansion with no
performance degredation
• I/O pins both 5V TTL and 3.3V LVTTL compatible with
VCCQ pins
• PWRDN pin to place device in low-power mode
• Packaged in a 80-pin Thin Plastic Quad Flat Pack
(TQFP)
The IDT71215 uses a 5V power supply on Vcc with sepa-
rate VCCQ pins provided for the outputs to offer compliance
withboth5.0VTTLand3.3VLVTTLLogiclevels. ThePWRDN
pin offers a low-power standby mode to reduce power con-
sumption by 90%, providing significant system power sav-
ings.
The IDT71215 is fabricated using IDT's high-performance,
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
DESCRIPTION:
The IDT71215 is a 245,760-bit Cache Tag StaticRAM,
organized 16K x 15 and designed to support the Pentium and
other Intel processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
usedasstatusbits. A12-bitcomparatorison-chiptoallowfast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
PIN DESCRIPTIONS
CLK
System Clock
Input
Input
Input
Input
Output
I/O
A0 – A13
CS1, CS2
WET
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BRDYH
BRDYOE
BRDYIN
BRDY
BRDY Force High
BRDY Output Enable
Additional BRDY Input
Burst Ready
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
WES
OET
TAG0 – TAG11 Tag Data Input/Outputs
VLDOUT / S1OUT Valid Bit / S1 Bit Output
DTYOUT / S2OUT Dirty Bit / S2 Bit Output
OES
Output
Output
Output
Output
Pwr
RESET
PWRDN
SFUNC
W/R
Powerdown Mode Control Pin
Status Bit Function Control Pin
Write/Read Input from Processor
WTOUT / S3OUT
MATCH
VCC
Write Through Bit / S3 Bit Output
Match
+5V Power
Output Buffer Power
Ground
VLDIN / S1IN Valid Bit / S1 Bit Input
DTYIN / S2IN Dirty Bit / S2 Bit Input
VCCQ
VSS
QPwr
Gnd
WTIN / S3IN
Write Through Bit / S3 Bit Input
3075 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
DSC-3075/3
14.3
1
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
80
V
V
V
V
SS
SS
SS
SS
V
V
V
SS
SS
SS
1
TAG8
DTYIN / S2IN
TAG7
WTIN / S3IN
TAG6
A0
A1
A2
VLDOUT / S1OUT
V
V
CCQ
SS
V
V
CC
SS
BRDY
PN80-1
MATCH
A3
A4
A5
A6
A7
V
V
SS
CCQ
WTOUT / S3OUT
TAG5
TAG4
V
SS
SS
SS
SS
NC
V
V
V
V
V
V
SS
SS
SS
3075 drw 01
TQFP
TOP VIEW
14.3
2
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
ADDR (0:13)
0
1
16K x 12
MEMORY
16K x 3
MEMORY
Reg
TAG BITS
STATUS BITS
CS1
CS2
Data in
Register
Data in
Register
Reg
SA
VLD/S1IN
DTY/S2IN
WT/S3IN
SA
TAG (0:11)
OET
VLD/S1OUT
DTY/S2OUT
WT/S3OUT
WRITE
(pos) PULSE
GENERATOR
WET
Reg
WES
CLK
OES
RESET
(neg) PULSE
GENERATOR
COMPARE
RESET
PWRDN
SFUNC
MATCH
BRDY
W/R
BRDYH
BRDYIN
Reg
BRDYOE
14.3
3
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES
CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS(1, 2)
CS2
CLK
TAG VLDOUT DTYOUT WTOUT MATCH
OPERATION POWER
BRDY
CS1
RESET PWRDN
WET WES BRDYOE
CHIP SELECT FUNCTION
H
X
L
X
L
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
–
Deselected
Deselected
Selected
Active
Active
Active
H
–
–
RESET FUNCTION
L
H
H
X
L
L
L
L
L
L
L
H
H
H
H
H
H
↑
↑
↑
↑
↑
↑
H
H
H
H
L
H
H
H
H
X
L
L
H
X
X
X
X
Hi-Z
Hi-Z
L(3)
L(3)
L(3)
L(3)
Hi-Z
Hi-Z
–
L(3)
L(3)
Hi-Z
Hi-Z
–
L(3)
L(3)
Hi-Z
Hi-Z
–
H
Reset Status Active
L
Hi-Z Reset Status Active
Hi-Z Reset Status Active
Hi-Z Reset Status Active
H
X
X
X
Hi-Z Hi-Z
Hi-Z Hi-Z
X
X
–
–
–
–
–
–
Not Allowed
Not Allowed
–
–
X
–
–
–
POWER-DOWN FUNCTION
X
X
X
L
X
H
H
X
Hi-Z Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z Power-down Standby
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
3075 tbl 02
2. OET, OES, W/R, BRDYH, BRDYIN and SFUNC are "X" for this table.
3. OES is LOW.
READ AND WRITE FUNCTIONS(1, 2)
CLK W/
TAG VLDIN DTYIN WTIN VLDOUT DTYOUT WTOUT
MATCH
OPERATION
OET OES WET WES
R
READ FUNCTION
L
X
H
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DOUT
–
–
DOUT
–
–
DOUT
–
DOUT
DOUT
DOUT
DOUT
Read TAG I/O
Read Status Bits
TAG I/O Disable
Status Disabled
X
H
Hi-Z
–
Hi-Z
Hi-Z
Hi-Z
WRITE FUNCTION
H
L
X
X
L
L
L
X
X
L
L
↑
↑
↑
↑
X
X
X
X
DIN
–
–
–
–
DOUT
–
DOUT
–
DOUT
–
L
–
L
L
Write TAG I/O
Not Allowed
–
–
–
(3)
(3)
(3)
X
X
X
–
DIN
DIN
DIN
DIN
DIN
DIN
DOUT
DOUT
DOUT
Write Status Bits
Write Status Bits
X
H
–
Hi-Z
Hi-Z
Hi-Z
NOTES:
3075 tbl 03
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. BRDYOE, BRDYH, BRDYIN and SFUNC are "X" for this table.
3. DOUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation.
14.3
4
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES (CONT.)
MATCH FUNCTION(1, 2, 3)
CS2 SFUNC
TAG VLD(4) DTY(4) WT(4) MATCH
OPERATION
Deselected
CS1
H
X
OET WET WES
X
L
X
X
X
X
X
X
L
X
X
X
L
X
X
X
H
L
X
X
X
X
X
L
Hi-Z
Hi-Z
–
–
–
–
–
–
–
Hi-Z
Hi-Z
DOUT
L
Deselected
L
H
H
H
H
H
H
H
–
–
–
Selected
L
DOUT
DIN
–
–
–
Read Tag I/O
L
H
X
H
H
H
–
–
–
L
Write Tag I/O
L
X
H
H
H
–
DIN
L
DIN
–
DIN
–
L
Write Status Bits
Invalid Data - Dedicated Status Bits
Match - Dedicated Status Bits
L
H
H
H
TAGIN
TAGIN
TAGIN
L
L
L
H
X
–
–
M
L
H
–
–
M
Match - Generic Status Bits
NOTES:
3075 tbl 04
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.
3. PWRDN and RESET are HIGH for this table. W/R, BRDYH, BRDYOE, BRDYIN, OES, and CLK are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
FUNCTION(1, 2, 3, 5)
BRDY
BRDYH W/ SFUNC VLD(4) DTY(4) WT(4) TAG MATCH
OPERATION
BRDY Disabled
Ext BRDY Input (7)
Read TAG
BRDYOE BRDYIN(6) OET WET WES
R
BRDY
Hi-Z
L
H
L
L
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
X
L
X
X
X
X
L
X
X
X
X
X
H
X
X
L
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
L
X
X
–
–
X
X
–
–
–
X
L
H
H
H
H
H
H
H
H
H
H
X
–
X
DOUT
DIN
–
H
X
X
X
X
X
H
H
H
H
X
–
X
L
H
Write TAG
X
X
X
X
H
H
H
H
DIN
X
DIN
–
DIN
X
L
H
Write Status
Force BRDY HIGH
Invalid TAG
Write Through
Compare
X
X
X
H
H
H
H
–
X
L
H
L
–
X
–
H
L
X
–
H
L
–
X
M
M
M
M
H
L
H
H
H
X
–
TAGIN
TAGIN
TAGIN
TAGIN
M
L
L
–
X
M
Compare
L
X
X
L
–
X
M
Compare
L
L
H
–
X
M
Compare
NOTES:
3075 tbl 05
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.
3. PWRDN and RESET are HIGH for this table. CLK and OES are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
5. CS1 is LOW, CS2 is HIGH for this table.
6. BRDYIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.
7. BRDYIN will be a factor in determining the BRDY output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case, BRDY will
be LOW(Valid).
14.3
5
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Rating
Value
Unit
Symbol
Parameter
Min. Typ.
Max. Unit
VTERM Terminal Voltage with Respect –0.5 to +7.0(2)
to GND
V
VCC
Supply Voltage
4.75
4.75
3.0
0
5.0
5.0
3.3
0
5.25
5.25
3.6
0
V
V
V
V
V
VCCQ
VCCQ
VSS
5V Output Buffers
3.3V Output Buffers
Supply Ground
TA
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
–0 to +70
–65 to +135
–65 to +150
1.7
°C
°C
°C
W
TBIAS
TSTG
PT
VIH
Input High Voltage
2.2
3.0 VCC+0.3
VIHQ
VIL
I/O High Voltage
Input Low Voltage
2.2
3.0 VCCQ+0.3
V
V
IOUT
DC Output Current
20
mA
–0.5(1)
—
0.8
NOTES:
3075 tbl 08
NOTE:
3075 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
2. VIN should not exceed Vcc+0.5V. All pins should not exceed 7.0V.
VCCQ should never exceed VCC, and VCC should never exceed
VCCQ + 4.0V.
1. VIL (min.) = –1.5V for pulse width of less than 10ns, once per cycle.
CAPACITANCE
(TA = +25°C, f = 1.0 MHz)
Symbol
CIN
Parameter(1)
Condition
VIN = 0V
VI/O = 0V
Max. Unit
Input Capacitance
5
7
pF
pF
CTAG
TAG Input/Output
Capacitance
COUT
Output Capacitance
VOUT = 0V
7
pF
NOTE:
3075 tbl 07
1. This parameter is determined by device characterization but is not produc-
tion tested.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V)
Symbol
|ILI|
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min.
—
Max.
Unit
µA
VCC = Max., VIN = 0V to VCC
5
5
|ILO|
CS1 ≥ VIH, CS2 ≤ VIL, OE ≥ VIH, VCC = Max.
—
µA
VOUT = 0V to VCCQ, VCCQ = Max.
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 4mA, VCC = Min.
IOH = –4mA, VCC = Min.
—
0.4
—
V
2.4
V
3075 tbl 09
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 2) (VCC = 5.0V ± 5%)
71215S8
71215S9
71215S10
71215S12
Symbol Parameter
Test Condition
Com'l. Mil. Com'l.
Mil. Com'l. Mil. Com'l. Mil. Unit
ICC
Operating Power
Supply Current
PWRDN ≥ VIH
Outputs Open, VCC = Max., f = fMAX
330
30
—
—
—
300
30
—
—
—
290
30
—
—
—
280
30
—
—
—
mA
mA
(3)
ISB
Standby Power
Supply Current
PWRDN ≤ VIL, VIN ≥ VIH or ≤ VIL
VCC = Max., f = fMAX
(3)
(4)
ISB1
Full Standby Power PWRDN ≤ VIL, VIN ≥ VHC or ≤ VLC
Supply Current
25
25
25
25
mA
VCC = Max., f = 0(3)
NOTES:
3075 tbl 10
1. All values are maximum guaranteed values.
2. CS1 ≤ VIL, CS2 ≥ VIH.
3. fMAX =1/tCYC (all address inputs are cycling at fMAX). f = 0 means no address input lines are changing.
4. VHC = VCC - 0.2V, VLC = 0.2V
14.3
6
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
IDT71215S10 IDT71215S12
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
Symbol Parameter
Read
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tAAT
Address Access Time Tag Bits
—
—
1
10
8
—
—
1
11
9
—
—
1
12
10
—
6
—
—
1
14
12
—
7
ns
ns
tACST
Chip Select Access Time Tag Bits
Chip Select to Tag and Status Bits in Low-Z
Chip Select to Tag and Status Bits in High-Z
Output Enable to Tag Bits Valid
(1)
tCLZ
tCHZ
tOET
—
5
—
6
ns
(1)
1
1
1
1
ns
—
0
5
—
0
6
—
0
6
—
0
7
ns
(1)
(1)
tOTLZ
Output Enable to Tag Bits in Low-Z
Output Enable to Tag Bits in High-Z
Tag Bit Hold from Address Change
Output Enable to Status Bits Valid
Output Enable to Status Bits in Low-Z
Output Enable to Status Bits in High-Z
Address Access Time Status Bits
—
5
—
6
—
6
—
7
ns
tOTHZ
tTOH
tOES
1
1
1
1
ns
2
—
5
2
—
6
2
—
6
2
—
7
ns
—
0
—
0
—
0
—
0
ns
(1)
tOSLZ
tOSHZ
tAAS
—
5
—
6
—
6
—
7
ns
(1)
1
1
1
1
ns
—
—
2
8
—
—
2
9
—
—
2
10
8
—
—
2
12
10
—
ns
tACSS
tSOH
Chip Select Access Time Status Bits
Status Bit Hold from Address Change
6
7
ns
—
—
—
ns
NOTE:
3075 tbl 11
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
(1)
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
IDT71215S10 IDT71215S12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Reset and Power Down Cycles
tSR
RESET Set-up Time
4
—
4
—
4
—
4
—
ns
tHR
RESET Hold Time
1
—
50
—
1
—
60
1
—
60
1
—
70
ns
ns
ns
ns
ns
tSRST
tSHRS
tRSMI
tRSMV
Status Bit Reset Time
—
2
—
2
—
2
—
2
Status Bit Hold from RESET LOW
RESET LOW to MATCH and BRDY Invalid
RESET HIGH to MATCH and BRDY Valid
—
—
—
—
—
9
110
—
—
10
120
—
—
10
120
—
—
12
130
(2)
tRSHZ
RESET LOW to TAG High-Z
—
—
30
1
9
—
—
30
1
10
100
—
—
—
30
1
10
100
—
—
—
30
1
12
110
—
ns
ns
(2)
tRSLZ
RESET HIGH to TAG Low-Z
90
—
—
—
50
—
tPDSR
tRHPL
tRHWL
PWRDN Set-up to RESET LOW
RESET HIGH to PWDRN LOW
RESET HIGH to WET and WES LOW
PWRDN LOW to Low Power Mode
PWRDN HIGH to Active Power Mode
ns
—
—
—
CLK
ns
90
—
0
95
—
0
—
95
—
0
—
105
—
0
—
(2)
tPD
50
—
50
—
50
—
ns
(2)
tPU
ns
(2)
tPDHZ
PWRDN LOW to Outputs in High-Z
—
9
—
10
—
10
—
12
ns
(2)
tPDLZ
tPUV
PWRDN HIGH to Outputs in Low-Z
PWRDN HIGH to Outputs Valid
0
—
5
—
50
—
—
0
—
5
—
50
—
—
0
—
5
—
50
—
—
0
—
5
—
50
—
—
ns
ns
(2)
tWHPL
tPUWL
NOTES:
WET and WES HIGH to PWRDN LOW
PWRDN HIGH to WET and WES Active
ns
50
50
50
50
ns
3075 tbl 12
1. Power-down mode is intended to be used during extended time periods of device inactivity.
2. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
14.3
7
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
(1)
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8 IDT71215S9 IDT71215S10 IDT71215S12
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Symbol
Parameter
Write Cycle and Clock Parameters
tCYC
Clock Cycle Time
15
4.5
4.5
3
—
—
—
—
—
—
—
6
15
4.5
4.5
3
—
—
—
—
—
—
—
7
15
4.5
4.5
3
—
—
—
—
—
—
—
7
16.6
5
—
—
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2, 3)
tCH
Clock Pulse HIGH
(2, 3)
tCL
Clock Pulse LOW
5
tS
WET, WES, Chip Select, and Input Data Set-up Time
WET, WES, Chip Select, and Input Data Hold Time
Address Set-up Time
3
tH
1
1
1
1
tSA
tHA
tWMI
tCKLZ(
3
3
3
3
Address Hold Time
1
1
1
1
CLK HIGH Write to MATCH and BRDY Invalid
CLK HIGH Read to Outputs in Low-Z
CLK HIGH Read to Tag Bits Valid
CLK HIGH Write to Status Outputs Valid
Status Output Hold from CLK HIGH Write
WET and WES HIGH to PWRDN LOW
PWRDN HIGH to WET and WES Active
—
1.5
—
—
0
—
1.5
—
—
0
—
1.5
—
—
0
—
1.5
—
—
0
3)
—
9
—
10
9
—
10
9
—
12
10
—
—
—
(4)
tCTV
(4)
tCSV
tCSH
8
(3)
—
—
—
—
—
—
—
—
—
tWHPL
5
5
5
5
tPUWL
50
50
50
50
ns
NOTES:
3075 tbl 14
1. All Write cycles are synchronous and referenced from rising CLK.
2. This parameter is measured as a HIGH time above 2.0V and a LOW time below 0.8V.
3. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
4. Addresses are stable prior to CLK transition HIGH.
14.3
8
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
IDT71215S10 IDT71215S12
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% OR 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
Symbol
Parameter
Cycles
Min.
Max. Min.
Max.
Min.
Max.
Min. Max.
Unit
MATCH and
BRDY
tADM
tDAM
tCSM
Address to MATCH Valid
—
—
—
1
8
8
—
—
—
1
9
9
—
—
—
1
10
—
—
—
1
12
12
12
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Input to MATCH Valid
10
10
—
6
Chip Select to MATCH Valid
8
9
(1)
tCMLZ
tCMHZ
Chip Select to MATCH in Low-Z
Chip Select to MATCH in High-Z
MATCH Valid Hold from Address
MATCH Valid Hold from Data
BRDY Valid Hold from Address
BRDY Valid Hold from Data
—
5
—
6
(1)
1
1
1
1
tMHA
tMHD
tBHA
tBHD
tADB
tDAB
tCSB
tOEBV
2
—
—
—
—
9
2
—
—
—
—
10
10
10
6
2
—
—
—
—
11
11
11
7
2
—
—
—
—
13
13
13
8
2
2
2
2
2
2
2
2
2
2
2
2
Address to BRDY Valid
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
Data Input to BRDY Valid
9
Chip Select LOW to BRDY Valid
BRDYOE LOW to BRDY Valid
BRDYOE LOW to BRDY in Low-Z
BRDYOE HIGH to BRDY in High-Z
BRDYH HIGH to Force BRDY HIGH
BRDYH LOW to BRDY Valid
9
6
(1)
tOBLZ
tOBHZ
—
5
—
6
—
6
—
7
(1)
1
1
1
1
tBYFH
tBYHV
tSB
—
—
4
5
—
—
4
5
—
—
4
5
—
—
4
6
5
5
5
6
BRDYIN Set-up Time
—
—
6
—
—
6
—
—
7
—
—
8
tHB
BRDYIN Hold Time
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
tBIBL
tBIBV
tOEMI
tOEMV
CLK HIGH BRDYIN LOW to BRDY LOW
CLK HIGH BRDYIN HIGH to BRDY Valid
OET LOW to MATCH and BRDY Invalid
OET HIGH to MATCH and BRDY Valid
W/R HIGH to BRDY HIGH
6
6
7
8
6
7
7
8
7
8
8
10
8
(2)
tWRBH
tWRBV
tWMI
6
7
7
(2)
W/R LOW to BRDY Valid
6
7
7
8
CLK HIGH Write to MATCH and BRDY Invalid
CLK HIGH Read to MATCH and BRDY Valid
7
7
7
8
(3)
tWMV
NOTES:
8
9
10
12
ns
3075 tbl 15
1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
2. These parameters only apply when SFUNC is LOW and the internal WT bit is HIGH.
3. tADM, tDAM, tCSM and tADB, tDAB, tCSB must also be satisfied.
14.3
9
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
See Figs. 1, 2, 3, & 4
3075 tbl 16
AC TEST LOADS
VCCQ
VCCQ
Ω
893
Ω
893
Outputs
Tag I/O
347Ω
347 Ω
30pF *
50pF *
3075 drw 03
3075 drw 04
Figure 1. AC Test Load
Figure 2. Tag I/O AC Test Load
* Including scope and jig capacitance
6
V
CCQ
5
4
Ω
893
Tag I/O
and
Outputs
3
2
1
∆t
(Typical, ns)
347Ω
5pF*
3075 drw 05
Figure 3. AC Test Load
(for tHZ and tLZ parameters )
20 30 50
80 100
∆ Capacitance (pF)
* Including scope and jig capacitance
3075 drw 06
Figure 4. Lumped Capacitance Load, Typical Derating
14.3
10
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF WRITE AND READ CYCLES
14.3
11
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF MATCH AND
FUNCTIONS
BRDY
14.3
12
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF
FUNCTION
RESET
CLK
tSR
tHR
RESET
tPDSR
PWRDN
tSRST
tSHRS
VLDOUT
DTYOUT
WTOUT
tRHWL
tRSMV
tS
WES
WET
tRSMI
BRDY
VALID
VALID
MATCH
tRSLZ(1)
tRSHZ(1)
TAG (0:11)
3075 drw 09
NOTE:
1. Transition is measured ±200mV from steady state.
CLOCK TIMING WAVEFORM
tCH
tCYC
tCL
0.8V
0.8V
CLK
2.0V
2.0V
3075 drw 10
TIMING WAVEFORMS OF
AND W/ SIGNAL
R
BRDY
Applies when SFUNC is LOW, and the internal WT bit is HIGH
CLK
tSB
tHB
BRDYIN
tBIBL
tBIBV
W/R
tWRBH
tWRBV
BRDY
BRDY Valid
BRDY Valid
3075 drw 11
14.3
13
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF
FUNCTION
OES
OES
tOES
tOSHZ(1)
tOSLZ(1)
VLDOUT
DTYOUT
WTOUT
Valid Output
Valid Output
3075 drw 12
NOTE:
1. Transition is measured ±200mV from steady state.
TIMING WAVEFORMS OF POWER DOWN FUNCTION
PWRDN
tWHPL
CLK
tPUWL
tRHPL
RESET
tS
tS
WET, WES
tPDHZ(1)
tPUV
TAG (0:11)
Valid TAG out
tPDLZ(1)
VLDOUT
Valid Status out
DTYOUT
WTOUT
BRDY
BRDY Valid
MATCH
MATCH Valid
tPD
tPU
ICC
3075 drw 13
ISB
NOTE:
1. Transition is measured ±200mV from steady state.
ORDERING INFORMATION
IDT
71215
S
XX
PF
Device Type
Power
Speed
Package
PF
Plastic Thin Quad Flatpack (PN80-1)
Speed in nanoseconds
8
9
10
12
3075 drw 14
14.3
14
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