IDT71215S8PF9 [IDT]
Cache Tag SRAM, 16KX15, 8ns, BICMOS, PQFP80, PLASTIC, TQFP-80;
| 型号： | IDT71215S8PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache Tag SRAM, 16KX15, 8ns, BICMOS, PQFP80, PLASTIC, TQFP-80 信息通信管理 静态存储器 |
| 文件： | 总16页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BiCMOS Static RAM
240K (16K x 15-Bit)
Cache-Tag RAM
IDT71215
for the Pentium™ Processor
stored TAG bits and the current Tag input data. An active HIGH
MATCH output is generated when these two groups of data are the
same for a given address. This high-speed MATCH signal, with tADM
as fast as 8ns, provides the fastest possible enabling of secondary
cache accesses.
Features
◆
16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
Match output uses Valid bit to qualify MATCH output
High-Speed Address-to-Match comparison times
◆
The three separate I/O status bits (VLD, DTY, and WT) can be
configured for either dedicated or generic functionality, depending on
the SFUNC input pin. With SFUNC LOW, the status bits are defined
and used internally by the device, allowing easier determination of the
validity and use of the given Tag data. SFUNC HIGH releases the
defined internal status bit usage and control, allowing the user to
configure the status bit information to fit his system needs. A synchro-
nous RESET pin, when held LOW at a rising clock edge, will reset all
status bits in the array for easy invalidation of all Tag addresses.
The IDT71215 also provides the option for Burst Ready (BRDY)
generation within the cache tag itself, based upon MATCH, VLD bit,
WT bit, and external inputs provided by the user. This can significantly
simplify cache controller logic and minimize cache decision time.
Match and Read operations are both asynchronous in order to
provide the fastest access times possible, while Write operations are
synchronous for ease of system timing.
The IDT71215 uses a 5V power supply on VCC with separate VCCQ
pins provided for the outputs to offer compliance with both 5V TTL and
3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby
mode to reduce power consumption by 90%, providing significant
system power savings.
The IDT71215 is fabricated using IDT’s high-performance, high-
reliability BiCMOS technology and is offered in a space-saving 80-pin
Thin Plastic Quad Flat Pack (TQFP) package.
◆
– 8/9/10/12ns over commercial temperature range
BRDY circuitry included inside the Cache-Tag for
highest speed operation
◆
◆
Asynchronous Read/Match operation with Synchronous
Write and Reset operation
◆
Separate WE for the TAG bits and the Status bits
◆
Separate OE for the TAG bits, the Status bits, and BRDY
◆
Synchronous RESET pin for invalidation of all Tag
entries
◆
Dual Chip selects for easy depth expansion with no
performance degredation
I/O pins both 5V TTL and 3.3V LVTTL compatible with
◆
VCCQ pins
◆
PWRDN pin to place device in low-power mode
Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP).
◆
Description
The IDT71215 is a 245,760-bit Cache Tag Static RAM, orga-
nized 16K x 15 and designed to support the Pentium and other Intel
processors at bus speeds up to 66MHz. There are twelve common
I/O TAG bits, with the remaining three bits used as status bits. A 12-
bit comparator is on-chip to allow fast comparison of the twelve
Pin Descriptions
0
13
A – A
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
CLK
System Clock
Input
Input
Input
Input
Output
I/O
Chip Selects
BRDYH
CS1, CS2
WET
BRDY Force High
BRDY Output Enable
Additional BRDY Input
Burst Ready
Write Enable – Tag Bits
Write Enable – Status Bits
Output Enable – Tag Bits
Output Enable – Status Bits
Status Bit Reset
BRDYOE
BRDYIN
BRDY
0
WES
OET
11
TAG – TAG
Tag Data Input/Outputs
OES
OUT 1OUT
VLD /S
1
Valid Bit/S Bit Output
Output
Output
RESET
PWRDN
SFUNC
W/R
OUT 2OUT
DTY /S
2
Powerdown Mode Control Pin
Status Bit Function Control Pin
Dirty Bit/S Bit Output
OUT 3OUT
WT /S
3
Write Through Bit/S Bit Output Output
Write/Read Input from Processor Input
MATCH
Match
Output
Pwr
IN 1IN
1
CC
V
VLD /S
Valid Bit/S Bit Input
Input
Input
Input
+5V Power
Output Buffer Power
Ground
IN 2IN
2
CCQ
V
DTY /S
Dirty Bit/S Bit Input
QPwr
Gnd
IN 3IN
3
SS
V
WT /S
Write Through Bit/S Bit Input
3075 tbl 01
Pentium is a trademark of Intel Corporation.
OCTOBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC-3075/04
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Pin Configuration
80
V
SS
V
SS
V
SS
V
SS
V
V
V
SS
SS
SS
1
TAG8
DTYIN / S2IN
TAG7
WTIN / S3IN
TAG6
A0
A1
A2
VLDOUT / S1OUT
V
CCQ
SS
V
BRDY
V
CC
SS
PN80-1
V
MATCH
A3
A4
A5
A6
A7
V
SS
V
CCQ
WTOUT / S3OUT
TAG5
TAG4
V
SS
SS
SS
SS
NC
V
V
V
V
SS
V
SS
V
SS
3075 drw 01
TQFP
Top View
6.42
2
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Functional Block Diagram
ADDR (0:13)
0
1
16K x 12
MEMORY
TAG BITS
16K x 3
Reg
MEMORY
STATUS
BITS
CS1
CS2
DataIN
Register
DataIN
Register
Reg
SA
SA
VLD/S1IN
DTY/S2IN
WT/S3IN
TAG (0:11)
OET
VLD/S1OUT
DTY/S2OUT
WT/S3OUT
WRITE
(pos) PULSE
GENERATOR
WET
WES
CLK
Reg
OES
RESET
(neg) PULSE
GENERATOR
COMPARE
RESET
PWRDN
SFUNC
MATCH
W/R
BRDYH
BRDY
BRDYIN
Reg
BRDYOE
3075 drw 02
6.42
3
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Truth Table Chip Select, Reset, and Power-Down Functions(1,2)
OUT
TAG VLD
OUT
DTY
OUT
WT
CS1 CS2 RESET PWRDN CLK WET WES BRDYOE
MATCH BRDY OPERATION POWER
CHIP SELECT FUNCTION
H
X
L
X
L
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Deselected
Deselected
Selected
Active
Active
Active
Hi-Z
—
Hi-Z
—
H
RESET FUNCTION
(3)
(3)
(3)
(3)
L
L
H
H
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
X
L
L
H
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
L
L
L
L
H
Reset Status
Reset Status
Reset Status
Reset Status
Not Allowed
Not Allowed
Active
Active
Active
Active
—
↑
↑
↑
↑
↑
↑
(3)
(3)
(3)
(3)
L
L
L
L
Hi-Z
Hi-Z
Hi-Z
—
H
X
X
X
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
X
X
X
—
—
—
—
—
—
—
POWER-DOWN FUNCTION
X
X
X
L
X
H
H
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Power-down Standby
3075 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. OET, OES, W/R, BRDYH, BRDYIN and SFUNC are "X" for this table.
3. OESisLOW.
Truth Table Read and Write Functions(1,2)
IN
IN
DTY
IN
WT
OUT
VLD
OUT
DTY
OUT
WT
OET OES WET
WES CLK W/R
TAG VLD
MATCH
OPERATION
READ FUNCTION
OUT
OUT
L
X
H
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
Read TAG I/O
Read Status Bits
TAG I/O Disable
Status Disabled
OUT
D
OUT
D
OUT
D
OUT
D
—
Hi-Z
—
OUT
D
X
H
—
—
—
OUT
D
Hi-Z
Hi-Z
Hi-Z
WRITE FUNCTION
IN
OUT
OUT
OUT
H
L
X
X
L
L
L
X
X
L
L
X
X
X
X
D
—
—
—
—
—
—
D
D
D
L
—
L
Write TAG I/O
Not Allowed
↑
↑
↑
↑
—
—
—
—
—
—
OUT(3)
OUT(3)
OUT(3)
D
IN
D
IN
D
IN
D
X
X
X
X
Write Status Bits
D
D
IN
D
IN
D
IN
D
H
Hi-Z
Hi-Z
Hi-Z
L
Write Status Bits
3075 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. BRDYOE, BRDYH, BRDYIN and SFUNC are "X" for this table.
3. DOUT inthis caseis thesameas DIN;thatis,theinputdatais writtenthroughtotheoutputs duringthewriteoperation.
6.42
4
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Truth Table Match Function(1,2,3)
(4)
(4)
(4)
CS1
H
X
L
CS2 SFUNC OET
WET WES
TAG
Hi-Z
Hi-Z
—
VLD
DTY
WT
MATCH
Hi-Z
OPERATION
Deselected
X
L
X
X
X
X
X
X
L
X
X
X
L
X
X
X
H
L
X
X
X
X
X
L
—
—
—
—
—
—
—
—
—
—
—
—
Hi-Z
Deselected
OUT
D
H
H
H
H
H
H
H
—
Selected
OUT
D
L
—
L
L
Read Tag I/O
IN
D
L
H
X
H
H
H
—
Write Tag I/O
IN
IN
IN
L
X
H
H
H
—
D
D
D
L
Write Status Bits
IN
TAG
L
H
H
H
L
H
X
—
—
—
—
—
—
L
Invalid Data — Dedicated Status Bits
Match — Dedicated Status Bits
IN
TAG
L
L
M
M
IN
TAG
L
H
Match — Generic Status Bits
3075 tbl 04
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M=HIGHifTAGIN equals thememorycontents atthataddress;M=LOWifTAGIN does notequalthememorycontents atthataddress.
3. PWRDN and RESET are HIGH for this table. W/R, BRDYH, BRDYOE, BRDYIN, OES, and CLK are "X".
4. ThiscolumnrepresentsthestoredmemorycelldataforthegivenStatusbitattheselectedaddress.
Truth Table BRDY Function(1,2,3,5)
(4)
(4)
(4)
BRDYOE BRDYIN(6) OET
WET WES BRDYH W/R SFUNC
VLD DTY WT
TAG MATCH BRDY
OPERATION
BRDY Disabled
Ext BRDY Input(7)
Read TAG
H
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
X
L
X
X
X
X
L
X
X
X
X
X
H
X
X
L
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
L
X
X
X
X
—
—
—
—
X
X
X
X
—
—
X
L
Hi-Z
L
—
OUT
D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
M
IN
D
X
X
X
X
X
H
H
H
H
L
Write TAG
IN
D
IN
D
IN
D
X
X
X
X
H
H
H
H
—
—
—
—
L
Write Status
Force BRDY HIGH
Invalid TAG
Write Through
Compare
X
X
X
H
H
H
H
X
L
—
—
—
—
—
—
—
X
X
H
L
X
L
L
X
H
H
H
X
X
M
M
M
M
IN
TAG
L
IN
L
L
X
X
X
TAG
TAG
TAG
Compare
M
IN
IN
L
X
X
L
Compare
M
L
H
Compare
M
3075 tbl 05
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M=HIGHifTAGIN equals thememorycontents atthataddress;M=LOWifTAGIN does notequalthememorycontents atthataddress.
3. PWRDN and RESET are HIGH for this table. CLK and OES are "X".
4. ThiscolumnrepresentsthestoredmemorycelldataforthegivenStatusbitattheselectedaddress.
5. CS1 is LOW, CS2is HIGHforthis table.
6. BRDYIN is a synchronous input;thus the inputs notedinthe table mustbe appliedduringa risingCLKedge.
7. BRDYIN will be a factor in determining the BRDY output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case,BRDY will be LOW(Valid).
6.42
5
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Rating
Value
Unit
V
Symbol
Parameter
Min.
4.75
4.75
3.0
Typ.
5.0
5.0
3.3
0
Max.
5.25
5.25
3.6
Unit
V
Terminal Voltage with Respect to GND –0.5 to + 7.0(2)
TERM
V
VCC
Supply Voltage
A
T
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
0 to +70
–65 to +135
–65 to +150
1.7
°C
°C
°C
W
CCQ
V
5V Output Buffers
3.3V Output Buffers
Supply Ground
V
BIAS
T
CCQ
V
V
STG
T
VSS
0
0
V
T
P
IH
CC
V
Input High Voltage
I/O High Voltage
Input Low Voltage
2.2
3.0
3.0
—
V +0.3
V
OUT
I
DC Output Current
20
mA
IHQ
V
CCQ
2.2
V
+0.3
V
3075 tbl 08
NOTES:
–0.5(1)
0.8
V
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliabilty.
IL
V
3075 tbl 06
NOTE:
1. VIL (min.) = –1.5V for pulse width of less than 10ns, once per cycle.
2. VIN shouldnotexceedVcc+0.5V.Allpinsshouldnotexceed7.0V.VCCQshouldnever
exceed VCC, and VCC should never exceed VCCQ + 4.0V.
Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Condition
VIN = 0V
VI/O = 0V
VOUT = 0V
Max.
Unit
pF
Input Capacitance
5
7
7
CTAG
COUT
TAG Input/Ouput Capacitance
Output Capacitance
pF
pF
NOTE:
3075 tbl 07
1. Thisparameterisdeterminedbydevicecharacterizationbutisnotproductiontested.
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min.
Max.
Unit
|ILI|
VCC = Max., VIN = 0V to VCC
—
5
5
|ILO|
CS1 ≥ V , CS2 V ,
IH
V , V = Max.
≤ IL OE ≥ IH CC
—
µA
V
VOUT = 0V to VCCQ, VCCQ = Max.
OL
V
OL
I
CC
Output Low Voltage
Output High Voltage
= 4mA, V = Min.
—
0.4
—
VOH
IOH = –4mA, VCC = Min.
2.4
V
3075 tbl 09
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1,2) (VCC = 5.0V ± 5%)
71215S8
71215S9
71215S10
71215S12
Symbol
Parameter
Test Condition
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Unit
CC
I
Operating Power
Supply Current
IH
PWRDN ≥ V
330
30
—
300
30
—
290
30
—
280
30
—
mA
(3)
MAX
CC
Outputs Open, V = Max., f = f
SB
I
Standby Power
Supply Current
IL IN
IH
IL
PWRDN ≤ V , V ≥ V or ≤ V
—
—
—
—
—
—
—
—
mA
(3)
MAX
= Max., f = f
CC
V
(4)
LC
SB1
I
IL IN
HC
PWRDN ≤ V , V ≥ V or ≤ V
Full Standby Power
Supply Current
25
25
25
25
mA
(3)
CC
V
= Max., f = 0
3075 tbl 10
NOTES:
1. Allvaluesaremaximumguaranteedvalues.
2. CS1 ≤ VIL, CS2 ≥ VIH.
3. fMAX =1/tCYC (alladdress inputs are cyclingatfMAX). f=0means noaddress inputlines are changing.
4. VHC = VCC - 0.2V, VLC = 0.2V
6.42
6
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
AC Electrical Characteristics
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
IDT71215S10
IDT71215S12
Symbol
READ CYCLE
AAT
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
t
Address Access Time Tag Bits
—
—
1
10
8
—
—
1
11
9
—
—
1
12
10
—
6
—
—
1
14
12
—
7
ns
ns
ns
ns
ns
ns
Chip Select Access Time Tag Bits
ACST
t
(1)
Chip Select to Tag and Status Bits in Low-Z
Chip Select to Tag and Status Bits in High-Z
Output Enable to Tag Bits Valid
—
5
—
6
CLZ
t
(1)
1
1
1
1
CHZ
t
OET
t
—
0
5
—
0
6
—
0
6
—
0
7
(1)
OTLZ
Output Enable to Tag Bits in Low-Z
—
—
—
—
t
(1)
Output Enable to Tag Bits in High-Z
Tag Bit Hold from Address Change
Output Enable to Status Bits Valid
Output Enable to Status Bits in Low-Z
1
2
5
1
2
6
1
2
6
1
2
7
ns
ns
ns
ns
OTHZ
t
TOH
t
—
5
—
6
—
6
—
7
OES
t
—
0
—
0
—
0
—
0
(1)
(1)
—
—
—
—
OSLZ
t
Output Enable to Status Bits in High-Z
Address Access Time Status Bits
1
—
—
2
5
8
1
—
—
2
6
9
1
—
—
2
6
1
—
—
2
7
ns
ns
ns
OSHZ
t
AAS
t
10
8
12
10
—
ACSS
t
Chip Select Access Time Status Bits
Status Bit Hold from Address Change
6
7
SOH
t
—
—
—
ns
3075 tbl 11
NOTE:
1. This parameteris guaranteedwiththe ACLoad(Figure 3)bydevice characterization, butis notproductiontested.
6.42
7
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
AC Electrical Characteristics(1)
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
IDT71215S10
IDT71215S12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
RESET AND POWER DOWN CYCLES
4
—
—
50
—
9
4
—
—
60
4
1
—
—
60
4
—
—
70
ns
ns
ns
ns
ns
ns
SR
t
RESET Set-up Time
HR
t
1
1
1
RESET Hold Time
SRST
t
Status Bit Reset Time
Status Bit Hold from RESET LOW
—
2
—
2
—
2
—
2
SHRS
t
—
10
—
10
—
12
RSMI
t
—
—
—
—
—
—
—
—
RESET LOW to MATCH and BRDY Invalid
RESET HIGH to MATCH and BRDY Valid
RESET LOW to TAG High-Z
RSMV
t
110
120
120
130
(2)
—
9
—
10
—
10
—
12
ns
RSHZ
t
(2)
—
30
1
90
—
—
—
50
—
9
—
30
1
100
—
—
—
50
—
30
1
100
—
—
—
50
—
30
1
110
—
—
—
50
—
12
ns
ns
RSLZ
t
RESET HIGH to TAG Low-Z
PDSR
t
PWRDN Set-up to RESET LOW
RESET HIGH to PWDRN LOW
RESET HIGH to WET and WES LOW
PWRDN LOW to Low Power Mode
PWRDN HIGH to Active Power Mode
RHPL
CLK
ns
t
RHWL
90
—
0
95
—
0
95
—
0
105
—
0
t
(2)
ns
PD
t
(2)
—
10
—
10
ns
PU
t
(2)
—
—
—
—
ns
PDHZ
t
PWRDN LOW to Outputs in High-Z
PWRDN HIGH to Outputs in Low-Z
PWRDN HIGH to Outputs Valid
(2)
PDLZ
0
—
5
—
50
—
—
0
—
5
—
50
—
—
0
—
5
—
50
—
—
0
—
5
—
50
—
—
ns
ns
ns
t
PUV
t
(2)
WHPL
t
WET and WES HIGH to PWRDN LOW
PWRDN HIGH to WET and WES Active
PUWL
50
50
50
50
ns
t
3075 tbl 12
NOTES:
1. Power-downmodeis intendedtobeusedduringextendedtimeperiods ofdeviceinactivity.
2. This parameteris guaranteedwiththe ACLoad(Figure 3)bydevice characterization, butis notproductiontested.
6.42
8
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
AC Electrical Characteristics(1)
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
IDT71215S10
IDT71215S12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE AND CLOCK PARAMETERS
CYC
t
Clock Cycle Time
Clock Pulse HIGH
Clock Pulse LOW
15
—
—
15
—
—
15
—
—
16.6
5
—
—
ns
ns
(2, 3)
4.5
4.5
4.5
CH
t
(2, 3)
CL
t
4.5
3
—
—
—
—
—
6
4.5
3
—
—
—
—
—
7
4.5
3
—
—
—
—
—
7
5
3
—
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
t
WET, WES, Chip Select, and Input Data Set-up Time
WET, WES, Chip Select, and Input Data Hold Time
Address Set-up Time
H
t
1
1
1
1
SA
t
3
3
3
3
HA
t
Address Hold Time
1
1
1
1
WMI
t
CLK HIGH Write to MATCH and BRDY Invalid
CLK HIGH Read to Outputs in Low-Z
CLK HIGH Read to Tag Bits Valid
—
1.5
—
—
0
—
1.5
—
—
0
—
1.5
—
—
0
—
1.5
—
—
0
(3)
CKLZ
t
—
9
—
10
9
—
10
9
—
12
10
—
—
—
(4)
CTV
t
(4)
CSV
t
CLK HIGH Write to Status Outputs Valid
Status Output Hold from CLK HIGH Write
8
(3)
CSH
—
—
—
—
—
—
—
—
—
t
WHPL
t
5
5
5
5
WET and WES HIGH to PWRDN LOW
PWRDN HIGH to WET and WES Active
50
50
50
50
ns
PUWL
t
3075 tbl 14
NOTES:
1. AllWritecycles aresynchronous andreferencedfromrisingCLK.
2. This parameter is measured as a HIGH time above 2.0V and a LOW time below 0.8V.
3. This parameteris guaranteedwiththe ACLoad(Figure 3)bydevice characterization, butis notproductiontested.
4. Addresses arestablepriortoCLKtransitionHIGH.
6.42
9
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
AC Electrical Characteristics
(VCC = 5.0V ± 5%, VCCQ = 5.0V ± 5% or 3.3V ± 0.3V, TA = 0 to 70°C)
IDT71215S8
IDT71215S9
Min. Max.
IDT71215S10
IDT71215S12
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
MATCH AND BRDY CYCLES
ADM
t
Address to MATCH Valid
—
—
—
1
8
8
—
9
—
—
—
1
10
10
10
—
6
—
—
—
1
12
12
12
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DAM
t
Data Input to MATCH Valid
Chip Select to MATCH Valid
Chip Select to MATCH in Low-Z
Chip Select to MATCH in High-Z
MATCH Valid Hold from Address
MATCH Valid Hold from Data
BRDY Valid Hold from Address
—
—
1
9
9
CSM
t
8
(1)
(1)
CMLZ
t
—
5
—
6
CMHZ
t
1
1
1
1
MHA
t
2
—
—
—
—
9
2
—
—
—
—
10
10
10
6
2
—
—
—
—
11
11
11
7
2
—
—
—
—
13
13
13
8
MHD
t
2
2
2
2
2
2
2
2
BHA
t
2
2
2
2
BHD
t
BRDY Valid Hold from Data
Address to BRDY Valid
ADB
t
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
—
—
—
—
0
DAB
t
Data Input to BRDY Valid
Chip Select LOW to BRDY Valid
9
CSB
t
9
OEBV
t
6
BRDYOE LOW to BRDY Valid
BRDYOE LOW to BRDY in Low-Z
BRDYOE HIGH to BRDY in High-Z
BRDYH HIGH to Force BRDY HIGH
BRDYH LOW to BRDY Valid
(1)
OBLZ
t
—
5
—
6
—
6
—
7
(1)
1
1
1
1
OBHZ
t
BYFH
t
—
—
4
5
—
—
4
5
—
—
4
5
—
—
4
6
BYHV
t
5
5
5
6
SB
t
—
—
6
—
—
6
—
—
7
—
—
8
BRDYIN Set-up Time
HB
t
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
1.5
—
—
—
—
—
—
—
—
BRDYIN Hold Time
BIBL
t
CLK HIGH BRDYIN LOW to BRDY LOW
CLK HIGH BRDYIN HIGH to BRDY Valid
BIBV
t
6
6
7
8
OEMI
t
6
7
7
8
OET LOW to MATCH and BRDY Invalid
OET HIGH to MATCH and BRDY Valid
W/R HIGH to BRDY HIGH
7
8
8
10
8
OEMV
t
(2)
WRBH
t
6
7
7
(2)
WRBV
t
W/R LOW to BRDY Valid
6
7
7
8
WMI
t
CLK HIGH Write to MATCH and BRDY Invalid
CLK HIGH Read to MATCH and BRDY Valid
7
7
7
8
(3)
WM V
t
8
9
10
12
ns
3075 tbl 15
NOTES:
1. This parameteris guaranteedwiththe ACLoad(Figure 3)bydevice characterization, butis notproductiontested.
2. These parameters only apply when SFUNC is LOW and the internal WT bit is HIGH.
3. tADM,tDAM,tCSMand tADB,tDAB,tCSBmustalsobesatisfied.
6.42
10
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
See Figures 1, 2, 3, & 4
3075 tbl 16
AC Test Loads
VCCQ
VCCQ
Ω
Ω
893
893
Outputs
Tag I/O
347
Ω
Ω
347
30pF *
50pF *
3075 drw 03
3075 drw 04
* Including scope and jig capacitance
Figure 1. AC Test Load
Figure 2. Tag I/O AC Test Load
6
VCCQ
5
4
Ω
893
Tag I/O
and
Outputs
3
2
1
∆t
(Typical, ns)
Ω
347
5pF*
3075 drw 05
20 30 50
80 100
∆ Capacitance (pF)
3075 drw 06
* Including scope and jig capacitance
Figure 3. AC Test Load
(for tHZ and tLZ parameters )
Figure 4. Lumped Capacitance Load, Typical Derating
6.42
11
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Timing Waveforms of Write and Read Cycles
6.42
12
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Timing Waveforms of Match and BRDY Functions
6.42
13
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Timing Waveforms of RESET Function
CLK
tSR
tHR
RESET
tPDSR
PWRDN
tSRST
tSHRS
VLDOUT
DTYOUT
WTOUT
tRHWL
tRSMV
tS
WES
WET
tRSMI
BRDY
VALID
VALID
MATCH
tRSLZ(1)
tRSHZ(1)
TAG (0:11)
3075 drw 09
NOTE:
1. Transitionismeasured±200mVfromsteadystate.
Clock Timing Waveform
tCH
tCYC
tCL
0.8V
0.8V
CLK
2.0V
2.0V
3075 drw 10
Timing Waveforms of BRDY and W/R Signal
Applies when SFUNC is LOW, and the internal WT bit is HIGH
CLK
tSB
tHB
BRDYIN
tBIBL
tBIBV
W/R
tWRBH
tWRBV
BRDY
BRDY Valid
BRDY Valid
3075 drw 11
6.42
14
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Timing Waveforms of OES Function
OES
tOES
tOSHZ(1)
tOSLZ(1)
VLDOUT
DTYOUT
Valid Output
Valid Output
WTOUT
3075 drw 12
NOTE:
1. Transitionismeasured±200mVfromsteadystate.
Timing Waveforms of POWER DOWN Function
PWRDN
tWHPL
CLK
tPUWL
tRHPL
RESET
tS
tS
WET, WES
tPDHZ(1)
tPUV
TAG (0:11)
Valid TAG out
tPDLZ(1)
VLDOUT
Valid Status out
DTYOUT
WTOUT
BRDY
BRDY Valid
MATCH
MATCH Valid
tPD
tPU
ICC
3075 drw 13
ISB
NOTE:
1. Transitionismeasured±200mVfromsteadystate.
Ordering Information
IDT
71215
S
XX
PF
Device Type
Power
Speed
Package
PF
Plastic Thin Quad Flatpack (PN80-1)
Speed in nanoseconds
8
9
10
12
3075 drw 14
6.42
15
IDT71215BiCMOSStaticRAM
240K (16K x 15-Bit) Cache-Tag RAM for the Pentium™ Processor
Commercial Temperature Range
Datasheet Document History
10/19/99
Updatedtonewformat
Pg. 15
Added datasheet document history
CORPORATE HEADQUARTERS
2975 Stender Way
for SALES:
for Tech Support:
800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com
800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
16
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