IDT71256S120D [IDT]

CMOS STATIC RAM 256K (32K x 8-BIT); CMOS静态RAM 256K （ 32K ×8位）


型号：	IDT71256S120D
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CMOS STATIC RAM 256K (32K x 8-BIT) CMOS静态RAM 256K （ 32K ×8位）
文件：	总9页 (文件大小：82K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71256S

IDT71256L

CMOS STATIC RAM

256K (32K x 8-BIT)

Integrated Device Technology, Inc.

FEATURES:

• High-speed address/chip select time

DESCRIPTION:

— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)

— Commercial: 20/25/35/45ns (max.) Low Power only.

• Low-power operation

The IDT71256 is a 262,144-bit high-speed static RAM

organized as 32K x 8. It is fabricated using IDT’s high-

performance, high-reliability CMOS technology.

• Battery Backup operation — 2V data retention

• Produced with advanced high-performance CMOS

technology

• Input and output directly TTL-compatible

• Available in standard 28-pin (300 or 600 mil) ceramic

DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ

and 32-pin LCC

Address access times as fast as 20ns are available with

power consumption of only 350mW (typ.). The circuit also

offers a reduced power standby mode. When CSgoes HIGH,

the circuit will automatically go to, and remain in, a low-power

standbymodeaslongasCSremainsHIGH. Inthefullstandby

mode, the low-power device consumes less than 15µW,

typically. This capability provides significant system level

power and cooling savings. The low-power (L) version also

offers a battery backup data retention capability where the

circuit typically consumes only 5µW when operating off a 2V

battery.

• Military product compliant to MIL-STD-883, Class B

The lDT71256 is packaged in a 28-pin (300 or 600 mil)

ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600

mil) plastic DIP, and 32-pin LCC providing high board-level

packing densities.

TheIDT71256militaryRAMismanufacturedincompliance

with the latest revision of MIL-STD-883, Class B, making it

ideally suited to military temperature applications demanding

the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

V_CC

GND

262,144 BIT

MEMORY ARRAY

ADDRESS

DECODER

A14

I/O 0

I/O CONTROL

INPUT

DATA

CIRCUIT

I/O ₇

CONTROL

CIRCUIT

2946 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1996

1996 Integrated Device Technology, Inc.

DSC-2946/7

7.2

IDT71256 S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

TRUTH TABLE⁽¹⁾

A₁₄

A₁₂

A₇

A₆

A₅

A₄

A₃

A₂

A₁

V_CC

A₁₃

A₈

A₉

A₁₁

I/O

Function

Standby (ISB)

Standby (ISB1)

High-Z

VHC

D28-3

P28-1

P28-2

D28-1

SO28-5

High-Z Output Disabled

DOUT

DIN

Read Data

Write Data

A₁₀

A₀

I/O ₇

I/O ₆

I/O ₅

I/O ₄

I/O ₃

NOTE:

1. H = VIH, L = VIL, X = Don’t Care

2946 tbl 02

I/O ₀

I/O ₁

I/O ₂

GND

2946 drw 02

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

DIP/SOJ

TOP VIEW

Symbol

Rating

Com’l.

Mil.

Unit

VTERM

Terminal Voltage –0.5 to +7.0 –0.5 to +7.0

with Respect

to GND

Operating

Temperature

0 to +70

–55 to +125 °C

INDEX

TBIAS

TSTG

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

32 31 30

A₈

A₉

A₁₁

A₁₀

I/O

I/O₆

Storage

Temperature

A₀

I/O0

L32-1

Power Dissipation

1.0

IOUT

DC Output

Current

NOTE:

2946 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect reliability.

14 15 16 17 18 19 20

2946 drw 03

32-Pin LCC

TOP VIEW

PIN DESCRIPTIONS

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Name

Description

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

Max. Unit

A0–A14

I/O0–I/O7

Addresses

Data Input/Output

CIN

VIN = 0V

CI/O

VOUT = 0V

Chip Select

Write Enable

Output Enable

Ground

NOTE:

2946 tbl 04

1. This parameter is determined by device characterization, but is not

production tested.

GND

VCC

Power

2946 tbl 01

7.2

IDT71256S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Parameter

Min. Typ. Max. Unit

Grade

Military

Commercial

Temperature

–55°C to +125°C

0°C to +70°C

GND

VCC

Supply Voltage

4.5

5.0

5.5

5.0V ± 10%

GND

VIH

Supply Voltage

5.0V ± 10%

Input High Voltage

Input Low Voltage

2.2

—

6.0

0.8

2946 tbl 05

VIL

–0.5⁽¹⁾

NOTE:

2946 tbl 06

1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.

DC ELECTRICAL CHARACTERISTICS^{(1, 2)}

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)

71256S/L20

71256S/L25

71256S/L30

71256S/L35

Symbol

Parameter

Power Com’l. Mil. Com’l. Mil. Com’l. Mil.

Com’l. Mil.

Unit

ICC

Dynamic Operating Current

—

150

—

145

—

140

CS ≤ VIL, Outputs Open

(2)

VCC = Max., f = fMAX

135

—

115

—

130

—

125

105

—

120

ISB

Standby Power Supply

Current (TTL Level)

CS ≥ VIH, VCC = Max.,

—

(2)

Outputs Open, f = fMAX

ISB1

Full Standby Power Supply

Current (CMOS Level)

CS ≥ VHC, VCC = Max., f = 0

—

0.4

1.5

0.4

1.5

71256S/L45 71256S/L55

Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com'l. Mil.

71256S/L70 71256S/L85⁽³⁾71256S/L100⁽³⁾

Symbol

Parameter

Unit

ICC

Dynamic Operating Current

—

135

—

135

—

135

—

135

—

135

CS ≤ VIL, Outputs Open

(2)

VCC = Max., f = fMAX

100 115

—

115

—

115

—

115

—

115

ISB

Standby Power Supply

Current (TTL Level)

CS ≥ VIH, VCC = Max.,

—

(2)

Outputs Open, f = fMAX

ISB1

Full Standby Power Supply

Current (CMOS Level)

CS ≥ VHC, VCC = Max., f = 0

—

0.4

1.5

NOTES:

2946 tbl 07

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.

3. Also available: 120 and 150 ns military devices.

7.2

IDT71256 S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

1.5V

Input Timing Reference Levels

Output Reference Levels

AC Test Load

1.5V

See Figures 1 and 2

2946 tbl 08

480Ω

DATAOUT

255Ω

255

Ω

30pF*

5pF*

2946 drw 05

2946 drw 04

Figure 2. AC Test Load

Figure 1. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)

*Includes scope and jig capacitances

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V ± 10%

IDT71256S

Typ.

IDT71256L

Min. Typ. Max.

Symbol

Parameter

Test Condition

VCC = Max.,

VIN = GND to VCC

Min.

Max.

Unit

|ILI|

Input Leakage Current

MIL.

COM’L.

—

µA

|ILO|

VOL

Output Leakage Current VCC = Max., CS= VIH,

VOUT = GND to VCC

MIL.

COM’L.

—

µA

Output Low Voltage

IOL = 8mA, VCC = Min.

IOL = 10mA, VCC = Min.

IOH = –4mA, VCC = Min.

—

0.4

0.5

—

0.4

0.5

—

VOH

Output High Voltage

2.4

2946 tbl 09

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(L Version Only) VLC = 0.2V, VHC = VCC – 0.2V

Typ. ⁽¹⁾

VCC @

Max.

VCC @

Symbol

VDR

Parameter

Test Condition

Min.

2.0v

3.0V

2.0V

3.0V

Unit

VCC for Data Retention

Data Retention Current

—

2.0

—

ICCDR

MIL.

COM’L.

—

500

120

800

200

µA

tCDR

Chip Deselect to Data

Retention Time

CS ≥ VHC

—

(3)

(2)

Operation Recovery Time

tRC

—

NOTES:

1. TA = +25°C.

2946 tbl 10

2. tRC = Read Cycle Time.

3. This parameter is guaranteed, but not tested.

7.2

IDT71256S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOW VCC DATA RETENTION WAVEFORM

DATA

RETENTION

MODE

VCC

4.5V

VDR≥2V

tCDR

VIH

VDR

2946 drw 06

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

71256S25

71256L25

71256S30⁽³⁾

71256L30⁽³⁾

71256S35

71256L35

71256S45

71256L45

71256L20⁽¹⁾

Min. Max.

Symbol

Parameter

Min. Max. Min. Max. Min. Max.

Min. Max. Unit

Read Cycle

tRC

tAA

Read Cycle Time

—

Address Access Time

tACS

Chip Select Access Time

(2)

tCLZ

tCHZ

tOE

Chip Select to Output in Low-Z

Chip Deselect to Output in High-Z

Output Enable to Output Valid

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

Output Hold from Address Change

(2)

—

(2)

tOLZ

(2)

tOHZ

tOH

—

Write Cycle

tWC

tCW

tAW

tAS

Write Cycle Time

—

Chip Select to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

tWP

tWR

tDW

tWHZ

tDH

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Write Enable to Output in High-Z

Data Hold from Write Time

Output Active from End-of-Write

—

(2)

tOW

NOTES:

1. 0° to +70°C temperature range only.

2946 tbl 11

2. This parameter guaranteed by device characterization, but is not production tested.

3. –55° to +125°C temperature range only.

7.2

IDT71256 S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)

71256S55⁽¹⁾

71256L55⁽¹⁾

71256S70⁽¹⁾

71256L70⁽¹⁾

71256S85⁽¹⁾

71256L85⁽¹⁾

71256S100^(1,3)

71256L100^(1,3)

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

Read Cycle

tRC

tAA

Read Cycle Time

—

100

—

100

—

Address Access Time

tACS

Chip Select Access Time

(2)

tCLZ

tCHZ

tOE

Chip Deselect to Output in Low-Z

Output Enable to Output in Low-Z

Output Enable to Output Valid

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

Output Hold from Address Change

(2)

—

(2)

tOLZ

—

(2)

tOHZ

tOH

—

Write Cycle

tWC

tCW

tAW

tAS

Write Cycle Time

—

100

—

Chip Select to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

tWP

tWR

tDW

tDH

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Data Hold from Write Time (WE)

Write Enable to Output in High-Z

Output Active from End-of-Write

(2)

tWHZ

—

(2)

tOW

NOTES:

2946 tbl 11

1. –55°C to +125°C temperature range only.

2. This parameter guaranteed by device characterization, but is not production tested.

3. Also available: 120 and 150 ns military devices.

7.2

IDT71256S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1⁽¹⁾

tRC

ADDRESS

tAA

tOH

tOE

(5)

tOHZ

tOLZ

tACS

(5)

tCHZ

tCLZ

DATA OUT

2946 drw 07

TIMING WAVEFORM OF READ CYCLE NO. 2^{(1, 2, 4)}

tRC

ADDRESS

tAA

tOH

DATA OUT

2946 drw 08

TIMING WAVEFORM OF READ CYCLE NO. 3^{(1, 3, 4)}

ACS

(5)

CLZ

(5)

CHZ

DATA OUT

2946 drw 09

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

7.2

IDT71256 S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

CONTROLLED TIMING)^{(1, 2, 3, 5, 7)}

tWC

ADDRESS

(6)

tOHZ

tAW

(7)

tWP

tWR

tAS

(6)

tWHZ

tOW

DATA OUT

DATA IN

(4)

tDW

tDH

2946 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CONTROLLED TIMING)^{(1, 2, 3, 5)}

ADDRESS

(7)

ttWR

tDH2

DATA IN

2946 drw 11

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

be as short as the spectified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.

7.2

IDT71256S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

71256

XXX

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

300 mil CERDIP (D28-3)

600 mil CERDIP (D28-1)

300 mil SOJ (SO28-5)

600 mil Plastic DIP (P28-1)

Leadless Chip Carrier (32-pin) (L32-1)

Commercial Only

Military Only

Speed in nanoseconds

100

120

150

Standard Power

Low Power

2946 drw 12

7.2

IDT71256S120D [IDT]

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