IDT71256SA20Y8 [IDT]

Standard SRAM, 32KX8, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28;
IDT71256SA20Y8
型号: IDT71256SA20Y8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Standard SRAM, 32KX8, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

静态存储器 光电二极管 内存集成电路
文件: 总8页 (文件大小:81K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CMOS Static RAM  
256K (32K x 8-Bit)  
IDT71256SA  
Features  
Description  
32K x 8 advanced high-speed CMOS static RAM  
TheIDT71256SA isa262,144-bithigh-speedStaticRAMorganized  
as32Kx8.ItisfabricatedusingIDT’shigh-perfomance,high-reliability  
CMOS technology. This state-of-the-art technology, combined with  
innovativecircuitdesigntechniques,providesacost-effectivesolutionfor  
high-speedmemoryneeds.  
Commercial (0° to 70°C) and Industrial (-40° to 85°C)  
temperature options  
Equal access and cycle times  
– CommercialandIndustrial:12/15/20/25ns  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
TheIDT71256SAhasanoutputenablepinwhichoperatesasfastas  
6ns,withaddress accesstimesasfastas12ns. Allbidirectionalinputsand  
outputsoftheIDT71256SA areTTL-compatibleandoperationisfroma  
single5Vsupply. Fullystaticasynchronouscircuitryisused,requiringno  
clocksorrefreshforoperation.  
TTL-compatible  
Low power consumption via chip deselect  
Commercial product available in 28-pin 300- and 600-mil  
Plastic DIP, 300 mil Plastic SOJ and TSOP packages  
Industrial product available in 28-pin 300 mil Plastic SOJ  
TheIDT71256SAispackagedin28-pin300-and600-milPlasticDIP,  
28-pin300milPlasticSOJandTSOP.  
and TSOP packages  
FunctionalBlockDiagram  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
262,144-BIT  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
A9  
A10  
A11  
A12  
A13  
A14  
,
8
8
I/O0 - I/O7  
I/O CONTROL  
2948 drw 01  
CS  
WE  
OE  
CONTROL  
LOGIC  
FEBRUARY 2001  
1
DSC-2948/07  
©2000IntegratedDeviceTechnology,Inc.  
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
AbsoluteMaximumRatings(1)  
PinConfigurations  
Symbol  
Rating  
Value  
Unit  
1
28  
27  
26  
25  
24  
VCC  
WE  
A
A
A
A
A
A
A
A
A
A
I/O  
I/O  
I/O  
14  
12  
CC  
V
Supply Voltage  
-0.5 to +7.0  
V
2
3
Relative to GND  
7
6
5
4
3
2
1
0
A
A
13  
8
TERM  
V
CC  
Terminal Voltage  
Relative to GND  
-0.5 to V +0.5  
V
4
5
A
A
9
6
23  
22  
11  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
-55 to +125  
-55 to +125  
1.0  
oC  
oC  
W
BIAS  
T
SO28-5  
P28-2  
P28-1  
7
OE  
STG  
T
8
21  
20  
A
10  
9
CS  
T
P
10  
11  
12  
13  
14  
19  
18  
I/O  
I/O  
I/O  
I/O  
I/O  
7
0
1
2
6
5
4
3
OUT  
I
DC Output Current  
50  
mA  
17  
16  
15  
2948 tbl 02  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS  
may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other conditions above those  
indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect  
reliability.  
GND  
,
2948 drw 02  
DIP/SOJ  
Top View  
22  
23  
24  
25  
26  
27  
28  
1
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
A
10  
OE  
CS  
I/O  
I/O  
I/O  
I/O  
I/O3  
GND  
I/O  
I/O  
I/O  
A11  
Truth Table(1,2)  
7
A
9
6
A8  
Function  
I/O  
CS  
OE  
WE  
A13  
5
WE  
4
OUT  
DATA  
L
L
H
Read Data  
Write Data  
High-Z Outputs Disabled  
VCC  
SO28-8  
A14  
IN  
DATA  
L
X
H
X
X
L
2
A
12  
2
,
3
A
A
A
A
A
7
6
5
4
3
1
L
H
4
0
5
A0  
A1  
A
2
SB  
H
X
High-Z Deselected - Standby (I )  
6
7
8
(3)  
HC  
SB1  
)
V
X
High-Z Deselected - Standby (I  
2948 drw 02a  
2948 tbl 03  
NOTES:  
TSOP  
Top View  
1. H = VIH, L = VIL, x = Don't care.  
2. VLC = 0.2V, VHC = VCC –0.2V.  
3. Other inputs VHC or VLC.  
RecommendedDCOperating  
Conditions  
RecommendedOperating  
TemperatureandSupplyVoltage  
Symbol  
Parameter  
Min. Typ.  
Max.  
5.5  
0
Unit  
V
Grade  
Commercial  
Industrial  
Temperature  
0OC to +70OC  
-40OC to +85OC  
GND  
Vcc  
CC  
V
Supply Voltage  
4.5  
0
5.0  
0V  
4.5V ± 5.5V  
4.5V ± 5.5V  
GND Ground  
0
V
0V  
____  
IH  
CC  
V
Input High Voltage  
Input Low Voltage  
2.2  
V
+0.5  
0.8  
V
2948 tbl 01  
-0.5(1)  
V
____  
IL  
V
2948 tbl 04  
NOTE:  
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.  
2
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
DC Electrical Characteristics  
(VCC = 5.0V ± 10%)  
IDT71256SA  
Symbol  
Parameter  
Input Leakage Current  
Output Leakage Current  
Output Low Voltage  
Test Conditions  
Min.  
Max.  
5
Unit  
µA  
µA  
V
___  
LI  
|I |  
CC  
IN =  
CC  
V
= Max., V GND to V  
___  
___  
LO  
|I |  
CC  
V
IH OUT  
CC  
= Max., CS = V , V = GND to V  
5
OL  
V
OL  
CC  
I
= 8mA, V = Min.  
0.4  
___  
OH  
V
OH  
I
CC  
Output High Voltage  
= -4mA, V = Min.  
2.4  
V
2948 tbl 05  
DCElectricalCharacteristics(1)  
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)  
Symbol  
Parameter  
71256SA12  
71256SA15  
71256SA20  
71256SA25  
Unit  
ICC  
Dynamic Operating Current  
160  
150  
145  
145  
mA  
(2)  
(2)  
IL  
CC  
MAX  
CS < V , Outputs Open, V = Max., f = f  
ISB  
Standby Power Supply Current (TTL Level)  
50  
15  
40  
15  
40  
15  
40  
15  
mA  
mA  
IH  
CC  
MAX  
CS > V , Outputs Open, V = Max., f = f  
ISB1  
Standby Power Supply Current (CMOS Level)  
(2)  
HC  
CC  
CS > V , Outputs Open, V = Max., f = 0 ,  
IN  
LC  
IN  
HC  
V < V or V > V  
2948 tbl 06  
NOTES:  
1. All values are maximum guaranteed values.  
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.  
Capacitance  
(TA = +25°C, f = 1.0MHz, SOJ package)  
AC Test Conditions  
Input Pulse Levels  
GND to 3.0V  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
Max.  
Unit  
Input Rise/Fall Times  
3ns  
1.5V  
IN  
C
IN  
V = 3dV  
7
pF  
Input Timing Reference Levels  
Output Reference Levels  
AC Test Load  
1.5V  
C
I/O  
VOUT = 3dV  
7
pF  
2948 tbl 08  
See Figures 1 and 2  
NOTE:  
2948 tbl 07  
1. This parameter is guaranteed by device characterization, but not production  
tested.  
5V  
5V  
480  
480Ω  
OUT  
DATA  
OUT  
DATA  
5pF*  
255Ω  
30pF*  
255Ω  
.
,
2948 drw 03  
2948 drw 04  
Figure 1. AC Test Load  
Figure 2. AC Test Load  
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)  
*Including jig and scope capacitance.  
6.42  
3
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
AC Electrical Characteristics (VCC = 5.0V ± 10%)  
71256SA12  
71256SA15  
71256SA20  
Min. Max.  
71256SA25  
Min. Max.  
Min. Max.  
Min.  
Max.  
Symbol  
Read Cycle  
RC  
Parameter  
Unit  
____  
____  
____  
____  
t
Read Cycle Time  
Address Access Time  
12  
15  
20  
25  
ns  
ns  
ns  
ns  
____  
____  
____  
____  
AA  
t
12  
15  
20  
25  
____  
____  
____  
____  
ACS  
t
Chip Select Access Time  
12  
15  
20  
25  
____  
____  
____  
____  
(1)  
Chip Select to Output in Low-Z  
Chip Select to Output in High-Z  
Output Enable to Output Valid  
Output Enable to Output in Low-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
Chip Select to Power Up Time  
Chip Deselect to Power Down Time  
4
4
4
4
CLZ  
t
(1)  
0
6
0
7
0
10  
0
11  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CHZ  
t
____  
____  
____  
____  
tOE  
6
7
10  
11  
____  
____  
____  
____  
(1)  
0
0
3
0
0
3
0
0
3
0
0
3
OLZ  
t
(1)  
OHZ  
6
6
8
10  
t
____  
____  
____  
____  
OH  
t
____  
____  
____  
____  
(1)  
PU  
0
0
0
0
t
____  
____  
____  
____  
(1)  
PD  
12  
15  
20  
25  
t
Write Cycle  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
WC  
t
Write Cycle Time  
12  
9
9
0
8
0
6
0
4
15  
10  
10  
0
20  
15  
15  
0
25  
20  
20  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAW  
Address Valid to End-of-Write  
Chip Select to End-of-Write  
Address Set-up Time  
CW  
t
AS  
t
WP  
t
Write Pulse Width  
10  
0
15  
0
20  
0
WR  
t
Write Recovery Time  
DW  
t
Data Valid to End-of-Write  
Data Hold Time  
7
11  
0
13  
0
DH  
t
0
____  
____  
____  
____  
(1)  
Output Active from End-of-Write  
4
4
4
tOW  
(1)  
WHZ  
Write Enable to Output in High-Z  
0
6
0
6
0
10  
0
11  
ns  
t
2948 tbl 09  
NOTE:  
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.  
4
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Read Cycle No. 1(1)  
tRC  
ADDRESS  
tAA  
OE  
tOE  
(5)  
tOLZ  
(5)  
CS  
(5)  
(3)  
tOHZ  
tACS  
(5)  
tCLZ  
tCHZ  
HIGH IMPEDANCE  
tPU  
DATAOUT  
DATA OUT VALID  
tPD  
ICC  
ISB  
VCC SUPPLY  
CURRENT  
2948 drw 05  
,
Timing Waveform of Read Cycle No. 2(1,2,4)  
tRC  
ADDRESS  
tAA  
tOH  
tOH  
DATAOUT VALID  
DATAOUT  
PREVIOUS DATAOUT VALID  
2948 drw 06  
,
NOTES:  
1. WE is HIGH for Read Cycle.  
2. Device is continuously selected, CS is LOW.  
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.  
4. OE is LOW.  
5. Transition is measured ±200mV from steady state.  
6.42  
5
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)  
tWC  
ADDRESS  
tAW  
CS  
(2)  
tWR  
tOW  
tAS  
(3)  
tWP  
WE  
(5)  
(5)  
tCHZ  
(3)  
tWHZ  
(5)  
HIGH IMPEDANCE  
DATAOUT  
DATAIN  
tDH  
tDW  
DATAIN VALID  
2948 drw 07  
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)  
tWC  
ADDRESS  
tAW  
CS  
tWR  
tCW  
tAS  
WE  
tDW  
tDH  
DATAIN  
DATAIN VALID  
2948 drw 08  
,
NOTES:  
1. A write occurs during the overlap of a LOW CS and a LOW WE.  
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data  
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as  
short as the specified tWP.  
3. During this period, I/O pins are in the output state, and input signals must not be applied.  
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.  
5. Transition is measured ±200mV from steady state.  
6
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
Ordering Information — Commercial  
IDT  
71256  
SA  
XX  
XXX  
X
Device  
Type  
Power  
Speed  
Package  
Process/  
Temperature  
Range  
Blank  
Commercial (0°C to +70°C)  
P
TP  
Y
600-mil Plastic DIP (P28-1) only 25ns available  
300-mil Plastic DIP (P28-2)  
300-mil SOJ (SO28-5)  
PZ  
TSOP Type I (SO28-8)  
12  
15  
20  
25  
,
Speed in nanoseconds  
2948 drw 09  
Ordering Information — Industrial  
IDT  
71256  
SA  
XX  
XXX  
X
Device  
Type  
Power  
Speed  
Package  
Process/  
Temperature  
Range  
I
Industrial (-40°C to +85°C)  
Y
PZ  
300-mil SOJ (SO28-5)  
TSOP Type I (SO28-8)  
12  
15  
20  
25  
,
Speed in nanoseconds  
2948 drw 10  
6.42  
7
IDT71256SA  
CMOS Static RAM 256K (32K x 8-Bit)  
Commercial and Industrial Temperature Ranges  
DatasheetDocumentHistory  
1/7/00  
Updatedtonewformat  
RevisedIndustrialTemperaturerangeofferings  
RemovedNoteNo.1forWriteCyclediagrams,renumberedfootnotesandnotes  
AddedDatasheetDocumentHistory  
Pp. 1, 3, 4, 7  
Pg. 6  
Pg. 8  
08/09/00  
02/01/01  
Notrecommendedfornewdesigns  
Removed"Notrecommendedfornewdesigns"  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
sramhelp@idt.com  
800 544-7726, x4033  
800-345-7015 or 408-727-6116  
fax:408-492-8674  
www.idt.com  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
8

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