IDT7164S25PGI [IDT]
Standard SRAM, 8KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | IDT7164S25PGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7164S/LS
IDT7164L/LL
CMOS Static RAM
64K (8K x 8-Bit)
Features
Description
◆
High-speed address/chip select access time
TheIDT7164isa65,536bithigh-speedstaticRAMorganizedas8K
x8.ItisfabricatedusingIDT’shigh-performance,high-reliabilityCMOS
technology.
– Military:20/25/35/45/55/70/85/100ns(max.)
– Industrial:25/35ns (max.)
– Commercial:15/20/25/35ns(max.)
Low power consumption
Battery backup operation – 2V data retention voltage
(L Version only)
Produced with advanced CMOS high-performance
technology
Inputs and outputs directly TTL-compatible
Three-state outputs
Address access times as fast as 15ns are available and the circuit
offers a reduced power standby mode. When CS1 goes HIGH or CS2
goes LOW, the circuit will automatically go to, and remain in, a low-
power stand by mode. The low-power (L) version also offers a battery
backup data retention capability at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
◆
◆
◆
◆
◆
◆
Available in 28-pin DIP, CERDIP and SOJ
Military product compliant to MIL-STD-883, Class B
◆
TheIDT7164ispackagedina28-pin300milDIPandSOJ anda28-
pin600milCERDIP.
Militarygradeproductismanufacturedincompliancewiththelatest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demandingthe highestlevelofperformance
and reliability.
Functional Block Diagram
A0
VCC
GND
65,536 BIT
MEMORY ARRAY
ADDRESS
DECODER
A
12
7
0
I/O
0
7
I/O CONTROL
I/O
CS1
CS2
OE
CONTROL
LOGIC
2967 drw 01
WE
FEBRUARY 2007
1
DSC-2967/14
©2007 IntegratedDeviceTechnology,Inc.
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configurations
Symbol
Rating
Com'l.
Mil.
Unit
V
WE
CS
CC
NC
1
28
27
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
A12
2
2
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
1
2
3
26
25
24
A
A
A
8
4
Operating
Te m p e rature
0 to +70
-55 to +125
-65 to +135
oC
oC
D28-1
D28-3
P28-1
P28-2
SO28-5
T
A
9
5
11
6
23
22
Te m p e rature
Under Bias
-55 to +125
TBIAS
OE
7
A10
8
21
20
CS
1
TSTG
Storage Temperature -55 to +125
-65 to +150
oC
W
9
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
10
11
12
13
14
19
18
17
16
P
T
Power Dissipation
DC Output Current
1.0
50
1.0
50
I/O
I/O
I/O
IOUT
mA
2967 tbl 02
NOTES:
15
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
,
DIP/SOJ2967 drw 02
Top View
Pin Descriptions
Truth Table(1,2,3)
WE
CS1
CS
2
OE
I/O
Function
Deselected - Standby (ISB
Deselected - Standby (ISB
Deselected - Standby (ISB1)
Name
Description
Address
X
H
X
X
X
High-Z
High-Z
High-Z
)
A0 - A12
X
L
X
)
I/O
CS
CS
0
- I/O
7
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
X
V
HC or
VLC
X
VHC
1
2
X
H
H
L
X
L
L
L
V
LC
X
H
L
High-Z
High-Z
Deselected - Standby (ISB1
Output Disabled
Read Data
)
WE
OE
H
H
H
DATAOUT
DATAIN
GND
X
Write Data
VCC
Power
2967 tbl 03
NOTES:
2967 tbl 01
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V
Recommended DC Operating
Conditions
Recommended Operating
Symbol
Parameter
Min.
Typ.
Max.
5.5
0
Unit
V
Temperature and Supply Voltage
V
CC
Supply Voltage
4.5
5.0
Grade
Temperature
-55OC to +125OC
-40OC to +85OC
0OC to +70OC
GND
Vcc
GND Ground
0
0
V
Military
0V
5V ± 10%
5V ± 10%
5V ± 10%
____
V
IH
Input HIGH Voltage
Input LOW Voltage
2.2
V
CC + 0.5
V
Industrial
0V
-0.5(1)
0.8
V
____
VIL
Commercial
0V
2967 tbl 05
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
2967 tbl 04
2
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 0V
OUT = 0V
Max.
Unit
CIN
V
8
pF
CI/O
V
8
pF
2967 tbl 06
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S15
7164L15
7164S20
7164L20
7164S25
7164L25
Com'l.
110
100
180
150
20
Com'l.
100
90
Ind.
110
100
170
150
20
Mil.
110
100
180
160
20
Com'l.
90
Ind.
110
100
170
150
20
Symbol
Parameter
Power
Mil.
110
100
180
160
20
Unit
ICC1
Operating Power Supply Current
S
L
S
L
S
L
mA
CS
1
= VIL, CS
2
= VIH, Outputs Open
V
CC = Max., f
=
0(2)
90
ICC2
Dynamic Operating Current
CS = VIL, CS = VIH, Outputs Open
CC = Max., f = fMAX
mA
mA
mA
170
150
20
170
150
20
1
2
(2)
V
ISB
Standby Power Supply Current
(TTL Level), CS1 > VIH, CS2 < VIL,
(2)
Outputs Open, VCC = Max., f = fMAX
3
3
3
5
3
3
5
ISB1
Full Standby Power Supply Current
(CMOS Level), f = 0(2), VCC = Max.
S
L
15
15
15
20
1
15
15
20
1
1. CS
1
> VHC and CS
< VLC
2 > VHC, or
0.2
0.2
0.2
0.2
0.2
2. CS
2
2967 tbl 07
7164S35
7164L35
7164S45
7164L45
7164S55
7164L55
7164S70
7164S85/100
7164L85/100
7164L70
Mil.
100
90
Com'l. Ind.
Mil.
100
90
Mil.
100
90
Mil.
100
90
Symbol
Parameter
Power
Mil.
100
90
Unit
I
CC1 Operating Power Supply Current
S
L
S
L
S
L
90
90
110
100
150
130
20
mA
CS
1
= VIL, CS
2
= VIH, Outputs Open
VCC = Max., f
=
0(2)
ICC2
Dynamic Operating Current
CS = VIL, CS = VIH, Outputs Open
CC = Max., f = fMAX
mA
mA
mA
150
130
20
160
140
20
160
130
20
160
125
20
160
120
20
160
120
20
1
2
(2)
V
ISB
Standby Power Supply Current
(TTL Level), CS > VIH, CS
Outputs Open, VCC = Max., f = fMAX
1
2 < VIL,
(2)
3
3
5
5
5
5
5
ISB1 Full Standby Power Supply Current
S
L
15
15
20
1
20
1
20
1
20
1
20
1
(CMOS Level), f = 0(2), VCC = Max.
1. CS
1
> VHC and CS
< VLC
2 > VHC, or
0.2
0.2
2. CS
2
2967 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
6.42
3
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DC Electrical Characteristics (VCC = 5.0V ± 10%)
IDT7164S
IDT7164L
Symbol
Parameter
Test Conditions
MIL.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
Input Leakage Current
|ILI|
V
CC = Max.,
10
5
5
2
V
IN = GND to VCC
COM'L. & IND
µA
____
____
____
____
|ILO
|
Output Leakage Current
Output Low Voltage
V
CC = Max., CS
1
= VIH
,
MIL.
COM'L. & IND
10
5
5
2
VOUT = GND to VCC
µA
V
____
____
____
____
IOL = 8mA, VCC = Min.
0.4
0.4
VOL
IOL = 10mA, VCC = Min.
0.5
0.5
____
____
VOH
Output High Voltage
IOH = -4mA, VCC = Min.
2.4
2.4
V
2967 tbl 09
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1)
Max.
VCC @
VCC @
Symbol
Parameter
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
____
____
____
____
____
V
DR
V
CC for Data Retention
2.0
____
____
Data Retention Current
MIL.
COM'L. & IND
10
10
15
15
200
60
300
90
µA
ICCDR
(3)
CDR
____
____
____
____
t
Chip Deselect to Data
Retention Time
0
ns
1. CS
CS
2. CS
1
> VHC
> VHC, or
< VLC
2
2
____
____
____
____
____
____
(3)
(2)
Operation Recovery Time
Input Leakage Current
ns
t
R
t
RC
(3)
____
2
2
µA
IILII
2967 tbl 10
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 11
5V
5V
480Ω
480Ω
DATAOUT
255Ω
DATAOUT
5pF*
255Ω
30pF*
,
,
2967 drw 04
2967 drw 03
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
4
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S15(1)
7164L15(1)
7164S20(2)
7164L20(2)
7164S25
7164S35
7164L35
7164L25
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
____
____
____
____
t
RC
Read Cycle Time
15
20
25
35
ns
ns
ns
____
____
____
____
tAA
Address Access Time
15
15
19
20
25
25
35
35
____
____
____
____
____
____
____
____
(3)
ACS1
Chip Select-1 Access Time
t
(3)
ACS2
Chip Select-2 Access Time
20
25
30
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
(4)
CLZ1,2
____
____
____
____
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1,2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
5
5
5
5
t
____
____
____
____
tOE
7
8
12
18
____
____
____
____
(4)
OLZ
0
0
0
0
t
____
____
____
____
(4)
CHZ1,2
8
9
13
15
t
____
____
____
____
(4)
OHZ
7
8
10
15
t
____
____
____
____
tOH
5
5
5
5
____
____
____
____
(4)
PU
0
0
0
0
t
____
____
____
____
(4)
PD
15
20
25
35
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW1,2
AW
AS
WP
WR1
WR2
Write Cycle Time
15
14
14
0
20
15
15
0
25
18
18
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
14
0
15
0
21
0
25
0
t
Write Recovery Time (CS
1
, WE)
t
Write Recovery Time (CS
2)
5
5
5
5
____
____
____
____
(4)
WHZ
Write Enable to Output in High-Z
Data to Write Time Overlap
6
8
10
14
t
____
____
____
____
t
DW
DH1
DH2
8
0
5
4
10
0
13
0
15
0
____
____
____
____
____
____
____
____
t
Data Hold from Write Time (CS , WE)
1
t
Data Hold from Write Time (CS
2)
5
5
5
____
____
____
____
(4)
OW
Output Active from End-of-Write
4
4
4
ns
t
2967 tbl 12
NOTES:
1. 0° to +70°C temperature range only.
2. 0° to +70°C and –55°C to +125°C temperature ranges only.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
6.42
5
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges)
7164S45
7164L45
7164S55
7164L55
7164S70
7164L70
7164S85/100
7164L85/100
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
____
____
____
____
t
RC
Read Cycle Time
45
55
70
85/100
ns
ns
ns
____
____
____
____
tAA
Address Access Time
45
45
55
55
70
70
85/100
85/100
____
____
____
____
____
____
____
____
(1)
ACS1
Chip Select-1 Access Time
t
(1)
ACS2
Chip Select-2 Access Time
45
55
70
85/100
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
____
____
____
____
(2)
CLZ1,2
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1,2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
5
5
5
5
t
____
____
____
____
tOE
25
30
35
40
____
____
____
____
(2)
OLZ
0
0
0
0
t
____
____
____
____
(2)
CHZ1,2
20
25
30
35
t
____
____
____
____
(2)
OHZ
20
25
30
35
t
____
____
____
____
tOH
5
5
5
5
____
____
____
____
(2)
PU
0
0
0
0
t
____
____
____
____
(2)
PD
45
55
70
85/100
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW1,2
AW
AS
WP
WR1
WR2
Write Cycle Time
45
33
33
0
55
50
50
0
70
60
60
0
85/100
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
75
t
0
t
25
0
50
0
60
0
75
t
Write Recovery Time (CS
1
, WE)
0
t
Write Recovery Time (CS
2)
5
5
5
5
____
____
____
____
(2)
WHZ
Write Enable to Output in High-Z
Data to Write Time Overlap
18
25
30
35
t
____
____
____
____
t
DW
DH1
DH2
20
0
25
0
30
0
35
0
____
____
____
____
____
____
____
____
t
Data Hold from Write Time (CS , WE)
1
t
Data Hold from Write Time (CS
2)
5
5
5
5
____
____
____
____
(2)
OW
Output Active from End-of-Write
4
4
4
4
ns
t
2967 tbl 13
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
6
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
t
RC
ADDRESS
t
OH
tAA
OE
tOE
(5)
t
OLZ
CS2
t
(5)
ACS2
(5)
tCHZ2
tCLZ2
CS1
(5)
OHZ
tACS1
t
(5)
(5)
CLZ1
t
tCHZ1
DATAOUT
DATA VALID
2967 drw 05
Timing Waveform of Read Cycle No. 2(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
DATAOUT
DATA VALID
2967 drw 06
Timing Waveform of Read Cycle No. 3(1,3,4)
CS1
CS2
t
ACS2
(5)
(5)
(5)
(5)
t
CHZ2
t
CLZ2
ACS1
CLZ1
t
t
CHZ1
t
DATAOUT
DATA VALID
tPU
I
CC
POWER
SUPPLY
CURRENT
I
SB
t
PD
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
2967 drw 07
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
7
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5)
t
WC
ADDRESS
CS2
CS1
(2)
WR1
t
t
AW
tAS
WE
(3)
(5)
(6)
OW
tWP
t
DATAOUT
DATAIN
t
DH1,2
t
DW
(6)
t
WHZ
DATA VALID
2967 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1)
t
WC
ADDRESS
(2)
WR2
tAS
t
t
CS2
(2)
WR1
t
CW
(4)
CS1
tAW
WE
t
DW
tDH1,2
DATAIN
DATA VALID
2967 drw 09
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified tWP.
6. Transition is measured ±200mV from steady state.
8
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥ 2V
t
CDR
tR
CS
VIH
VIH
VDR
2967 drw 10
Ordering Information — Commercial
IDT
X
7164
X
XX
XXX
L
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
G
Commercial (0°C to +70°C)
Restricted hazardous substancwe device
Y*
P**
TP*
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
300 mil Plastic DIP (P28-2)
15
20
25
35
Speed in nanoseconds
,
S
L
Standard Power
Low Power
First generation or current die step
Current generation die step optional
Blank
L
* Available for 15ns and 20ns speed grades only.
** Available for 25ns and 35ns speed grades only.
2967 drw 11
6.42
9
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Ordering Information — Industrial
IDT
L
X
7164
X
XX
XXX
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
I
Industrial (–40°C to +85°C)
G
Restricted hazardous substance device
P
Y
600 mil Plastic DIP (P28-1)
300 mil Plastic SOJ (PJ28)
20
25
35
Speed in nanoseconds
Standard Power
S
L
,
Low Power
Blank First generation or current die step
Current generation die step optional
L
2967 drw 12
Ordering Information — Military
IDT
7164
X
XX
XXX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
B
Military (–55°C to +125°C)
Compliant with MIL-STD-883, Class B
D
TD
600 mil CERDIP (D28-1)
300 mil CERDIP (D28-3)
20*
25
35
45
55
70
85
Speed in nanoseconds
100**
S
L
Standard Power
Low Power
*
Available only in 600mil CERDIP (D28-1) and 300mil CERDIP
(D28-1) and 300mil CERDIP (D28-3) packaging for a low power.
** Available only in 600 mil CERDIP (D28-1) packaging.
2967 drw 13
10
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DatasheetDocumentHistory
1/13/2000
Updatedtonewformat
AddedIndustrialTemperaturerangeofferings
Removedcommercial70nsspeedgradeoffering
Added100nsspeedgradespecificationdetails
RevisednotesandfootnotesinDCElectricaltables
Pp. 1, 2, 3, 5, 10
Pp. 1, 3, 9
Pp. 1, 3, 6, 10
Pg. 3
Pp. 5, 6
RevisednotesandfootnotesinACElectricaltables
Pg. 8
Pp. 9, 10
Pg. 11
RemovedNote 1fromWrite Cycle No. 1andNo. 2diagrams;renumberednotes andfootnotes
SeparatedOrderingInformationintocommercial,industrial,andmilitaryofferings
AddedDatasheetDocumentHistory
08/09/00
02/01/01
12/07/01
09/30/04
11/16/06
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
AddPJ28toIndustrialtemperature.
Added"restrictedhazardoussubstancedevice"toorderinginformation.
Addedinustrialtemppowerlimitsfor20nspart.Changedpowerlimitsfor25nspartforcommercial
andindustrial. Changedpowerlimitsforcommercialandindustrialfor35nspart.
Added 20ns part to ordering information. Refer to PCN SR-0602-01
AddedLgenerationdiesteptodatasheetorderinginformatiom.
Pg. 10
Pg. 9,10
Pg.3
Pg.10
Pg. 9, 10
02/20/07
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
11
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明