IDT71P73204S167BQ [IDT]
DDR SRAM, 2MX8, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165;
| 型号： | IDT71P73204S167BQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | DDR SRAM, 2MX8, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 双倍数据速率 静态存储器 |
| 文件： | 总25页 (文件大小：635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71P73204
IDT71P73104
IDT71P73804
IDT71P73604
18Mb Pipelined
DDR™II SRAM
Burst of 4
Features
Description
The IDT DDRIITM Burst of four SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization on the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
less than single data rate speeds,allowing the user to fan out addresses
and ease system design while maintaining maximum performance on
data transfers.
◆
◆
◆
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Common Read and Write Data Port
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
MultiplexedAddress Bus
-
One Read or One Write request per two clock
cycles.
DDR (Double Data Rate) Data Bus
Four word bursts data per two clock cycles
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
◆
-
◆
◆
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. Theoutput impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
◆
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
-
◆
1.8V Core Voltage (VDD)
◆
JTAG Interface
◆
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
Functional Block Diagram
DATA
REG
(Note1)
WRITE DRIVER
(Note2)
SA
ADD
REG
(Note2)
SA0
SA
1
(Note4)
(Note4)
(Note1)
18M
MEMORY
ARRAY
DQ
LD
RW
BWx
CTRL
LOGIC
(Note3)
K
K
CLK
GEN
CQ
CQ
C
SELECT OUTPUT CONTROL
C
6431 drw 16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
JULY 2005
1
©2005 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.“
DSC-6431/00
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Clocking
output at the designated time in correspondence with the C andC clocks.
Write operations are initiated by holding the Read/Write control
input (R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
The DDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K and K clocks are the primary device input clocks. The K
clock is used to clock in the control signals (LD, R/W and BWx or NWx),
the address, and the first and third words of the data burst during a write
operation. The K clock is used to clock in the control signals (BWx or
NWx), and the second and fourth words of the data burst during a write
operation. The K and K clocks are also used internally by the SRAM. In
the event that the user disables the C and C clocks, the K and K clocks
will also be used to clock the data out of the output register and generate
the echo clocks.
The C and C clocks may be used to clock the data out of the
output register during read operations and to generate the echo clocks.
C and C must be presented to the SRAM within the timing tolerances.
The output data from the DDRII will be closely aligned to the C and C
input, through the use of an internal DLL. When C is presented to the
DDRII SRAM, the DLL will have already internally clocked the data to
arrive at the device output simultaneously with the arrival of theC clock.
The C and second data item of the burst will also correspond. The third
and fourth data words will follow on the next clock cycle of the C and C,
the address. On the following rising edge of K, the first word of the four
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BWx or NWx) inputs. On the
following rising edge of K, the second word of the data write burst will be
accepted at the device inputwith the designated (BWx or NWx) inputs.
The subsequent K and K rising edges will receive the last two words of
the four word burst, with their BWx/NWx enables.
DDRII devices internally store four words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9 devices
do not have the ability to address to the single word level or change the
burst order; however the byte and nibble write signals can be used to
prevent writing any byte or individual nibbles, or combined to prevent
writing one word of the burst. The x18 and x36 DDRll devices have the
ability to address to the individual word level using the SA0 and SA1
address bits, but the burst will continue in a linear sequence and wraps
around without incrementing the SA bits. When reading or writing x18
and x36 DDRll devices, the burst will begin at the designated address,
but if the burst is started at any other position than the first word of the
burst, the burst will wrap back on itself and read the first locations before
completing. The x18 and x36 DDRII devices can also use the byte write
signals to prevent writing any individual byte or word of the burst.
respectively.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C
and C may be disabled by tying both signals high, forcing the outputs
and echo clocks to be controlled instead by the K and K clocks.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used
to closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLLby holding Doff low. With the DLLoff, the C andC (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and Vss to allow the SRAM to adjust its output drive
impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C
clocks (or K, K if C, C are disabled). The rising edge of C generates the
rising edge of CQ, and the falling edge of CQ. The rising edge of C
generates the rising edge of CQ and the falling edge of CQ. This
scheme improves the correlation of the rising and falling edges of the
echo clock and will improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guarantee-
ing that the echo clock will remain closely correlated with the data, within
the tolerances designated.
to it’s lowest value, the ZQ pin may be tied to VDDQ.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
6.242
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven
during a valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When
operating in a single clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a
Read operation is not initiated or LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high
Input/Output
Synchronous
DQ[X:0]
impedance after any previous read operation in progress completes.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
Input
Synchronous
BW
0
, BW
1
BW
2, BW
3
2M x 9 -- BW
0
controls DQ[8:0]
controls DQ[8:0] and BW
controls DQ[8:0], BW
1M x 18 -- BW
0
1
controls DQ[17:9]
512K x 36 -- BW
0
1
controls DQ[17:9], BW
2
controls DQ[26:18] and BW3 controls DQ[35:27]
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising
edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the
Input
NW0, NW1
Synchronous data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the
device.
2M x 8 -- NW0 controls D[3:0] and NW1 controls D[7:4].
Input
SA
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Synchronous
Input
Burst count address bits on x18 and x36 DDRll devices. These bits allow changing the burst order in read or write operations, or
SA0, SA1
Synchronous addressing to the individual word of a burst. See page 9 for all possible burst sequences.
Load Control Logic. Sampled on the rising edge of K. If LD is low, a four word burst read or write operation will initiate
Input
Synchronous
designated by the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations
LD
will not be initiated.
Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a
Input
Synchronous
R/W
C
read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is
high during the rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
Input Clock
details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
Input Clock together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
C
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
Input Clock
K
K
through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through
Input Clock
DQ[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can
Output Clock
CQ, CQ
be used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left
ZQ
Input
unconnected.
6431 tbl 02a
6.42
3
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL
turned off will be different from those listed in this data sheet. There will be an increased propagation
delay from the incidence of C and C to DQ, or K and K to DQ as configured. The propagation delay is not
a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed
grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected.
TMS
No
Connect
NC
No connects inside the package. Can be tied to any voltage level
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well
as AC measurement points.
VREF
Power
Supply
V
DD
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground for the device. Should be connected to ground of the system.
VSS
Ground
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or
scaled to the desired output voltage.
VDDQ
6431 tbl 02b
6.442
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73204 (2M x 8)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
K
7
8
9
10
11
V
SS/
V
SS/
CQ
SA
NC
NC
NC
R/W
SA
NC
SA
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
NW
1
LD
SA
SA (2)
SA (1)
DQ3
NC
NC
NC
NC
NC
NC
NC
SA
K
NC
NC
NC
NC
NC
NC
NW
0
NC
NC
VSS
NC
SA
VSS
VSS
VSS
VSS
VSS
VSS
DQ
NC
NC
ZQ
NC
NC
2
DQ
4
VDDQ
VSS
VSS
VSS
VDDQ
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ
5
VDDQ
VDD
VSS
VDD
VDDQ
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ1
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
K
L
DQ
NC
NC
NC
TDI
0
DQ
6
VDDQ
VSS
VSS
VSS
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
NC
M
N
P
R
NC
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
NC
DQ
7
SA
SA
SA
SA
NC
TCK
SA
TMS
C
6431 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73104 (2M x 9)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
K
7
8
9
10
11
V
SS/
V
SS/
SA
NC
NC
NC
R/W
SA
NC
NC
SA
NC
BW
SA
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
LD
SA
SA (2)
SA (1)
NC
NC
NC
NC
NC
NC
K
NC
NC
NC
NC
NC
NC
DQ3
VSS
NC
VSS
NC
NC
VSS
VSS
VSS
VSS
VSS
DQ
4
VDDQ
VSS
VSS
VSS
VDDQ
DQ
NC
NC
ZQ
NC
NC
2
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ
5
VDDQ
VDD
VSS
VDD
VDDQ
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ1
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
K
L
DQ
6
VDDQ
VSS
VSS
VSS
VDDQ
DQ
NC
NC
0
NC
VSS
VSS
VSS
VSS
VSS
NC
M
N
P
R
NC
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
NC
DQ
7
SA
SA
SA
SA
NC
DQ8
TCK
SA
TMS
TDI
C
6431 tbl 12a
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.642
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73804 (1M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
K
7
8
9
10
11
V
SS/
Vss/
SA (1)
SA
R/W
SA
NC
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
BW
1
LD
SA
SA (2)
DQ
9
NC
NC
SA
K
NC
DQ8
BW
0
NC
NC
NC
VSS
SA
0
SA
1
VSS
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
VDDQ
VSS
VSS
VSS
VDDQ
DQ6
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ
NC
ZQ
NC
5
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
NC
DQ14
NC
VDDQ
VDD
VSS
VDD
VDDQ
DQ4
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ3
K
L
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ
NC
NC
2
NC
VSS
VSS
VSS
VSS
VSS
DQ1
M
N
P
R
NC
DQ16
DQ17
SA
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
NC
SA
SA
SA
SA
NC
DQ0
TCK
TMS
TDI
C
6431 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to VSS.on the 1M x 18 DDRII Burst of 4 (71P73804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 4 (71P73804) devices.
6.42
7
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73604 (512K x 36)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
BW
BW
6
K
7
8
9
10
11
V
SS/
NC/
SA (1)
V
SS/
R/W
SA
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
2
3
BW
1
LD
SA
SA (3)
SA (2)
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
K
NC
DQ17
NC
DQ8
BW
0
VSS
SA
SA
0
SA
1
VSS
DQ7
DQ29
NC
VSS
VSS
VSS
VSS
VSS
DQ16
VDDQ
VSS
VSS
VSS
VDDQ
DQ15
NC
DQ6
DQ30
DQ31
VDDQ
VDD
VSS
VDD
V
DDQ
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ14
ZQ
G
H
J
VREF
V
DDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
NC
NC
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
VDDQ
VDD
VSS
VDD
VDDQ
DQ13
DQ12
NC
DQ4
VDDQ
VDD
VSS
VDD
VDDQ
DQ3
K
L
DQ33
NC
VDDQ
VSS
VSS
VSS
VDDQ
DQ2
VSS
VSS
VSS
VSS
VSS
DQ11
NC
DQ1
M
N
P
R
DQ35
NC
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
DQ10
SA
SA
SA
SA
DQ9
DQ0
TCK
TMS
TDI
C
6431 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address
2. A10 is reserved for the 72Mb expansion address.
3. A2 is reserved for the 144Mb expansion address.
6.842
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Write Descriptions(1,2)
Signal
BW
0
BW
X
L
1
BW
X
X
L
2
BW
X
X
X
L
3
NW
0
NW
X
1
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
Write Nibble 0
Write Nibble 1
L
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
6431 tbl 09
NOTES:
1) All byte write (BWx)and nibble write (NWx) signals are sampled on
the rising edge of K and again onK. The data that is present on the data
bus in the designated byte/nibble will be latched into the input if the
corresponding BWx orNWx is held low. The rising edge of K will sample
the first and third bytes/nibbles of the four word burst and the rising edge
of K will sample the second and fourth bytes/nibbles of the four word
burst.
2) The availability of the BWx or NWx on designated devices is de-
scribed in the pin description table.
3) The DDRII Burst of four SRAM has data forwarding. Aread request
that is initiated on the cycle following a write request to the same address
will produce the newly written data in response to the read request.
Linear Burst Sequence Table (1,2)
SA [1:0]
a
b
d
c
00
01
10
11
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
6431 tbl 22
NOTES:
1. SA [1:0] is the address presented on pins SA1 and SA0 giving the burst sequence a,b,c,d.
2. SA0 and SA1 are only available on the x18 and x36-bit devices.
6.42
9
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Application Example
SRAM #1
SRAM #4
Ω
R=250
Ω
R=250
ZQ
DQ
ZQ
DQ
V
t
BW0 BW1
LD R/W
A
S
SA
C C K K
C C K K
BW0 BW1
LD R/W
R
Vt
Data Bus
Address
R
V
t
R
t
V
LD
R
R
R
R/W
BWx/NWx
MEMORY
CONTROLLER
Return CLK
V
t
Source CLK
Return CLK
Source CLK
V
t
Vt
Ω
R=50
=VREF
6431 drw 20
61.402
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Absolute Maximum Ratings(1)(2)
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Parameter
Input Capacitance
Conditions
Max.
Unit
pF
Symbol
Rating
Value
Unit
C
IN
5
6
7
7
Supply Voltage on VDD with
Respect to GND
VTERM
–0.5 to +2.9
V
CCLK
Clock Input Capacitance
Output Capacitance
DQ I/O Capacitance
pF
V
DD = 1.8V
VDDQ = 1.5V
Supply Voltage on VDDQ with
Respect to GND
CO
pF
V
TERM
–0.5 to VDD+0.3
–0.5 to VDD+0.3
–0.5 to VDDQ+0.3
V
V
V
CDQ
pF
Voltage on Input terminals with
respect to GND
NOTE:
6431 tbl 06
VTERM
1. Testedatcharacterizationandretestedafteranydesignorprocesschangethat
may affect these parameters.
Voltage on Input, Output and I/O
terminals with respect to GND
VTERM
T
BIAS
STG
OUT
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
T
I
Continuous Current into Outputs
mA
6431 tbl 05
NOTES:
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
maycausepermanentdamagetothedevice. Thisisastressratingonlyand
functionaloperationofthedeviceattheseoranyotherconditionsabovethose
indicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDDQmustnotexceedVDDduringnormaloperation.
Recommended DC Operating and
Temperature Conditions
Symbol
Parameter
Power Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
1.4
0
Typ.
1.8
1.5
0
Max.
1.9
1.9
0
Unit
V
V
DD
DDQ
SS
V
V
V
V
Input Reference
Voltage
V
REF
0.68
0
V
DDQ/2
0.95
70
V
o
Ambient Temperature (1)
25
c
T
A
6431 tbl 04
NOTE:
1. During production testing, the case temperature equals the ambient
temperature.
6.42
11
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
VDD = Max VIN = VSS to VDDQ
Output Disabled
Min
-2
-2
-
Max
+2
Unit
Note
Input Leakage Current
Output Leakage Current
l
lL
lOL
+2
250MHz
200MHz
167MHz
250MHz
200MHz
167MHz
250MHz
200MHz
167MHz
250MHz
200MHz
167MHz
800
700
600
650
550
475
650
550
475
325
300
275
VDD = Max,
Operating Current
(x36): DDR
I
DD
IOUT = 0mA (outputs open),
-
mA
mA
mA
mA
1
1
1
2
Cycle Time > tKHKH Min
-
-
VDD = Max,
Operating Current
(x18): DDR
IDD
IOUT = 0mA (outputs open),
-
Cycle Time > tKHKH Min
-
-
VDD = Max,
Operating Current
(x9,x8): DDR
IDD
IOUT = 0mA (outputs open),
-
Cycle Time > tKHKH Min
-
-
Device Deselected (in NOP state),
IOUT = 0mA (outputs open),
Standby Current NOP
ISB1
-
f=Max,
All inputs < 0.2V or > VDD -0.2V
-
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
RQ = 250Ω, IOH = -15mA
RQ = 250Ω, IOL = 15mA
V
DDQ/2-0.12
DDQ/2-0.12
DDQ-0.2
V
DDQ/2+0.12
V
V
V
V
3, 7
4, 7
5
VOH
VOL
VOH
VOL
1
V
VDDQ/2+0.12
1
IOH = -0.1mA
V
VDDQ
2
IOL = 0.1mA
VSS
0.2
6
2
6431 tbl 10C
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an impedance
measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
61.422
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Min
Max
Unit Notes
Input High
Voltage, DC
V
IH (DC
)
V
REF +0.1
V
DDQ +0.3
V
V
V
V
1,2
1,3
4,5
Input Low
Voltage, DC
VIL (DC)
-0.3
V
REF -0.1
Input High
Voltage, AC
VIH (AC)
VREF +0.2
-
Input Low
Voltage, AC
VIL (AC)
-
V
REF -0.2
4,5
6431 tbl 10d
NOTES:
1. These are DC test criteria. DC design criteria is VREF +50mV. TheAC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is forAC function test only, not forAC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the targetAC level, VIL(AC) or VIH(AC)
b) Reach at least the targetAC level.
c)After theAC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
Undershoot Timing
20% tKHKH (MIN)
V
IH
V
DD +0.5
DD +0.25
DD
V
VSS
V
VSS-0.25V
V
SS-0.5V
VIL
6431 drw 22
6431 drw 21
20% tKHKH (MIN)
6.42
13
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
AC Test Conditions
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Symbol
VDD
Value
1.7-1.9
Unit
V
VDDQ
VIH
1.4-1.9
V
(VDDQ/2) + 0.5
(VDDQ/2) - 0.5
VDDQ/2
V
Input Low Level
VIL
V
Input Reference Level
Input Rise/Fall Time
VREF
V
0.3/0.3
TR/TF
ns
DQ Rise/Fall Time
0.5/0.5
Output Timing Reference Level
VDDQ/2
V
6431 tbl 11a
NOTE:
1. Parameters are tested with RQ=250Ω
Input Waveform
(VDDQ/2) + 0.5V
Test points
VDDQ/2
V
DDQ/2
(VDDQ/2) - 0.5V
6431 drw 07
Output Waveform
Test points
VDDQ/2
VDDQ/2
6431 drw 08
AC Test Load
VDDQ
/2
DDQ/2
V
Ω
RL = 50
REF
V
OUTPUT
Ω
=50
Z0
Device
Under
Test
Ω
Q = 250
R
ZQ
6431 drw 10
61.442
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C )(3,7)
250MHz
200MHz
167MHz
Unit
Note
Symbol
Parameter
Min.
Max
Min.
Max
Min.
Max
Clock Parameters
tKHKH
Average clock cycle time (K,K,C,C)
Cycle to Cycle Period Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K, C→C)
Clock to clock (K→K, C→C)
Clock to data clock (K→C, K→C)
DLL lock time (K,C)
4.00
-
6.30
5.00
-
7.88
6.00
-
8.40
ns
ns
tKC var
0.20
0.20
0.20
1,5
8
tKHKL
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
tKLKH
-
-
-
ns
8
tKHKH
-
-
-
ns
9
tKHKH
-
-
-
ns
9
tKHCH
1.80
2.30
2.80
ns
tKC lock
tKC reset
Output Parameters
tCHQV
-
-
-
-
-
-
cycles
ns
2
K static to DLL reset
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output HIGH-Z
C HIGH to output LOW-Z
-
0.45
-
-0.45
-
0.45
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
tCHQX
-0.45
-
-
0.45
-
-
0.45
-
-0.50
-
-
0.50
-
tCHCQV
TCHCQX
TCQHQV
TCQHQX
TCHQZ
-0.45
-
-0.45
-
-0.50
-
0.30
-
0.35
-
0.40
-
-0.30
-
-0.35
-
-0.40
-
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
TCHQX1
Set-Up Time
tAVKH
-0.45
-0.45
-0.50
Address valid to K,K rising edge
0.50
0.50
0.35
-
-
-
0.6
0.6
-
-
-
0.7
0.7
-
-
-
ns
ns
ns
6
R, W inputs valid to K,K rising edge
tIVKH
tDVKH
Data-in and BWx/NWx valid to K,K rising edge
0.40
0.50
Hold Times
tKHAX
K, K rising edge to address hold
0.50
0.50
0.35
-
-
-
0.6
0.6
-
-
-
0.7
0.7
-
-
-
ns
ns
ns
6
tKHIX
K, K rising edge to R, W inputs hold
K, K rising edge to data-in and BWx/NWx hold
tKHDX
0.40
0.50
6431 tbl 11
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65
(EIA/JESD65) pg.10
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V). It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
6.42
15
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
Write A3
(burst of 4)
10
Read A4
(burst of 4)
NOP
Read A0
(burst of 4)
2
Write A2
(burst of 4)
8
Read A1
(burst of 4)
4
NOP
NOP
(Note 1)
7
11
13
9
12
1
3
6
5
K
tKHKL
tKHKH
tKLKH
tKHKH
K
Note 2
LD
tIVKH
tKHIX
Note 1
R/W
A3
A2
A1
A4
SA
DQ
A0
tAVKH tKHAX
tKHDX
tDVKH
tKHDX
tDVKH
Q02
Q03
Q13
Q01
Q00
Q0
Q1
Q12
Qx3
D33
D20
D30
D32
Q40
D23
D31
D22
D21
tKHCH
tCHQV
tCQHQV
tCQHQX
tCHQZ
tCHQV
tKHCH
tCHQX
tCHQX
tCHQX1
C
tKHKH
tKHKH
tKLKH
tKHKL
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6431 drw 09
NOTE:
1. If R/W is low on the second rising edge of K after a Read request, the device automatically performs a NOP (No Operation.)
2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus
contention.
61.462
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
IEEE 1149.1 Test Access Port and Boundary Scan-JTAG
This part contains an IEEE standard 1149.1 Compatible TestAccess required. It is possible to use this device without utilizing the TAP. To
Port (TAP). The package pads are monitored by the Serial Scan disable theTAPcontroller without interfacing with normal operation of the
circuitry when in test mode. This is to support connectivity testing during SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
manufacturingandsystemdiagnostics. InconformancewithIEEE1149.1, TDI are designed so an undriven input will produce a response identical
the SRAM contains aTAPcontroller, Instruction register, Bypass Regis- to the application of a logic 1, and may be left unconnected, but they may
ter and ID register. TheTAPcontroller has a standard 16-state machine also be tied to VDD through a resistor. TDO should be left unconnected.
that resets internally upon power-up; therefore, the TRST signal is not
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
Instruction
EXTEST
TDO Output
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IDCODE
2
1
5
4
5
5
SAMPLE-Z
RESERVED
SRAM
CORE
SAMPLE/PRELOAD Boundary Scan register
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
BYPASS Reg.
TDO
Bypass Register
3
Identification Reg.
6431 tbl 13
NOTES:
Instruction Reg
Control Signal
TAP Controller
.
1. Places DQs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial
shift of the external TDI data.
s
TMS
TCK
3. Bypass register is initialized to Vss when BYPASS instruction is in
voked. The Bypass Register also holds serially loaded TDI when
existing the Shift DR states.
6431 drw 18
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Select IR
Run Test Idle
Select DR
0
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift IR
1
Shift DR
1
0
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause IR
1
Pause DR
1
0
0
0
Exit 2 DR
1
Exit 2 IR
1
0
1
Update DR
0
Update IR
1
6431 drw 17
6.42
17
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Scan Register Definition
Part
Instrustion Register
Bypass Register
ID Register
32 bits
Boundry Scan
107 bits
512Kx36
1Mx18
3 bits
3 bits
3 bits
1 bit
1 bit
1 bit
32 bits
107 bits
2Mx8/x9
32 bits
107 bits
6431 tbl 14
Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
DESCRIPTION
PART NUMBER
Revision Number (31:29)
0x0
Revision Number
0x0290
0x0291
0x0292
0x0293
512Kx36
1Mx18
2Mx9
DDRII BURST OF 4
71P73604S
71P73804S
71P73104S
71P73204S
Device ID (28:12)
2Mx8
Allows unique identification of SRAM
vendor.
IDT JEDEC ID CODE (11:1)
0x033
1
ID Register Presence
Indicator (0)
Indicates the presence of an ID register.
6431 tbl 15
61.482
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Boundary Scan Exit Order (2M x 8-Bit, 2Mx9-Bit, 1Mx18-Bit)
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
PIN ID
ORDER
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
73
2
6P
74
10C
11D
9C
3
6N
75
4
7P
76
5
7N
77
9D
6
7R
78
11B
11C
9B
7
8R
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
3G
2G
1J
83
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
8A
89
11L
11M
9L
7A
90
7B
91
6B
92
10L
11K
10K
9J
6A
93
5B
94
5A
95
4A
96
9K
5C
97
10J
11J
4B
98
3A
99
2N
2P
11H
10G
9G
1H
1A
100
101
102
103
104
105
106
107
1P
2B
11F
11G
9F
3R
4R
4P
3B
1C
1B
10F
11E
10E
3D
5P
3C
5N
5R
1D
6431 tbl 16
6431 tbl 17
6431 tbl 18
6.42
19
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Boundary Scan Exit Order (512K x 36-Bit)
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
10E
11C
9D
ORDER
1
PIN ID
6R
ORDER
73
PIN ID
3C
3E
1E
2E
2D
3F
2
6P
74
3
6N
75
4
7P
76
9C
5
7N
77
6
7R
11D
11B
10B
9B
78
7
8R
79
1F
8
8P
80
1G
2F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
9P
10C
11A
Internal
9A
82
3G
2J
83
10N
10P
11M
9N
84
1J
85
2G
3K
1K
2K
3J
8B
86
7C
87
9M
11N
11L
10L
9L
6C
88
8A
89
7A
90
3L
1L
1M
2L
3N
2M
1N
3M
3P
7B
91
6B
92
10M
11K
9K
6A
93
5B
94
5A
95
9J
4A
96
10K
11J
9G
5C
97
4B
98
3A
99
1P
11H
10G
10J
11F
10F
9F
1H
100
101
102
103
104
105
106
107
2P
1A
2N
3R
4R
4P
3B
1B
1C
2B
11G
11E
9E
5P
3D
5N
5R
2C
1D
6431 tbl 16b
6431 tbl 17b
6431 tbl 18b
62.402
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
JTAG DC Operating Conditions
Parameter
Output Power Supply
Symbol
Min
1.4
1.7
1.3
-0.3
-5
Ty p
Max
1.9
Unit Note
V
DDQ
DD
IH
IL
IL
IL
0L
OH
OL
-
1.8
-
V
V
Power Supply Voltage
Input High Level
V
1.9
V
VDD+0.3
0.5
V
Input Low Level
V
-
V
TCK Input Leakage Current
TMS, TDI Input Leakage Current
TDO Output Leakage Current
Output High Voltage (IOH =-1mA)
Output Low Voltage (IOL = 1mA)
NOTE:
I
-
+5
µA
µA
µA
I
-15
-5
-
+15
I
-
+5
1
V
V
DDQ - 0.2
-
VDDQ
V
V
1
V
VSS
-
0.2
6431 tbl 19
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the
external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
Min
1.8
Unit
V
Note
Input High Level
Input Low Level
V
IH
VIL
0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
0.9
ns
V
Input and Output Timing Reference Level
1
6431 tbl 20
NOTE:
1. For SRAM outputs see AC test load on page 14.
JTAG Input Test Waveform
1.8 V
JTAG AC Test Load
0.9 V
Test points
0.9 V
0.9 V
0 V
50Ω
6431 drw 23
Z0 = 50Ω
TDO
,
6431 drw 25
JTAG Output Test Waveform
Test points
0.9 V
0.9 V
6431 drw 24
6.42
21
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
TCK Cycle Time
t
CHCH
CHCL
CLCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CLQV
-
-
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
t
t
-
t
-
t
5
-
t
5
-
t
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
t
5
-
t
5
-
t
0
10
6431 tbl.21
JTAG Timing Diagram
TCK
tCHCH
t
CHCL
t
CLCH
t
MVCH
DVCH
t
CHMX
TMS
t
tCHDX
TDI/
SRAM
Inputs
tSVCH
tCHSX
SRAM
Outputs
tCLQV
TDO
6431 drw 19
62.422
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
23
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Ordering Information
IDT
71P73XXX
X
XXX
XX
Device
Type
Power Speed
Package
BQ
165 Fine Pitch Ball Grid Array (fBGA)
250
200
167
Clock Frequency in MegaHertz
IDT71P73204 2M x 8 DDR II SRAM Burst of 4
IDT71P73104 2M x 9 DDR II SRAM Burst of 4
IDT71P73804 1M x 18 DDR II SRAM Burst of 4
IDT71P73604 512K x 36 DDR II SRAM Burst of 4
6431 drw 15
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
62.442
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18 x -Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Revision History
REV
DATE
PAGES
DESCRIPTION
0
07/29/05
p. 1-24
Released Final datasheet
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