IDT71T6280HS133BG [IDT]
QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165;
| 型号： | IDT71T6280HS133BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165 静态存储器 |
| 文件： | 总17页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9Mb Pipelined
QDR™ SRAM
Burst of 2
Advance
Information
IDT71T6280H
Features
Description
◆
9Mb Density (512Kx18)
The IDT71T6280H is a 2.5V Synchronous pipelined SRAM equipped
with QDR™ architecture. QDR architecture consists of two separate
ports to access the memory array. The Read port has dedicated Data
Outputs to support Read operations, and the Write Port has dedicated
Data inputs to support Write operations. Access to each port is accom-
plished through a common address bus. The Read address is latched
on the rising edge of the K clock and the Write address is latched on the
rising edge of K clock. QDR architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around” the data
bus required with common I/O devices. Accesses to the IDT71T6280H
Read and Write ports are completely independent of one another. All
accesses are initiated synchronously on the rising edge of the positive
input clock (K). In order to maximize data throughout, both Read and
Writeports are equipped with DoubleData Rate (DDR) interfaces. There-
fore, data can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising edge of the
output clock (C and C) thereby maximizing performance while simplifying
system design.
◆
Separate Independent Read and Write Data Ports
— Supports concurrent transactions
333MHz Data Rate for High Bandwidth Applications
Fast Clock-to ValidDR access times
◆
◆
— 2.5ns for 166MHz version
Double Data Rate (DDR) interfaces on both Read and Write
◆
ports (data transfered at 333MHz)
Two Input clocks (K and K), using rising edges only, for
◆
precise timing
◆
Two output register clocks (C and C) compensate for clock
skew and flight time mismatches
— Clock and data delivered together to receiving device
Single multiplexed address input bus latches address
◆
inputs for both READ and WRITE ports
Data forwarding feature provides most current data
Separate Port Selects for depth expansion
Internal synchronous self-timed three-state control
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
165-ball,1.0mm pitch 13mm x 15mm fBGA Package
Variable drive HSTL output buffers
◆
◆
◆
◆
Depth expansion is accomplished with a Port Select input for each
port. Each Port Select allow each port to operate independently.
All synchronous inputs pass through input registers controlled by the
K or K input clocks. All data outputs pass through output registers con-
trolled by the C or C input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
◆
◆
◆
◆
JTAG Interface
Variable Impedance HSTL.
◆
Pin Description Summary
A0 - A17
Address Inputs
Input
Input
Synchronous
Synchronous
Synchronous
Synchronous
N/A
Read Port Enable
RPE
Write Port Enable
Input
WPE
Individual Byte Write Selects
Clock signals for Data, Address and Control Inputs
Data Output Clocks
Data Input
Input
BW0, BW1
K, K
Input
C, C
Input
N/A
D0 D17
-
Input
Synchronous
Synchronous
Static
Q0 Q17
-
Data Output
Output
Input
ZQ
TMS, TDI, TCK
TDO
Output Impedance Matching Input
JTAG Inputs
Input
N/A
JTAG Output
Input
N/A
VREF
Reference Voltage Input
Core and Output Power
Ground
Input
Static
VDD, VDDQ
VSS
Supply
Supply
Static
Static
5285 tbl 01
FEBRUARY 2000
QDR SRAMs and Quad Data Rate comprise a new family of products developed by Cypress Semiconductor, IDT, Inc. and Micron Technology.
1
©2000IntegratedDeviceTechnology,Inc.
DSC-5285/01
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
I/O
Active
Description
Address inputs. Sampled on the rising edge of the K clock during active read and on the
rising edge of the K clock during active write operations. These address inputs are
multiplexed for both Read and Write operations. Internally, the device is organized 256Kx36
and delivered externally in two 18-bit words. Therefore, only 18 address inputs are needed
to access the entire memory array. These inputs are ignored when appropriate port is
deselected. Therefore, on the rising edge of the postive input clock (K), these inputs are
ignored if the Read port is deselected. These inputs are ignored on the rising edge of the
negative input clock (K) when the Write port is deslected.
A0 - A17 Address Inputs
Input
N/A
Read Port Enable. Sampled on the rising edge of positive input clock (K). When active, a
Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are
automatically three-stated following the next rising edge of the C clock. The IDT71T628H is
organized internally as 256Kx36. Each read access consists of a burst of two sequential 18-
bit transfers over one clock cycle. The entire burst of two data words should be allowed to
complete. Initiating Read accesses on two consecutive K clock rises is a valid operation
resulting in two consecutive Read operations.
Read port
Enable
Input
Low
RPE
Write Port Enable. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting will deselect the Write port. When deselected, the
pending access is allowed to complete. The IDT71T6280H is organized internally as
256Kx18. Each write access consists of a burst of two sequential 18-bit transfers over one
clock cycle. The entire burst of two data words should be allowed to complete. Initiating
Write accesses on two consecutive K clock rises is a valid operation resulting in two
consecutive Read Operations.
Write Port
Enable
Input
Input
Low
Low
WPE
Byte Write Enables 0 and 1. Sampled on the rising edge of the K and K clocks during write
operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered. BW0 controls D[8:0] while BW1
controls D[17:9]. BW0 and BW1 are sampled on same edge as D[17:0]. Deselecting a Byte
Write Enable will cause the corresponding byte of data to be ignored and not written into
the device.
Individual Byte
BW0 , BW1
Write Enables
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
(data, address and control) to the device and drive out data through Q[17:0} when in single
clock mode.
K
Master Clock
Master Clock
Input
Input
N/A
N/A
Negative Input Clock Input. K is used to capture synchronous inputs (data, address and
control) being presented to the device and drive out data through Q[17:0] when in single
clock mode. All accesses are initiated on the rising edge of K.
K
Positive Output Clock Input. C is used in conjuction with C clock out the Read data from the
device. C and C can travel with the data to the receiving device. When used in this way C and
C can be used to de-skew the flight times of various devices on the board (see application
example).
Output Data
Clock
C
Input
N/A
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can travel with the data to the receiving device. When used in this
way C and C can be used to de-skew the flight times of various devices on the board (see
application example).
Output Data
Clock
Input
Input
N/A
N/A
N/A
C
Data Input signals, sampled on the rising edge of K and K clocks during the data portion of
a valid write operation.
D0 - D17
Q0 - Q17
Data Input
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations (or
K and K when in single clock mode). When the read is deselected, Q[17:0} are
automatically tri-stated.
Data Output
Output
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. Q [17:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected to
directly to VDD, which enables the minimum impedance mode. This pin cannot be
connected directly to Vss or left unconnected.
Programmable
Impedance
Matching
ZQ
Input
N/A
5285 tbl 02a
Pin Descriptions continued on Page 3.
6.242
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function
I/O
Active
Description
Test Mode
Select
N/A
TMS
Input
Gives input command for TAP controller; sampled rising edge of TCK.
Te s t Data
Input
N/A
N/A
N/A
TDI
Input
Input
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK.
Clock input ofTAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from falling edge of TCK.
TCK
TDO
Test Clock
Te s t Data
Output
Serial output of registers placed between TDI and TDO. This output is active dpending on
state of TAP controller.
Output
Input
I/O
Reference
Voltage
REF
V
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as A/C measurement points.
N/A
N/A
Core Power
Supply
VDD
N/A
Power supply inputs to the core of the device. Should be connected to 2.5V power supply.
I/O Power
Supply
Power supply inputs for the outputs of the device. Should be connected to 1.5V power
supply.
VDDQ
VSS
N/A
N/A
N/A
N/A
Core Ground
Ground for the core of the device. Should be connected to ground of the system.
5285 tbl 02
Introduction
Functional Overview
onto the Q[17:0]. The requested data will be valid 2.5ns from the rising
edge of the output clock (C or C, 166MHz device). With the separate
Input and Output ports and the internal logic determining when the device
should drive the data bus, the QDR architecture has eliminated the need
for an output enable input to control the state of the output drivers.
Read accesses can be initiated on every rising edge of the positive
input clock (K). Doing so will pipeline the data flow such that data is
transferred out of the device on every rising edge of the output clocks (C
and C). The IDT71T6280H will deliver the most recent data for the
address location being accessed. This includes forwarding data when a
Readand Write transactions tothesameaddress locationareinitiatedon
the same clock rise.
When the read port is deselected, the IDT71T6280H will first com-
plete the pending read tansactions. Synchronous internal circuitry will
automatically three-state the outputs following the next rising edge of the
positive output clock (C). This will allow for a seamless transition between
devices without the insertion of wait states.
The IDT71T6280H is equipped with internal logic that synchronously
controls the state of the output drivers. The logic inside the device deter-
mines when the output drivers need to be active or inactive. This ad-
vancedlogiceliminatestheneedforanasynchronousoutputenable(OE)
sincethedevicewillautomaticallyenable/disabletheoutputdriversduring
the proper cycles. The IDT71T6280H will automatically power-up in a
deselctedstatewiththeoutputsinathreestatecondition.
The IDT71T6280H is a synchronous pipelined Burst SRAM equipped
with both a Read Port and a Write Port. The Read port is dedicated to
ReadoperationsandtheWritePortisdedicatedtoWriteoperations. Data
flows into the SRAM through the Write port and out through the Read
Port. The IDT71T6280H multiplexes the address inputs in order to min-
imize the number of address pins required. The IDT71T6280H latches
the Read address on the rising edge of the positive input clock (K) and
latches the Write address on the rising edge of the negative input clock
(K). By having separate Read and Write ports, the IDT71T6280H com-
pletely eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Accesses for both ports are initiated by the positive input clock (K). All
synchronous input timing is referenced from the rising edge of the input
clocks (K andK) and all output timing is referenced to the output clocks, C
and C (or K and K when in single clock mode.)
All synchronous data inputs (D[17:0]) inputs pass through input reg-
isters controlled by the input clocks (K and K). All synchronous data
outputs (Q[17:0]) outputs pass through output registers controlled by the
rising edge of the output clocks (C and C).
All synchronous control (RPE, WPE, BW0, BW1) inputs pass through
input registers controlled by the rising edge of the input clocks (K andK).
Read Operations
Read operations are initiated by asserting RPE active at the rising
edge of the positive input clock (K). The address presented to A[17:0] is
stored in the Read address register. Because theIDT71T6280His a 36-
bit memory, it will access two 18-bit data words with each read operation.
FollowingthenextK clockrise the dataisavailabletobelatched out ofthe
device, triggered by the C clock. On the following C clock rise the
corresponding lower order word of data is driven onto the Q[17:0]. On
the subsequent rising edge of C the higher order data word is driven
Write Operations
Write operations are initiated by asserting WPE active at the rising
edge of the positive input clock (K). On the same clock rise (K) the data
presented to D[17:0] is stored into the lower 18-bit Write Data register
provided BW[1:0] are both asserted active. On the subsequent rising
edge of the negative input clock (K), the information presented to A[17:0]
Introduction continued on Page 4.
6.42
3
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Introduction continued
is latched and stored in the Write Address Register and the information Concurrent Transactions
presented to D[17:0] is also stored into the upper 18-bit Write Data Reg-
ister provided BW[1:0] are both asserted active. The 36 bits of data are independently of one another. Since each port latches the address inputs
then written into the memory array at the specified location. on different clock edges, the user can Read or Write to any location,
The Read and Write ports on the IDT71T6280H operate completely
Writeaccessescanbeinitiatedoneveryrisingedgeofthepositiveclock. regardless of the transaction on the other port. Should the Read and
Doingsowillpipelinethedataflowsuchthat18-bitsofdatacanbetransferred Write ports access the same location on the rising edge of the positive
into the device on every rising edge of the input clocks (K andK).
input clock, the information presented to the D[17:0] will be forwarded to
Byte Write operations are supported by the IDT71T6280H. A write the Q[17:0] such that no latency is required to access valid data. Coher-
operation is initiated by selecting the write port using WPE. Thebytes that ency is conducted on cycle boundaries. Once the second word of data is
are written are determined by BW0 and BW1 which are sampled with latched into the device, the write operation is considered completed. At
each set of 18-bit data word. Asserting the appropriate Byte Write Enable this point, any access to that address location will receive that data until
input during the data portion of a write will allow the data being presented altered by a subsequent Write operation. Coherency is not maintained
to be latched and written into the device. De-asserting the Byte Write for Write operations initiated in the cycle after a Read.
Enable input during the data portion of a write will allow the data stored in
the device for that byte to remain unaltered. This feature can be used to Depth Expansion
simplify READ/MODIFY/WRITE operations to a Byte Write operation.
When deselected, the write port will ignore all inputs.
The IDT71T6280H has a Port Select input for each port. This allows for
easydepthexpansion.BothPortSelectsaresampledontherisingedgeofthe
positiveinputclockonly(K).Eachportselectinputcandeselectthespecified
port. Deselectingaportwillnotaffecttheotherport. Allpendingtransactions
Single Clock Mode
The IDT71T6280H can be used with a single clock mode. In this (ReadandWrite)willbecompletedpriortothedevicebeingdeselected.
mode the device will recognize only the pair of input clocks (K and K) that
control both the input and output registers. This operation is identical to
Programmable Impedance
the operation if the device had zero skew between the K/K and C/C
clocks. All timing parameters remain the same in this mode. To use this
mode of operation, the user must tie C and C to VDD. During power-up,
the device will sense the single clock input and operating in either single
clock or double clock mode. The clock mode should not be changed
during device operation.
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and VSSto allow the SRAM to adjust its output driver imped-
ance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM, The allowable range of RQ to guar-
antee impedance matching with a tolerance of +/-10% is
between 175W and 350W, with VDDQ=1.5V. The output impedance is
adjusted every 1024 cycles to adjust for drifts in supply voltage and
temperature.
6.442
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Functional Block Diagram
D[17:0]
18
Write
Write
Data Reg
Data Reg
Address
Register
A
Address
Register
A
18
18
256Kx18 256Kx18
Memory
Array
Memory
Array
K
CLK
Gen.
RPE
Control
Logic
K
C
Read Data Reg.
36
C
18
VREF
WPE
18
18
Reg.
18
Reg.
Reg.
Control
Logic
18
0
BW
Q[17:0]
1
BW
5285 drw 01
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Ambient
VSS,
Symbol
Parameter
Min.
Typ.
Max.
Unit
Grade
VDD
VDDQ
Temperature(1 )
VSSQ
Power Supply
Voltage
VDD
VDDQ
VSS
VIH
2.4
1.4
0
2.5
1.5
0
2.6
1.9
0
V
V
V
V
Commercial
0°C to +70°C
OV 2.5 ± 100mV 1.4V to 1.9V
5285 tbl 03
I/O Supply Voltage
Ground
NOTE:
1. TA is the “instant on” case temperature.
+0.1
+0.3
Input High Voltage
Input Low Voltage
VREF
–
VDDQ
–0.1
VIL
–0.3(1 )
–
VREF
V
5285 tbl 04
NOTE:
1. -2.0V for pulse duration less than 20ns.
6.42
5
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Pin Configuration
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
6
K
7
8
9
10
11
(2)
(1)
(1)
(2)
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
NC
SS
WPE
BW1
NC
RPE
A
B
C
D
E
F
Q
9
D
9
A
16
K
A
17
NC
Q
8
BWO
NC
D
10
V
SS
A
2
A
0
A
1
V
SS
Q
7
D
8
D
11
Q
10
V
SS
V
SS
V
SS
V
SS
V
SS
NC
D
7
NC
Q
11
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
D
6
Q
6
Q
12
D
12
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
NC
NC
Q
5
D
13
Q
13
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
5
G
H
J
V
V
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
V
REF
ZQ
REF
NC
NC
DDQ
DDQ
NC
NC
NC
NC
NC
NC
D
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
4
D
4
Q
14
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
D
3
Q
3
K
L
Q
15
D
15
V
DDQ
V
SS
V
SS
V
SS
V
DDQ
NC
Q
2
NC
D
16
V
SS
V
SS
V
SS
V
SS
V
SS
Q
1
D
2
M
N
P
R
D
17
Q
16
V
SS
A
3
A
A
5
V
SS
NC
D
1
4
C
C
NC
Q
17
A
6
A
7
A
8
A
9
D
0
Q
0
TCK
A
10
A
11
A
12
A
13
A
14
A
15
TMS
TDI
5285 tbl 12
165-ball FBGA Pinout
TOP VIEW
NOTE:
1. 9A and 3A are reserved for future 18M and 36M respectively.
2. 10A and 2A are reserved for future 72M and 144M respectively. This should
be connected to Vss on the IDT71T6280H.
6.642
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Absolute Maximum Ratings(1)
Symbol
Rating
Value
Unit
Symbol
CIN
Parameter
Input Capacitance
Conditions
Max.
Unit
pF
(2)
VTERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +3.6
V
5
6
7
VDD = 2.5V
VDDQ = 1.5V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
(3)
DC Input Voltage(5 )
VTERM
–0.5 to VDDQ+0.5
V
V
pF
(4)
VTERM
DC Voltage Applied to Outputs in –0.5 to VDDQ+0.5
High-Z State(5 )
5285
tbl 06
NOTE:
1. Tested initially and after any design or process change that may affect these
parameters.
TA
Operating Temperature
Temperature Under Bias
Storage Temperature
0°C to 70°C
–55 to +125
–65 to +150
20
°C
°C
°C
mA
V
TBIAS
TSTG
IOUT
VESD
Current into Outputs (Low)
Static Discharge Voltage
>2001
(per MIL-STD-883, Method 3015)
ILU
Latch-Up Current
>200
mA
5285 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VDD terminals only.
3. Input terminals.
4. Output terminals.
5. Minimum voltage equals –2.0V for pulse duration less than 20ns.
6.42
7
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Application Example
R=250
Ω
R=250
Ω
ZQ
Q
ZQ
SRAM #4
DOUT
SRAM #1
DIN
VTERM = 0.75V
DIN
18
18
18
R = 50
Ω
18
72
Q
Din
72
Add.
Cntr.
2
CLK
CLK/
(input)
CLK
CLK/
(output)
2
5285 drw 03
R = 50
Ω
T
REF
V = V /2
The information contained herein is subject to change without notice. IDT, Cypress and Micron assume no responsibility for theuse of any circuitry other than circuitry embodied in their respective semiconductor
product. Nor does it convey or imply any license under patent or other rights. IDT, Cypress and Micron do not authorize its products for use as critical components in life-support systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user. The inclusion of IDT, Cypress or Micron products in life-support systems application implies that the manufacturer assumes all risk
of such use and in doing so indemnifies IDT, Cypress and Micron against all charges.
6.842
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Read Port Cycle Description Truth Table(1,2)
RPE
Operation
Address Used
K
Comments
Deselected
—
H
L–H
Read port is deselected. Outputs three-state following nextrising edge of negative input
clock (K) if in single clock mode, or C if using C and C as output clocks.
Begin Read
External
L
L–H
Read operation initiated. Addresses are stored in the Read Address Register. Following the
next K clock rise the first (lower order) 18-bit word will be available to be driven out onto
Q[17:0] gated by the rising edge of the output clock C. On the subsequent rising edge of the
negative output clock (C) the second (higher order) 18-bitword is driven out onto Q[17:0].
5285 tbl 07
Write Port Cycle Description Truth Table(1,2,3,4,5)
WPE
Operation
Address Used
K
Comments
Deselected
—
H
L–H
WPE deselects Write Port. All Write Port inputs are ignored during this clock rise and the
subsequent rising edge of the negative input clock (K).
Begin Read External on next
L
L–H
Write operation initiated. The information presented to D[17:0] is stored in the Write Data
Register. On the subsequent rising edge of the negative input clock (K) the device will latch
the addresses presented to A[17:0] and the data presented to D[17:0]. The entire 36 bits of
information will then be written into the memory array. See Write Description table for byte
write information.
rising edge of K
5285 tbl 08
NOTES:
1. X = Don’t Care, H = Logic High, L = Logic Low.
2. Device will power-up deselected and the outputs in a three-state condition.
3. BW0 and BW1 asserted active LOW during all cycles. For byte write operations, see Write Description table.
4. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
5. It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Write Descriptions(1)
Operation
BW
0
BW
1
K
K
Comments
Write Initiated
L
L
L–H
—
Both bytes (D[17:0]) are written into the low order 18-bit write buffer
device during this portion of a write operation.
Both bytes (D[17:0]) are written into the higher order 18-bit write
buffer device during this portion of a write operation. The
contents of the entire 36-bits write buffer are written into the
memory array.
Write Completed —
Write initiated on
previous K clock rise
L
L
—
L–H
Write Initiated
L
L
H
H
L–H
—
—
During the Data portion of a Write sequence, only the lower byte
(D[8:0]) is written into the device. D[17:9] will remain unaltered.
Write Completed —
Write initiated on
L–H
During the Data portion of a Write sequence, only the lower byte
(D[8:0]) is written into the device. D[17:9] will remain unaltered.
previous K clock rise
Write Initiated
H
H
L
L
L–H
—
—
During the Data portion of a Write sequence, only the upper byte
(D17:9]) is written into the device. D[8:0] will remain unaltered.
Write Completed —
Write initiated on
L–H
During the Data portion of a Write sequence, only the upper byte
(D[17:9]) is written into the device. D[8:0] will remain unaltered.
previous K clock rise
Write — NO-OP
Write — NO-OP
NOTE:
H
H
H
H
L–H
—
—
No data is written into the device during this portion of a write
operation.
L–H
No data is written into the device during this portion of a write
operation.
tbl 09
5285
1. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BW0 and BW1 can be altered on different portions of a write cycle, as
long as the set-up and hold requirements are achieved.
6.42
9
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 2.5 ± 100mV, VDDQ = 1.4V to 1.9V)
Symbol
|ILI
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
--
Max.
Unit
µA
µA
V
|
GND
GND
V
V
5
5
≤
≤
I ≤ DD
VDDQ, Output Disabled
I ≤
|I
V
--
LO
|
V
OL
IOL = 2.0mA, Nominal Impedance
IOH = –2.0mA, Nominal Impedance
Typical Value = 0.75V
V
SS
VDDQ/2–0.3
V
OH
Output High Voltage
Input Reference Voltage
V
DDQ/2+0.3
V
DDQ
V
V
REF
0.68
0.9
V
5285 tbl 10a
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 2.5 ± 100mV, VDDQ = 1.4V to 1.9V)
Symbol
Parameter
DD Operating Supply
Test Conditions
S166
S133
S100
Unit
IDD
V
VDD = Max., IOUT = 0mA,
f = fMAX(2) = 1/tCYC
550
450
330
mA
I
SB1
Automatic Power-Down Current Max. VDD, Both Ports Deselected,
100
80
60
mA
Inputs Static, V ≥ V or V ≤ V ,
IN
IH
IN
IL
f = fMAX(3) = 1/tCYC
5285 tbl 10b
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. Clock Inputs.
AC Test Conditions
AC Test Loads
Input Pulse Levels
0.25V to 1.25V
V
DDQ/2
VREF
Input Rise/Fall Times
2ns
0.75V
OUTPUT
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
=50
Ω
Z
0
Device
Under
Test
Ω
RL = 50
0.75V
R=250
Ω
See Figures a and b
REF = 0.75V
V
ZQ
5285tbl 11a
5285 drw 04
Including scope and jig.
(1)
(a)
ALL INPUT PULSES
1.25V
0.75V
VDDQ
/2
0.25V
5285 drw 06
V
REF
V
DDQ
/2
Ω
R=50
NOTE:
1. Unless otherwise noted, test conditions assume signal transition time of 2V/
ns, timing reference levels of 0.75V, VDDQ = 1.5V, input pulse levels of
0.25V to 1.25V, and output loading of the specified IOL/IOH and load
capacitance showing in (a) of AC Test Loads.
OUTPUT
Device
Under
Test
5
pF
R=250
Ω
ZQ
5285 drw 05
Including scope and jig.
(b)
61.402
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
(1,2,3)
AC Electrical Characteristics (VDD = 2.5 ± 100mV, VDDQ = 1.4V to 1.9V)
IDT71T6280HS166 IDT71T6280HS133 IDT71T6280HS100
Min.
Max
Min.
Max
Min.
Max
Symbol
Parameter
Unit
Clock Parameters
tCY C
tCH
tCL
K Clock and C Clock Cycle Time
Input Clock (K/ and C/ ) High Pulse Width
6.0
2.4
2.4
2.7
—
—
—
3.3
7.5
3.2
3.2
3.4
—
—
—
4.1
10.0
3.5
3.5
4.4
—
—
—
5.4
ns
ns
ns
ns
K
C
Input Clock (K/K and C/C) Low Pulse Width
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise
(Rising Edge to Rising Edge)
tKHKH
tKHCH
K/K Clock Rise to C/C Clock Rise (Rising Edge to Rising Edge)
0.0
2.0
0.0
2.5
0.0
3.0
ns
Output Parameters
tCD
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
—
1.2
1.2
2.5
—
—
—
1.2
1.2
3.0
—
—
—
1.2
1.2
3.0
—
—
ns
ns
ns
tCDC
Data Output Hold After Output C/C Clock Rise (Active to Active)
Clock (C and C) Rise to Low-Z
(1,2,4)
tCL Z
(1,2,4)
Clock (C and C) Rise to High-Z (Active to High-Z)
—
2.5
—
3.0
—
3.0
ns
tCHZ
Set-Up Times
tSA
Address Set-Up to Clock (K and K) Rise
0.7
0.7
0.7
0.7
0.7
—
—
—
—
—
0.8
0.8
0.8
0.8
0.8
—
—
—
—
—
1.0
1.0
1.0
1.0
1.0
—
—
—
—
—
ns
ns
ns
ns
ns
tSD
D[17:0] Set-Up to Clock (K and K) Rise
RPE Set-Up to Clock K Rise
tSR
tSW
WPE Set-Up to Clock K Rise
tSB
BW0, BW1 Set-Up to Clock K and K Rise
Hold Times
tHA
Address Hold After Clock (K and K) Rise
D[17:0] Hold After Clock (K and K) Rise
RPE Hold After Clock K Rise
0.7
0.7
0.7
0.7
0.7
—
—
—
—
—
0.8
0.8
0.8
0.8
0.8
—
—
—
—
—
1.0
1.0
1.0
1.0
1.0
—
—
—
—
—
ns
ns
ns
ns
ns
tHD
tHR
tHW
WPE Hold After Clock K Rise
tHB
BW0, BW1 Hold After Clock K and Rise
K
5285 tbl 11
NOTES:
1. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VDDQ = 1.5V, input pulse levels of 0.25V to
1.25V, and output loading of the specified IOL/IOH and load capacitance showing in (a) of AC Test Loads.
2. tCHZ and tCLZ are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured ±100mV from steady-state voltage.
3. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
4. These parameters are guaranteed with the AC load (part b) by device characterization. They are not production tested.
6.42
11
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Timing Waveform of Read/Deselect Cycle
tKHKH
CYC
t
tKHKH
K
CH
t
tCL
K
tCH
CL
t
tSA
A[17:0]
A
B
C
tHA
tSR
tHR
RPE
CLZ
t
Q[17:0]
(A+1)
Q
(B)
Q
(B+1)
CHZ
(C)
Q
(C+1)
Q
(A)
Q
Q
tCLZ
t
CD
t
tCDC
tKHCH
C
tKHKH
CDC
t
CD
t
C
5285 drw 07
Device originally deselected.
Activity on the Write Port is
unknown.
Don't Care
Undefined
=
=
61.422
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Timing Waveform of Write/Deselect Cycle
CYC
t
tCH
K
tCL
K
tCL
tSA
A[17:0]
C
A
B
HA
t
HW
t
SW
t
WPE
HB
t
tSB
BWX
(A+1)
D
(B)
D
(B+1)
D
D(C)
(C+1)
D
D[17:0]
D(A)
.
tSD
HD
t
5285 drw 08
BWx is both BW0 and BW1.
Don't Care
Undefined
=
=
6.42
13
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Timing Waveform of Combined Read and Write Cycles
K
K
A[17:0]
WPE
RPE
A
B
G
C
B
E
D
BWX
DATA IN
[17:0]
(C)
(B)
D
(B+1)
D
D
(A)
D(A+1)
D(C+1)
D(D)
D(D+1)
D
Write Data Forwarded
DATA OUT
(E+1)
Q
(B)
Q
(B+1)
Q
Q(G)
(G+1)
Q
Q(E)
C
C
Read Port previously deselected. BWx assumed active.
5285 drw 09
= Don't Care
Undefined
=
61.442
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
Package Diagrams TBD
6.42
15
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Ordering Information
IDT
71T6280H
S
XX
PF
Device
Type
Power
Speed
Package
BF
165 Fine Pitch Ball Grid Array (fBGA)
100
133
166
Clock Frequency in MegaHertz
DATA RATE
PART NUMBER
t
CD PARAMETER
SPEED IN MEGAHERTZ
CLOCK CYCLE TIME
71T6280HS100BG
71T6280HS133BG
71T6280HS166BG
3.0 ns
3.0 ns
2.5 ns
100 MHz
133 MHz
166 MHz
10.0 ns
7.5 ns
6.0 ns
200 MHz
266MHz
333MHz
5285 drw 15
Advanced Datsheet:
“Advance Information” datasheets contain intial descriptions, subject to change, for products which are in development, including
features and block diagrams.
61.462
IDT71T6280H, 9 Mb (512K x 18-Bit) Pipelined SRAM with
QDR™ Architecture, Burst of 2
Advance Information
Commercial Temperature Range
Datasheet Document History
02/16/00
Created Datasheet
02/19/00 Pg 2,3,6 Modified Pin Defintions and Pin Configuration
Pg 7 Modified Absolute Max Ratings
Pg 10 Update DC Electrical Characteristics. Added Note #3.
Pg 11 Modified AC electrical Characteristics. Added Note #4.
Pg 12-14 ModifiedTiming Wave Diagrams
6.42
17
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