IDT71T75702S85PFGI [IDT]
ZBT SRAM, 512KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | IDT71T75702S85PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 512KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M x 18
2.5V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71T75902
Features
◆
◆
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
1M x 18 memory configuration
◆
◆
◆
◆
◆
◆
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
◆
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW2 control (May tie active)
◆
◆
◆
Green parts available, see Ordering Information
◆
Functional Block Diagram — 1M x 18
LBO
1M x 18 BIT
MEMORY ARRAY
Address
Address A [0:19]
D
D
Q
Q
CE1, CE2 CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
Clock
OE
Gate
TMS
Data I/O [0:15], I/O P[1:2]
TDI
TCK
5319 drw 01a
TDO
JTAG
TRST
(optional)
SEPTEMBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5319/10
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Description
Therearethreechipenablepins(CE1,CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three is not
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite
isinitiated.
TheIDT71T75902isa2.5Vhigh-speed18,874,368-bit(18Megabit)
synchronous SRAM organized as 1M x 18. It is designed to eliminate
deadbuscycleswhenturningthebusaroundbetweenreadsandwrites,
orwritesandreads.Thusithas beengiventhenameZBTTM,orZeroBus
Turnaround.
TheIDT71T75902hasanon-chipburstcounter. Intheburstmode,
the IDT71T75902 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
Address and control signals are applied to the SRAM during one
clockcycle,andonthenextclockcycletheassociateddatacycleoccurs,
be it read or write.
TheIDT71T75902containaddress,data-inandcontrolsignalregis-
ters.Theoutputsareflow-through(nooutputdataregister).Outputenable
istheonlyasynchronoussignalandcanbeusedtodisabletheoutputs
atanygiventime.
The IDT71T75902 SRAM utilize IDT’s high-performance CMOS
process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
AClockEnable(CEN)pinallowsoperationoftheIDT71T75902tobe
suspended as long as necessary. All synchronous inputs are
ignoredwhenCENishighandtheinternaldeviceregisterswillholdtheir
previous values.
PinDescriptionSummary
A0
-A19
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE , CE
1
2
, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
BW
CLK
Individual Byte Write Selects
Clock
1
, BW
2
ADV/LD
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
LBO
TMS
TDI
N/A
N/A
TCK
TDO
Test Clock
N/A
Test Data Output
JTAG Reset (Optional)
Sleep Mode
N/A
Asynchronous
Synchronous
Synchronous
Static
TRST
ZZ
I/O
0
-I/O31, I/OP1-I/OP2
Data Input/Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5319 tbl 01a
6.422
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
Commercial and Industrial Temperature Ranges
P2i.n5VDI/Oe, fBiunrsit tCioounntesr (a1nd) Flow-Through Outputs
Symbol
Pin Function
Address Inputs
Advance / Load
I/O Activ-
e
Description
A
0
-A19
I
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD
is sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs
is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at
rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
BW
1
-BW
2
cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW2) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle
later. BW
1-B2
can all be tied low if always doing write to the entire 18-bit word.
Chip Enables
LOW Synchronous active low chip enable. CE
1
and CE are used with CE
2
2
to enable the IDT71T75902 (CE1 or
CE1
, CE
2
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect
cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is
initiated.
CE
2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE
2
is used with CE
1
and CE2 to enable the chip. CE2 has inverted
polarity but otherwise identical to CE and CE2.
1
CLK
N/A This is the clock input to the IDT71T75902. Except for OE, all timing references for the device are made
with respect to the rising edge of CLK.
I/O
I/OP1-I/OP2
0
-I/O31 Data Input/Output I/O
N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
Linear Burst Order
Output Enable
I
I
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is
low the Linear burst sequence is selected. LBO is a static input, and it must not change during device
operation.
LBO
LOW Asynchronous output enable. OE must be low to read data from the IDT71T75902. When OE is HIGH the
I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write
cycles. In normal operation, OE can be tied low.
OE
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
N/A
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test Data Output
O
N/A
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75902 to
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A N/A 2.5V core power supply.
N/A N/A 2.5V I/O Supply.
N/A N/A Ground.
V
V
5319 tbl 02a
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.42
3
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedDCOperating
Conditions
Symbol
Rating
Commercial
Industrial
Unit
(2)
V
V
V
V
TERM
Terminal Voltage with
Respect to GND
V
Symbol
Parameter
Min. Typ.
2.375 2.5
2.375 2.5
Max.
2.625
2.625
0
Unit
V
-0.5 to +3.6
-0.5 to +3.6
(3,6)
(4,6)
(5,6)
V
DD
Core Supply Voltage
TERM
TERM
TERM
Terminal Voltage with
Respect to GND
V
V
V
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
0 to +70
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-40 to +85
V
DDQ I/O Supply Voltage
V
Terminal Voltage with
Respect to GND
V
SS
Ground
0
0
V
Terminal Voltage with
Respect to GND
____
V
IH
IH
IL
Input High Voltage — Inputs
Input High Voltage — I/O
Input Low Voltage
1.7
V
DD +0.3
V
V
1.7
V
DDQ +0.3(2)
0.7
V
____
____
Operating Ambient
Temperature
(7)
TA
oC
-0.3(1)
V
T
BIAS
STG
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
2.0
-55 to +125
-55 to +125
2.0
oC
oC
W
V
5319 tbl 03
T
NOTE:
P
T
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
IOUT
DC Output Current
50
50
mA
5319 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
RecommendedOperating
TemperatureandSupplyVoltage
Ambient
Grade
V
SS
V
DD
VDDQ
Temperature(1)
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Commerical 0 °C to +70 °C
Industrial -40 °C to +85 °C
OV
OV
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
5319 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
7. During production testing, the case temperature equals TA.
TQFPCapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
5
7
pF
CI/O
V
pF
5319 tbl 07
BGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5319 tbl 07a
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
6.442
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 1M x 18, 100 TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
DDQ
1
A10
NC
NC
80
79
78
77
2
3
V
4
VDDQ
V
NC
NC
I/O
I/O
SS
5
V
NC
I/OP1
I/O
I/O
V
V
I/O
I/O
V
SS
76
75
74
73
6
7
8
7
8
9
9
6
72
71
70
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
DDQ
DDQ
I/O10
I/O11
(1)
SS
5
4
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
SS
(1)
VDD
V
V
SS
DD
71T75902
PKG100
(2)
V
DD
VSS
ZZ
I/O
I/O
3
2
I/O12
I/O13
V
V
DDQ
SS
V
DDQ
VSS
I/O
I/O
NC
NC
V
V
NC
NC
NC
1
0
I/O14
I/O15
I/OP2
NC
VSS
SS
V
DDQ
NC
NC
NC
DDQ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5319 drw 02a
Top View
100 TQFP
NOTES:
1. Pins14and66donothavetobeconnecteddirectlytoVSS aslongasthe inputvoltageis<VIL.
2. Pin16doesnothavetobeconnecteddirectlytoVDD aslongastheinputvoltageis>VIH.
3. Pins38,39and43willbepulledinternallytoVDDifnotactivelydriven. TodisabletheTAPcontrollerwithoutinterferingwithnormaloperation,severalsettingsarepossible. Pins38,39
and43couldbetiedtoVDDorVSSandpin42shouldbeleftunconnected. OrallJTAGinputs(TMS,TDIandTCK)pins38,39and43couldbeleftunconnected“NC”andtheJTAG
circuitwillremaindisabledfrompowerup.
6.42
5
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configurations — 1M x 18, 119 BGA(1,2,3)
1
2
3
4
5
A8
A9
A13
6
7
A
B
C
D
E
F
V
DDQ
A6
A4
A3
A2
A19
A16
V
DDQ
NC
NC
I/O8
NC
CE2
A7
ADV/LD
NC
NC
NC
I/O7
CE2
A17
V
DD
NC
I/O9
NC
I/O10
NC
V
SS
SS
SS
NC
CE1
OE
V
SS
SS
SS
SS
SS
I/OP1
NC
V
V
V
V
V
V
V
DDQ
I/O6
NC
V
DDQ
I/O5
NC
G
H
J
NC
A18
BW2
SS
DD(2)
I/O11
V
R/W
I/O4
V
DDQ
V
DD
V
V
DD
V
SS(1)
SS
V
DD
V
DDQ
I/O3
NC
K
L
NC
I/O12
NC
V
SS
SS
SS
SS
SS
CLK
NC
V
NC
I/O2
NC
I/O1
NC
A12
A11
I/O13
V
BW1
M
N
P
R
T
V
DDQ
I/O15
NC
I/O14
NC
V
V
V
V
V
V
SS
SS
SS
V
DDQ
NC
I/O0
NC
ZZ
CEN
A1
I/OP2
A5
A0
NC
V
DD
V
SS(1)
LBO
(3)
NC
A10
A15
NC
A14
NC/TMS(3) NC/TDI(3)
NC/TDO(3) NC/TRST(3)
U
V
DDQ
NC/TCK(3)
V
DDQ
5319 tbl 25a
TopView
NOTES:
1. PinsR5andJ5donothavetobeconnecteddirectlytoVSS aslongastheinputvoltageis<VIL
2. PinJ3doesnothavetobeconnecteddirectlytoVDD aslongastheinputvoltageis>VIH.
3. U2,U3,U4andU6willbepulledinternallytoVDD ifnotactivelydriven.TodisabletheTAPcontrollerwithoutinterferingwithnormaloperation,severalsettingsarepossible. U2,U3,U4
andU6couldbetiedtoVDDorVSSandU5shouldbeleftunconnected. OrallJTAGinputs(TMS,TDI,andTCKandTRST)U2,U3,U4andU6couldbeleftunconnected“NC”and
theJTAGcircuitwillremaindisabledfrompowerup.
4. TRSTisofferedasanoptionalJTAGresetifrequiredintheapplication. Ifnotneeded,canbeleftfloatingandwillinternallybepulledtoVDD.
6.462
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
CEN
CE1
,
CE (5)
2
BWx
R/W
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
L
L
L
H
X
L
L
L
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D(7)
Q(7)
D(7)
L
X
H
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q(7)
(Advance burst counter)(2)
L
L
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
NOOP
HIZ
HIZ
DESELECT / NOOP
X
H
SUSPEND(4)
Previous Value
5319 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the
I/Osremainsunchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
BW
X
1
BW
X
2
OPERATION
R/W
H
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/OP1
WRITE BYTE 2 (I/O[8:15], I/OP2
NO WRITE
L
L
L
(2)
)
L
L
H
(2)
)
L
H
L
L
H
H
5319 tbl 09a
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5319 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42
7
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
1
1
0
0
1
0
0
1
1
Second Address
Third Address
1
1
0
1
0
0
1
1
0
1
Fourth Address(1)
1
0
0
1
0
5319 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A18)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
I/O [0:31], I/O P[1:2]
,
5319 drw 03a
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.482
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
CE (1)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
H
X
H
X
X
H
X
X
L
L
H
L
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
L
D
1
Load read
Burst read
n+1
X
Q0
n+2
A
1
L
Q0+1 Load read
n+3
X
X
L
H
X
L
L
Q1 Deselect or STOP
n+4
H
L
X
X
L
Z
NOOP
n+5
A
2
Z
Load read
Burst read
n+6
X
X
H
L
X
H
L
Q2
n+7
L
Q2+1 Deselect or STOP
n+8
A
3
L
X
X
X
X
X
X
X
L
Z
Load write
Burst write
n+9
X
X
L
H
L
X
L
L
D3
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A
4
L
D3+1 Load write
X
X
X
X
L
L
H
X
L
X
X
L
D4 Deselect or STOP
H
L
Z
NOOP
A
5
6
7
Z
Load write
Load read
Load write
Burst write
A
A
H
L
L
L
X
L
D5
L
L
Q
6
X
X
H
X
L
H
L
X
L
L
X
X
L
D7
A
8
X
X
L
D
7+1 Load read
Burst read
Q8+1 Load write
X
H
L
X
L
Q8
A
9
L
5319 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.42
9
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
ReadOperation(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
H
X
L
L
L
X
X
X
L
X
Address and Control meet setup
n+1
X
X
X
X
Q0
Contents of Address A0 Read Out
5319 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
H
X
X
X
X
H
X
H
L
L
X
X
X
X
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
Address and Control meet setup
Address A Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
H
H
H
H
L
Q
0
0
X
X
X
Q0+1
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
Q
0+2
0+3
Q
Address A0+3 Read Out, Load A
1
A
1
Q
0
Address A
Address A
0
1
Read Out, Inc. Count
Read Out, Inc. Count
X
H
L
X
L
Q
1
A
2
Q1+1
Address A1+1 Read Out, Load A2
5319 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
L
L
L
L
L
L
X
X
X
Address and Control meet setup
Write to Address A
n+1
X
X
X
X
X
D0
0
5319 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
L
X
X
X
X
L
L
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Address A Write, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
H
H
H
H
L
D0
0
X
X
X
D0+1
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
D
0+2
0+3
D
Address A0+3 Write, Load A
1
A
1
D0
Address A
Address A
0
1
Write, Inc. Count
Write, Inc. Count
X
X
L
H
L
X
L
D1
A
2
D1+1
Address A1+1 Write, Load A2
5319 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.1402
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
Address A
Clock n+1 Ignored
Address A Read out, Load A
Clock Ignored. Data Q
Clock Ignored. Data Q
0 and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
A
1
Q
Q
Q
0
0
1
X
X
H
H
L
0
0
0
is on the bus.
is on the bus.
0
A
2
3
4
Q
1
Address A
Address A
Address A
1
2
3
Read out, Load A
Read out, Load A
Read out, Load A
2
3
4
A
A
L
Q
Q
2
3
L
5319 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation with Clock Enable Used(1)
CE (2)
1
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
A
0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
H
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
Address A
Clock n+1 Ignored.
Write data D , Load A1.
0 and Control meet setup.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
A
1
D0
0
X
X
H
H
L
X
X
Clock Ignored.
Clock Ignored.
A
2
3
4
D1
Write Data D
Write Data D
Write Data D
1
, Load A
, Load A
, Load A
2
3
4
A
A
L
D2
2
L
D3
3
5319 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
11
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
CE (2)
1
I/O(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Z
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
A
0
Address A
Address A
Address A
Address A
0
0
1
1
and Control meet setup.
read out, Deselected.
and Control meet setup.
read out, Deselected.
X
H
L
Q
0
A
1
X
L
Z
X
X
H
H
L
Q
Z
Z
1
X
X
L
Deselected.
A
2
Address A
Address A
2
2
and Control meet setup.
read out, Deselected.
X
X
H
H
Q
2
X
Z
Deselected.
5319 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used(1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
H
H
L
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Z
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
A
0
Address A
Data D
Address A
Data D Write In, Deselected.
Deselected.
Address A
Data D Write In, Deselected.
Deselected.
0
and Control meet setup
X
X
L
H
L
X
L
D0
0
Write In, Deselected.
and Control meet setup
A
1
Z
1
X
X
X
X
L
H
H
L
X
X
L
D
Z
Z
1
1
A
2
2 and Control meet setup
X
X
X
X
H
H
X
X
D2
2
Z
5319 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.1422
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
LBO, JTAG and ZZ Input Leakage Current(1)
Output Leakage Current
___
___
___
|ILI
|
V
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VCC
30
5
µA
µA
V
|ILO
|
V
OL
OH
Output Low Voltage
IOL = +6mA, VDD = Min.
0.4
___
V
Output High Voltage
IOH = -6mA, VDD = Min.
2.0
V
5319 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
7.5ns
8.5ns
Com'l
Symbol
Parameter
Test Conditions
Unit
mA
mA
mA
Com'l
Ind
Ind
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
275
40
295
225
40
95
60
40
245
I
DD
(2)
V
IN > VIH or < VIL, f = fMAX
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
V
,
60
125
80
60
115
80
ISB1
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
(2,3)
f = fMAX
V
,
105
60
ISB2
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
mA
ISB3
(2,3)
V
IN > VHD or < VLD, f = fMAX
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN < VIH, VDD = Max., ZZ > VHD
40
60
60
mA
IZZ
(2,3)
V
IN > VHD or < VLD, f = fMAX
5319 tbl 22a
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ/2
AC Test Conditions
Input Pulse Levels
AC Test Load
0 to 2.5V
2ns
50Ω
Input Rise/Fall Times
I/O
Z0 = 50Ω
,
Input Timing Reference Levels
Output Reference Levels
Output Load
(VDDQ/2
)
5319 drw 04
Figure 1. AC Test Load
(VDDQ/2
)
6
5
4
Figure 1
5319 tbl 23
•
3
∆tCD
(Typical, ns)
2
•
•
1
•
•
20 30 50
80 100
200
5319 drw 05
Capacitance (pF)
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
13
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 2.5V±5%, Commercial and Industrial Temperature Ranges)
7.5ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
CYC
Clock Cycle Time
10
2.5
2.5
11
3.0
3.0
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
(1)
____
____
tCL
Output Parameters
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
7.5
8.5
ns
ns
ns
____
____
tCDC
2
2
(2,3,4)
(2,3,4)
____
____
3
3
tCLZ
____
____
Clock High to Data High-Z
Output Enable Access Time
5
5
ns
ns
ns
ns
tCHZ
____
____
tOE
5
5
(2,3)
____
____
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
tOLZ
____
____
(2,3)
OHZ
5
5
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
5319 tbl 24a
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 2.375V).
6.1442
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
.
6.42
15
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
,
6.1462
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
6.42
17
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
6.1482
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
6.42
19
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5319 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
Register Name
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
t
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
t
5(1)
ns
____
Note (1)
____
t
50
ns
I5319 tbl 03
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5319 tbl 01
NOTES:
1. Guaranteedbydesign.
2. ACTestLoad(Fig.1)onexternaloutputsignals.
3. RefertoACTestConditionsstatedearlierinthisdocument.
4. JTAGoperationsoccuratonespeed(10MHz). Thebasedevicemayrunatanyspeed
specifiedinthisdatasheet.
6.2402
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number.
IDT Device ID (27:12)
0x223
0x33
1
Defines IDT part number 71T75902
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
ID Register Indicator Bit (Bit 0)
I5319 tbl 02a
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5319tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
21
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Q
Q
,
5319 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
XXXX
S
XX
XX
X
X
X
Device
Type
Power Speed
Package
Tray
Tape & Reel
Blank
8
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
100-pin Plastic Thin Quad Flatpack (PKG100)
119 Ball Grid Array (BGG119)
PF
BG
75
85
Access time (tCD) in tenths of nanoseconds
IDT71T75902
1Mx18 Flow-Through ZBT SRAM
5319 drw 12
OrderablePartInformation
Speed
(ns)
Pkg.
Pkg.
Temp.
Grade
Orderable Part ID
Code
Type
75
71T75902S75BG
BG119
BG119
PBGA
PBGA
C
71T75902S75BG8
71T75902S75BGG
71T75902S75BGG8
71T75902S75PFG
71T75902S75PFG8
71T75902S75PFGI
71T75902S75PFGI8
71T75902S85BG
C
BGG119 PBGA
BGG119 PBGA
PKG100 TQFP
PKG100 TQFP
PKG100 TQFP
PKG100 TQFP
C
C
C
C
I
I
85
BG119
BG119
PBGA
PBGA
C
71T75902S85BG8
71T75902S85BGG
71T75902S85BGG8
C
BGG119 PBGA
BGG119 PBGA
C
C
5319t27.tbl
6.2422
IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
Rev
0
1
Date
05/25/00
08/24/01
Pages
Description
CreatedAdvanceInformationDatasheet
RemovedreferenceofBQ165package
Removedpageofthe165BGApinconfiguration
p. 1, 25
p. 8
p. 24
p. 7
p. 5-7
p. 21
Removed page of the 165 BGA package diagram outline
Corrected 3.3V to 2.5V in Note 3
Added clarification to JTAG pins, allow for NC. Added 36M address pin locations
Corrected100-pinTQFPpackagedrawing
2
3
4
5
10/16/01
12/21/01
05/29/02
06/07/02
p.1-4,7,14,21,22 AddedcompleteJTAGfunctionality.
p. 2,14
p. 14
p.1-26
p.5,6,14,15,25
p.6
Added notes for ZZ pin internal pulldown and ZZ leakage current.
Updated ISB3 power supply current from 40 to 60mA for all speeds.
ChangeddatasheetfromAdvancedinformationtofinalrelease.
AddedI-temptothedatasheet.
6
7
11/19/02
05/23/03
Updated165BGAtable.
8
04/01/04
p.1
Updated logo with new design.
p.5,6
p.7
Clarifiedambientandcaseoperatingtemperatures.
Updated I/O pin number order for the 119 BGA.
p.24
Updated 119BGA Package Diagram Drawing.
9
10
02/20/09
09/08/17
p.25
p.1-23
p. 1
Removed “IDT” from orderable parts number
RemovedIDT71T75702&512Kx36throughoutthedatasheet
InFeatures:Addedtext:"Greenpartsavailable,seeOrderingInformation"
Moved the FBD from page 3 to page 1 & the Pin Description Summary from page 1 to page 2
& the Pin Definitions from page 2 to page 3 in accordance with our standard datasheet format
Description text correctedgrammaticalerrors
p.2
p.2-3
Removed BW4 & replaced withBW2, removed I/OP4 and replaced with I/OP2 in the Pin Description
Summary&PinDefinitionstables
Updated“36-bitword”to“18-bitword”forBW1-BW2inPinDefinitions table
Removed Functional Block Diagram for 512K x 36
RemovedfBGAcapacitancetableasthispackageisnolongerofferedforthisdevice
Added IDTlogo, device & inaccordancewiththepackaging codeaddedPKG100
Removed Pin Configuration 512K x 36, PKG100
p.3
p.4
p.5
p.5
p.5
p.7
p.7
Removed footnote 4. for Pin Configuration 1M x 18, 119BGA
Removed Pin Configuration 512K X 36, 119BGA
Removed Description columns for BW3 and BW4 and removed Write Byte 3 and Write Byte 4 rows
fromPartialTruthTableforWritesandremovedfootnote3
Replaced P[1:4] with P[1:2] in Functional Timing Diagram
Removed 8.0ns column from DC Electrical Chars Table
Removed 8.0ns column from AC Electrical Chars Table
Removed BW1 - BW4 from all of the Timing Waveforms and replaced with BW1 - BW2
ChangesmadetotheJTAGIdentificationRegisterDefinitionsTableforInstruction
Field IDT Device ID (27:12), where Value 0x221 was removed and 71T75702 was removed
from the Description column
p.8
p.13
p.14
p.15-19
p.21
p.22
OrderingInformationaddedTray,T&RandGreenindicators
Updated package codes in Ordering Information for TQFP from PK100 to PKG100
& for BGA from BGA119 to BGG119
OrderingInformationremoved80speedgrade
AddedOrderablePartInformationfromidt.com
p.23-24
Removed Package Diagram Outlines for TQFP and BGA
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
800-345-7015 or 408-284-8200
fax:408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
23
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