IDT71T75902S85BGG [IDT]
ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, GREEN, PLASTIC, BGA-119;
| 型号： | IDT71T75902S85BGG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, GREEN, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总26页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71T75702
IDT71T75902
Features
◆
The IDT71T75702/902 contain address, data-in and control signal
registers.Theoutputsareflow-through(nooutputdataregister).Output
enable is the only asynchronous signal and can be used to disable the
outputsatanygiventime.
AClockEnable(CEN)pinallowsoperationoftheIDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignoredwhenCENishighandtheinternaldeviceregisterswillholdtheir
previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite
isinitiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode,theIDT71T75702/902canprovidefourcyclesofdataforasingle
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter
(ADV/LD = HIGH).
512K x 36, 1M x 18 memory configurations
◆
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
◆
◆
TM
◆
◆
◆
◆
◆
◆
◆
◆
◆
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
aroundbetweenreadsandwrites,orwritesandreads.Thustheyhave
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm
100-pinplasticthinquadflatpack(TQFP)aswellasa119 ballgridarray
(BGA).
TM
been given the name ZBT , or Zero Bus Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be
it read or write.
PinDescriptionSummary
A0-A19
Ad d re ss Inp uts
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/ O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
OE
Output Enable
W
R/
CEN
BW1 BW2 BW3 BW4
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
,
,
,
CLK
ADV/LD
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Tes t Mo de S el e ct
Test Data Input
Synchronous
Static
LBO
TMS
TDI
N/A
N/A
TCK
TDO
Te s t C loc k
N/A
Te s t D ata Outp ut
JTAG Reset (Optional)
Sleep Mode
N/A
Asynchronous
Synchronous
Synchronous
Static
TRST
ZZ
I/ O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input/Output
Co re Po wer, I/O Power
Ground
Supply
Supply
VSS
Static
5319 tbl 01
FEBRUARY 2009
1
©2004IntegratedDeviceTechnology,Inc.
DSC-5319/08
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
A0-A19
Address Inputs
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the
chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle
later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.
BW1-BW4
CE1, CE2
Chip Enables
LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71T75702/902
(CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a
deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after
deselect is initiated.
CE2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has
inverted polarity but otherwise identical to CE1 and CE2.
CLK
N/A This is the clock input to the IDT71T75702/902. Except for OE, all timing references for the device are
made with respect to the rising edge of CLK.
0
31
I/O -I/O
Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
I/OP1-I/OP4
LBO
LBO
is
Linear Burst Order
I
LOW Burst order selection input. When
is high the Interleaved burstsequence is selected. When
LBO
OE
low the Linear burst sequence is selected. LBO is a static input, and it must not change during device
operation.
Output Enable
I
LOW Asynchronous output enable. OE must be low to read data from the IDT71T75702/902. When OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
write cycles. In normal operation, OE can be tied low.
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
N/A
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of
the TAP controller.
Test Data Output
O
N/A
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
HIGH IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
This pin has an internal pulldown.
ZZ
Sleep Mode
DD
V
Power Supply
Power Supply
Ground
N/A N/A 2.5V core power supply.
N/A N/A 2.5V I/O Supply.
N/A N/A Ground.
VDDQ
SS
V
5319 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.422
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 512K x 36
LBO
512K x 36 BIT
MEMORY ARRAY
Address
Address A [0:18]
D
D
Q
Q
CE1, CE2 CE2
R/W
Control
CEN
ADV/LD
DI
DO
BWx
D
Q
Control Logic
Clk
Mux
Sel
Clock
Gate
OE
Data I/O [0:31], I/O P[1:4]
TMS
TDI
TCK
,
5319 drw 01
TDO
JTAG
TRST
(optional)
6.42
3
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram 1M x 18
LBO
1M x 18 BIT
MEMORY ARRAY
Address
Address A [0:19]
D
D
Q
Q
CE1, CE2 CE2
R/W
Control
CEN
ADV/LD
DI
DO
BWx
D
Q
Control Logic
Clk
Mux
Sel
Clock
OE
Gate
TMS
Data I/O [0:15], I/O P[1:2]
TDI
TCK
5319 drw 01a
,
TDO
JTAG
TRST
(optional)
RecommendedDCOperating
Conditions
Symbol
Parameter
Min. Typ.
2.375 2.5
2.375 2.5
Max.
Unit
V
VDD Core Supply Voltage
VDDQ I/O Supply Voltage
2.625
2.625
V
VSS
VIH
VIH
VIL
Ground
0
0
0
V
____
Input High Voltage — Inputs
Input High Voltage — I/O
Input Low Voltage
1.7
VDD +0.3
VDDQ +0.3(2 )
0.7
V
____
____
1.7
V
-0.3(1 )
V
5319 tbl 03
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Ambient
Grade
V
SS
V
DD
V
DDQ
Temperature(1)
Commerical 0 °C to +70 °C
Industrial -40 °C to +85 °C
OV
OV
2.5V ± 5% 2.5V ± 5%
2.5V ± 5% 2.5V ± 5%
5319 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
Pin Configuration 512K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
V
DDQ
V
DDQ
5
V
SS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
SS
V
DDQ
V
DDQ
I/O22
69
68
67
66
65
64
I/O
I/O
VSS
9
I/O23
8
(1)
SS
V
(1)
SS
V
DD
DD
(2)
V
V
V
DD
V
SS
ZZ
I/O
7
I/O6
63
62
I/O24
I/O25
61
60
59
V
DDQ
V
DDQ
V
SS
V
SS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
58
57
56
55
54
53
4
3
2
V
SS
V
SS
VDDQ
I/O30
I/O31
I/OP4
VDDQ
I/O
I/O
I/OP1
1
,
52
51
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5319 drw 02
Top View
100TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation,
several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS,
TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
6.42
5
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
Pin Configuration 1M x 18
Symbol
Rating
Commercial
Industrial
Unit
(2)
VTERM
Terminal Voltage with
Respect to GND
V
-0.5 to +3.6
-0.5 to +3.6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
(3,6)
VTERM
Terminal Voltage with
Respect to GND
V
V
V
1
80
79
78
77
76
75
74
73
NC
NC
NC
DDQ
V
SS
V
NC
NC
10
A
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
0 to +70
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-40 to +85
2
NC
NC
3
(4,6)
VTERM
Terminal Voltage with
Respect to GND
4
DDQ
V
V
5
SS
6
NC
(5,6)
7
VTERM
Terminal Voltage with
Respect to GND
P1
I/O
8
8
I/O
7
I/O
9
9
I/O
72
71
6
I/O
10
11
12
13
14
15
SS
V
DDQ
Operating Ambient
Temperature
SS
V
V
(7)
TA
oC
70
69
68
67
66
65
64
V
DDQ
10
I/O
5
I/O
oC
oC
W
11
I/O
4
I/O
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
2.0
-55 to +125
-55 to +125
2.0
SS(1)
V
SS
SS(1)
V
V
V
DD
V
DD(2)
DD
16
17
18
19
20
21
22
23
24
25
V
SS
V
12
I/O
13
I/O
DDQ
ZZ
3
I/O
2
I/O
DDQ
63
62
IOUT
DC Output Current
50
50
mA
61
60
59
58
57
56
55
V
V
V
5319 tbl 06
SS
V
I/O14
15
I/O
P2
I/O
NC
SS
V
DDQ
V
NC
NC
NC
SS
NOTES:
I/O
1
0
I/O
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
NC
NC
26
27
28
29
30
SS
V
V
54
53
DDQ
NC
NC
NC
,
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3. VDDQ terminals only.
5319 drw 02a
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
7. During production testing, the case temperature equals TA.
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the
input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.
3. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will
remain disabled from power up.
fBGACapacitance
(TA = +25°C, f = 1.0MHz)
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
TQFPCapacitance
(TA = +25°C, f = 1.0MHz)
CI/O
pF
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5319 tbl 07b
5
7
pF
CI/O
pF
5319 tbl 07
BGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5319 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 36, 119 BGA(1,2,3,4)
1
2
3
4
5
6
7
DDQ
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
6
4
18
8
16
NC
NC
CE2
A
ADV/LD
A
NC
NC
CE
3
9
2
DD
V
A
A
A
A
15
7
2
12
SS
V
SS
V
I/O
I/OP3
NC
I/OP2
I/O
16
15
SS
V
SS
V
I/O
I/O
I/O
I/O
CE
17
18
13
14
1
DDQ
V
SS
V
SS
V
DDQ
V
I/O
I/O
OE
19
12
G
H
J
I/O
I/O
A
I/O
I/O
10
BW
BW
2
20
21
17
11
3
SS
V
SS
V
I/O
I/O
R/W
I/O
I/O
22
23
9
8
(2)
DDQ
V
DD
V
DD
DD
V
SS(1)
DD
V
DDQ
V
V
V
SS
SS
K
L
M
N
P
I/O
I/O
V
CLK
NC
V
I/O
I/O
7
24
26
6
I/O
I/O
I/O
I/O
5
BW
BW
1
25
27
4
4
DDQ
V
SS
V
SS
V
DDQ
V
I/O
CEN
I/O28
3
SS
V
SS
V
I/O
I/O
A
I/O
I/O
1
29
30
1
2
SS
V
SS
V
I/O
I/OP4
A
I/OP1
I/O
0
31
0
DD
V
SS(1)
R
T
U
NC
A
V
A
NC
ZZ
LBO
5
13
(4)
NC
NC
A
A
A
14
NC
10
11
NC/TMS(3)
NC/TCK
(3)
(3)
(3, 5)
NC/TDO(3)
DDQ
V
NC/
TRST
DDQ
V
NC/TDI
5319 tbl 25
Top View
Pin Configurations 1M x 18, 119 BGA(1,2,3,4)
1
2
3
4
5
6
7
DDQ
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
6
4
19
8
16
NC
NC
CE2
A
ADV/LD
DD
A
NC
NC
NC
CE2
3
9
A
A
V
A
A
7
2
13
17
SS
V
SS
V
I/O
NC
I/O9
NC
NC
CE1
OE
I/OP1
NC
8
SS
V
SS
V
NC
I/O
7
DDQ
V
SS
V
SS
V
DDQ
V
I/O
6
SS
G
H
J
NC
I/O
I/O
A
V
NC
I/O
5
BW2
SS
10
18
SS
V
NC
V
R/W
I/O
NC
11
4
(2)
DDQ
V
DD
V
DD
DD
V
SS(1)
DD
V
DDQ
V
V
V
SS
SS
K
L
M
N
P
NC
I/O
I/O
V
CLK
NC
V
NC
I/O
3
12
13
SS
V
NC
I/O
NC
DDQ
1
BW
2
DDQ
V
SS
V
SS
V
I/O
NC
V
CEN
14
SS
V
SS
V
I/O
NC
A
I/O
NC
15
1
1
SS
V
SS
V
NC
I/O
A
NC
I/O
P2
0
0
DD
V
SS(1)
R
T
U
NC
NC
A
V
A
NC
ZZ
LBO
5
12
(4)
A
A
NC
A
A
10
15
14
11
(3)
(3, 5)
NC/TMS(3)
NC/TDO
(3)
(3)
NC/
TRST
DDQ
V
NC/TCK
DDQ
V
NC/TDI
5319 tb l 25a
NOTES:
Top View
1. Pins R5 and J5 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin J3 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several
settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST)
U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
4. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
5. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1)
(5 )
CEN
CE1, CE2
BWx
R/W
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
(7 )
L
L
L
L
H
X
L
L
X
L
L
H
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D
(7 )
Q
(7 )
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
D
(Advance burst counter)(2 )
(7 )
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q
(Advance burst counter)(2 )
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3 )
NOOP
HIZ
HIZ
DESELECT / NOOP
X
(4 )
SUSPEND
Previous Value
5319 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Osremainsunchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3 )
(3 )
BW1
X
BW2
X
BW3
BW4
OPERATION
R/W
H
L
READ
X
L
X
L
WRITE ALLBYTES
WRITE BYTE 1 (I/O[0:7], I/OP1)
L
L
(2 )
L
L
H
H
H
L
H
H
H
L
(2 )
WRITE BYTE 2 (I/O[8:15], I/OP2)
L
H
L
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3)
L
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
NO WRITE
L
H
H
H
H
L
H
H
H
5319 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address
Third Address
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)
1
0
1
0
0
5319 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.482
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
0
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
1
1
0
0
1
0
0
1
1
Second Address
Third Address
1
1
0
1
0
0
1
1
0
1
Fourth Address(1)
1
0
0
1
0
5319 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A18)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
I/O [0:31], I/O P[1:4]
,
5319 drw 03
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
9
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
DeselectandNOOPCycles(2)
(1 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
L
D1
Q0
Load read
Burst read
n+1
X
L
n+2
A1
X
L
Q0+1 Load read
n+3
H
X
L
L
Q1
Z
Deselect or STOP
n+4
X
X
X
L
NOOP
n+5
A2
X
Z
Load read
Burst read
n+6
X
H
L
Q2
n+7
X
L
Q2+1 Deselect or STOP
n+8
A3
X
X
X
X
X
X
X
X
L
Z
Load write
Burst write
n+9
X
L
X
L
L
D3
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A4
X
L
D3+1 Load write
X
X
L
H
X
L
X
X
L
D4
Z
Deselect or STOP
X
NOOP
A5
A6
A7
X
Z
Load write
Load read
Load write
Burst write
H
L
L
X
L
D5
Q6
D7
L
X
H
X
L
X
L
L
X
X
L
A8
X
X
X
L
D7+1 Load read
Q8 Burst read
Q8+1 Load write
X
L
A9
L
5319 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
6.1402
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
ReadOperation(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
L
L
L
X
X
X
L
X
Address and Control meet setup
Contents of Address A0 Read Out
n+1
X
X
X
Q0
5319 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Read Operation(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
X
X
X
H
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
Address and Control meet setup
Address A0 Read Out, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
L
Q0
X
Q0+1 Address A0+1 Read Out, Inc. Count
X
Q0+2
Q0+3
Q0
Address A0+2 Read Out, Inc. Count
Address A0+3 Read Out, Load A1
Address A0 Read Out, Inc. Count
Address A1 Read Out, Inc. Count
X
A1
X
H
L
X
L
Q1
A2
Q1+1 Address A1+1 Read Out, Load A2
5319 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
L
L
L
L
L
X
X
X
Address and Control meet setup
Write to Address A0
n+1
X
X
X
X
D0
5319 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Burst Write Operation(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Address A0 Write, Inc. Count
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
Address A0+3 Write, Load A1
Address A0 Write, Inc. Count
Address A1 Write, Inc. Count
Address A1+1 Write, Load A2
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
X
X
L
D0
X
D0+1
D0+2
D0+3
D0
X
X
A1
X
X
L
H
L
X
L
D1
A2
D1+1
5319 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
11
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
Address A0 and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
A1
X
Q0
Q0
Q0
Q1
Q2
Q3
Address A0 Read out, Load A1
Clock Ignored. Data Q0 is on the bus.
Clock Ignored. Data Q0 is on the bus.
Address A1 Read out, Load A2
Address A2 Read out, Load A3
Address A3 Read out, Load A4
X
X
L
X
A2
A3
A4
L
L
5319 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Write Operation with Clock Enable Used(1)
(2 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE1
n
A0
X
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
Address A0 and Control meet setup.
Clock n+1 Ignored.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
L
A1
X
D0
X
Write data D0, Load A1.
Clock Ignored.
X
X
L
X
X
Clock Ignored.
A2
A3
A4
D1
D2
D3
Write Data D1, Load A2
Write Data D2, Load A3
Write Data D3, Load A4
L
L
5319 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.1422
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
(2 )
(3 )
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE1
H
H
L
I/O
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
A0
X
Z
Address A0 and Control meet setup.
Address A0 read out, Deselected.
Address A1 and Control meet setup.
Address A1 read out, Deselected.
Deselected.
H
L
Q0
Z
A1
X
X
L
H
H
L
Q1
Z
X
X
X
L
A2
X
Z
Address A2 and Control meet setup.
Address A2 read out, Deselected.
Deselected.
H
H
Q2
Z
X
X
5319 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used(1)
CE(2 )
H
H
L
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
A0
X
Z
Address A0 and Control meet setup
Data D0 Write In, Deselected.
Address A1 and Control meet setup
Data D1 Write In, Deselected.
Deselected.
X
L
H
L
X
L
D0
Z
A1
X
X
X
L
H
H
L
X
X
L
D1
Z
X
A2
X
Z
Address A2 and Control meet setup
Data D2 Write In, Deselected.
Deselected.
X
X
H
H
X
X
D2
Z
X
5319 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
LBO, JTAG and ZZ Input Leakage Current(1 )
Output Leakage Current
___
___
___
|ILI|
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VCC
30
5
µA
µA
V
|ILO|
VOL
VOH
Output Low Voltage
IOL = +6mA, VDD = Min.
IOH = -6mA, VDD = Min.
0.4
___
Output High Voltage
2.0
V
5319 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
7.5ns
8ns
8.5ns
Com'l
Symbol
Parameter
Test Conditions
Unit
Com'l
Ind
Com'l
Ind
Ind
Ope rating Powe r
Supply Curre nt
De vice Se le cte d, Outputs Ope n,
ADV/LD = X, VDD = Max.,
V
IN > VIH or < VIL, f = fMAX
275
40
295
250
40
270
225
40
245
mA
I
DD
(2)
CMOS Standby Powe r
Supply Curre nt
De vice De se le cte d, Outputs Ope n,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
V
,
60
125
80
60
120
80
60
115
80
mA
mA
mA
I
SB1
Clock Running Powe r
Supply Curre nt
De vice De se le cte d, Outputs Ope n,
DD = Max., VIN > VHD or < VLD
V
,
105
60
100
60
95
I
SB2
(2,3)
f = fMAX
Idle Powe r
Supply Curre nt
De vice Se le cte d, Outputs Ope n,
CEN
> VIH, VDD = Max.,
60
I
SB3
(2,3)
HD LD MAX
> V or < V , f = f
IN
V
Full Sle e p Mode
Supply Curre nt
De vice Se le cte d, Outputs Ope n,
CEN < VIH, VDD = Max., ZZ > VHD
40
60
40
60
40
60
mA
I
ZZ
(2,3)
V
IN > VHD or < VLD, f = fMAX
5319 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ/2
AC Test Conditions
Input Pulse Levels
AC Test Load
0 to 2.5V
2ns
50Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
I/O
Z = 50Ω
0
,
(VDDQ/2)
(VDDQ/2)
Figure 1
5319 drw 04
Figure 1. AC Test Load
6
5
4
5319 tbl 23
•
3
∆tCD
(Typical, ns)
2
•
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
5319 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.1442
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 2.5V±5%, Commercial and Industrial Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
tCY C
Clock Cycle Time
10
2.5
2.5
10.5
2.7
11
3.0
3.0
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
____
____
____
(1)
2.7
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
2
2
2
____
____
____
(2,3,4)
3
3
3
tCL Z
____
____
____
(2,3,4)
5
5
5
ns
ns
ns
ns
tCHZ
____
____
____
tOE
5
5
5
____
____
____
(2,3)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
tOLZ
____
____
____
(2,3)
5
5
5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSE
Clock Enable Setup Time
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
tSA
Address Setup Time
tSD
Data In Setup Time
tSW
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
tSADV
tSC
tSB
Hold Times
tHE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Clock Enable Hold Time
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
tHA
tHD
Data In Hold Time
tHW
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
tHADV
tHC
ns
ns
tHB
Byte Write Enable ( x) Hold Time
BW
5319 tbl 24
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 2.375V).
6.42
15
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
.
6.1462
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
,
6.42
17
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
6.1482
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
6.42
19
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
,
6.2402
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification
tJCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
tJRSR
tJCD
3)
(
x
TRST
M5319 drw 01
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
tJCYC
tJCH
tJCL
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
Register Name
Instruction (IR)
Bit Size
____
____
ns
4
1
40
ns
Bypass (BYR)
(1 )
____
tJR
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1 )
____
tJF
5
ns
Note (1)
____
____
tJRST
tJRSR
tJCD
tJDC
tJS
50
ns
I5319 tbl 03
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
20
ns
____
0
ns
____
____
25
25
ns
tJH
JTAG Hold
ns
I5319 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
21
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Revision Number (31:28)
Value
Description
0x2
0x221, 0x223
0x33
Reserved for version number.
IDT Device ID (27:12)
Defines IDT part number 71T75702 and 71T75902, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
1
I5319 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5319tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.2422
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100 Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
23
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.2442
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Q
Q
,
5319 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
XXXX
S
XX
XX
X
Device
Type
Power Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
PF
BG
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
75
80
85
Access time (tCD) in tenths of nanoseconds
,
IDT71T75702
IDT71T75902
512Kx36 Flow-Through ZBT SRAM
1Mx18 Flow-Through ZBT SRAM
5319 drw 12
6.42
25
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
Rev
0
1
Date
05/25/00
08/24/01
Pages
Description
CreatedAdvanceInformationDatasheet
RemovedreferenceofBQ165package
Removedpageofthe165BGApinconfiguration
Removedpageofthe165BGApackagediagramoutline
Corrected 3.3V to 2.5V in Note 3
AddedclarificationtoJTAGpins,allowforNC. Added36Maddress pinlocations
Corrected 100-pin TQFP package drawing
p. 1, 25
p. 8
p. 24
p. 7
p. 5-7
p. 21
2
3
4
5
10/16/01
12/21/01
05/29/02
06/07/02
p. 1-4,7,14,21,22 AddedcompleteJTAGfunctionality.
p. 2,14
p. 14
p.1-26
Added notes for ZZ pin internal pulldown and ZZ leakage current.
UpdatedISB3powersupplycurrentfrom40to60mAforallspeeds.
ChangeddatasheetfromAdvancedinformationtofinalrelease.
6
7
11/19/02
05/23/03
p.5,6,14,15,25 AddedI-temptothedatasheet.
p.6
Updated165BGAtable.
8
04/01/04
p.1
Updatedlogowithnewdesign.
p.5,6
p.7
p.24
Clarifiedambientandcaseoperatingtemperatures.
Updated I/O pin number order for the 119 BGA.
Updated119BGAPackageDiagramDrawing.
Removed "IDT" from orderable parts number.
02/20/09 p.25
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Rd
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
800-345-7015 or
408/284-4555
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.2462
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