IDT71V128S20Y [IDT]

Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, SOJ-32;


型号：	IDT71V128S20Y
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, SOJ-32 静态存储器光电二极管内存集成电路
文件：	总7页 (文件大小：59K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

IDT71V128

3.3V CMOS STATIC RAM

1 MEG (256K x 4-BIT)

REVOLUTIONARY PINOUT

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• 256K x 4 advanced high-speed CMOS static RAM

• JEDEC revolutionary pinout (center power/GND) for

reduced noise.

• Equal access and cycle times

— Commercial: 12/15/20ns

• One Chip Select plus one Output Enable pin

• Bidirectional inputs and outputs directly TTL-compatible

• Low power consumption via chip deselect

• Available in a 32-pin 400 mil Plastic SOJ

The IDT71V128 is a 1,048,576-bit high-speed static RAM

organized as 256K x 4. It is fabricated using IDT’s high-

performance, high-reliability CMOS technology. This state-

of-the-arttechnology, combinedwithinnovativecircuit design

techniques, provides a cost-effective solution for high-speed

memory needs. The JEDEC centerpower/GND pinout re-

duces noise generation and improves system performance.

The IDT71V128 has an output enable pin which operates

as fast as 6ns, with address access times as fast as 12ns

available. AllbidirectionalinputsandoutputsoftheIDT71V128

are TTL-compatible and operation is from a single 5V supply.

Fully static asynchronous circuitry is used; no clocks or

refreshes are required for operation.

The IDT71V128 is packaged in a 32-pin 400 mil Plastic

SOJ.

FUNCTIONAL BLOCK DIAGRAM

1,048,576-BIT

MEMORY

ARRAY

ADDRESS

DECODER

A17

I/O0 – I/O3

I/O CONTROL

CONTROL

LOGIC

3485 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

JUNE 1996

1996 Integrated Device Technology, Inc.

DSC-3485/-

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONFIGURATION

Symbol

Rating

Com'l

Unit

(2)

VTERM

Terminal Voltage with Respect

to GND

–0.5 to +4.1⁽²⁾

A17

A16

A15

A14

A13

Operating Temperature

Temperature Under Bias

Storage Temperature

Power Dissipation

0 to +70

–55 to +125

1.25

°C

TBIAS

TSTG

I/O3

GND

VDD

I/O2

A12

A11

A10

I/O0

VDD

GND

I/O1

S032-3

IOUT

DC Output Current

NOTES:

3485 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliabilty.

2. VTERM must not exceed VDD + 0.5V.

3485 drw 02

SOJ

TOP VIEW

TRUTH TABLE^(1,2)

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

I/O

Function

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

Max.

Unit

DATAOUT Read Data

DATAIN

High-Z

Write Data

CI/O

VOUT = 3dV

Output Disabled

NOTE:

3485 tbl 03

Deselected - Standby (I^SB)

1. This parameter is guaranteed by device characterization, but is not prod-

uction tested.

(3)

V^HC

NOTES:

Deselected - Standby (ISB1)

3485 tbl 01

1. H = VIH, L = VIL, x = Don't care.

2. VLC = 0.2V, VHC = VDD -0.2V.

3. Other inputs ≥VHC or ≤VLC.

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Parameter

Min. Typ.

Max.

3.6

Unit

VDD

Supply Voltage

3.0

3.3

GND

VIH

Input High Voltage 2.0

Input Low Voltage –0.3⁽¹⁾

—

VDD+0.3

0.8

VIL

NOTE:

3485 tbl 04

1. VIL (min.) = –1V for pulse width less than 5ns, once per cycle.

DC ELECTRICAL CHARACTERISTICS

VDD = 3.3V ± 10%

IDT71V128

Symbol

|ILI|

Parameter

Test Condition

Min.

—

Max.

Unit

µA

Input Leakage Current

Output Leakage Current

Output LOW Voltage

Output HIGH Voltage

VDD = Max., VIN = GND to VDD

VDD = Max., CS = VIH, VOUT = GND to VDD

IOL = 8mA, VDD = Min.

|ILO|

—

µA

VOL

—

0.4

—

VOH

IOH = –8mA, VDD = Min.

2.4

3483 tbl 05

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS⁽¹⁾

(VDD = 3.3V ± 10%, VLC = 0.2V, VHC = VDD – 0.2V)

71V128S12⁽³⁾71V128S15 71V128S20

Symbol

Parameter

Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit

ICC

Dynamic Operating Current and

100

—

CS ≤ VIL, Outputs Open,

(2)

VDD = Max., f = fMAX

ISB

Standby Power Supply Current (TTL Level)

—

CS ≥ VIH, Outputs Open,

(2)

VDD = Max., f = fMAX

ISB1

Full Standby Power Supply Current

(CMOS Level) CS ≥ VHC,

Outputs Open,

VDD = Max., f = 0⁽²⁾, VIN ≤ VLC or VIN ≥ VHC

NOTES:

3484 tbl 06

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

3. 12ns specification is preliminary.

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

3ns

1.5V

See Figures 1 and 2

3485 tbl 07

3.3V

298Ω

3.3V

298Ω

216Ω

DATAOUT

30pF

DATAOUT

5pF*

216Ω

3485 drw 03

3485 drw 04

*Including jig and scope capacitance.

Figure 1. AC Test Load

Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 10%, Commercial Range)

71V128S12⁽³⁾

71V128S15 71V128S20

Min. Max. Min. Max.

Symbol Parameter

Read Cycle

Min.

Max.

Unit

tRC

tAA

Read Cycle Time

—

Address Access Time

tACS

Chip Select Access Time

(2)

tCLZ

tCHZ

tOE

Chip Select to Output in Low-Z

Chip Deselect to Output in High-Z

Output Enable to Output Valid

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

Output Hold from Address Change

Chip Select to Power-Up Time

Chip Deselect to Power-Down Time

(2)

—

(2)

tOLZ

—

(2)

tOHZ

tOH

—

(2)

tPU

tPD

(2)

—

Write Cycle

tWC

tAW

tCW

tAS

Write Cycle Time

—

Address Valid to End-of-Write

Chip Select to End-of-Write

Address Set-up Time

tWP

tWR

tDW

tDH

tOW

Write Pulse Width

Write Recovery Time

Data Valid to End-of-Write

Data Hold Time

(2)

Output Active from End-of-Write

Write Enable to Output in High-Z

(2)

tWHZ

NOTES:

1. 0°C to +70°C temperature range only.

3484 tbl 08

2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.

3. 12ns specification is preliminary.

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1⁽¹⁾

ADDRESS

tAA

tOE

(5)

OLZ

(5)

(3)

ACS

(5)

tOHZ

CLZ

(5)

CHZ

HIGH IMPEDANCE

DATAOUT

DATAOUT VALID

tPD

tPU

CC SUPPLY

CURRENT

3485 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 2^{(1, 2, 4)}

tRC

ADDRESS

tAA

tOH

DATAOUT VALID

PREVIOUS DATAOUT VALID

DATAOUT

3485 drw 06

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected, CS is LOW.

3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

CONTROLLED TIMING)^{(1, 2, 5, 7)}

tWC

ADDRESS

tAW

(3)

tWR

tAS

(4)

tWP

(6)

tCHZ

(4)

(6)

tWHZ

tOW

HIGH IMPEDANCE

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

3485 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CONTROLLED TIMING)^{(1, 2, 5)}

tWC

ADDRESS

tAW

(3)

tWR

tCW

tAS

tDW

DATAIN

DATAIN VALID

3485 drw 08

NOTES:

1. WE must be HIGH, CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to

turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the

minimum write pulse is the specified tWP.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active

during the tCW write period.

6. Transition is measured ±200mV from steady state.

9.8

IDT71V128

CMOS STATIC RAM 1MEG (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

71V128

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

400-mil SOJ (SO32-3)

Speed in nanoseconds

3485 drw 09

9.8

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