IDT71V256SB15PZ [IDT]

3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT); 3.3V CMOS快速SRAM具有2.5V兼容输入256K （ 32K ×8位）


型号：	IDT71V256SB15PZ
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) 3.3V CMOS快速SRAM具有2.5V兼容输入256K （ 32K ×8位）静态存储器输入元件
文件：	总6页 (文件大小：70K)
中文：	中文翻译
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IDT71V256SB

3.3V CMOS FAST SRAM

WITH 2.5V COMPATIBLE INPUTS

256K (32K x 8-BIT)

Integrated Device Technology, Inc.

FEATURES

• Ideal for high-performance processor secondary cache

• Fast access times:

— 12/15/20ns

• Inputs are 2.5V and LVTTL compatible: VIH = 1.8V

• Outputs are LVTTL compatible

• Low standby current (maximum):

— 2mA full standby

• Small packages for space-efficient layouts:

— 28-pin 300 mil SOJ

DESCRIPTION

TheIDT71V256SBisa 262,144-bithigh-speedstaticRAM

organized as 32K x 8. The improved VIH (1.8V) makes the

inputs compatible with 2.5V logic levels. The IDT71V256SB

is otherwise identical to the IDT71V256SA.

The IDT71V256SB has outstanding low power character-

istics while at the same time maintaining very high perfor-

mance. Address access times of as fast as12 ns are ideal for

tag SRAM in secondary cache designs.

When power management logic puts the IDT71V256SB in

standby mode, its very low power characteristics contribute to

— 28-pin TSOP Type I

• Produced with advanced high-performance CMOS extended battery life. By taking CS HIGH, the SRAM will

technology

• Single 3.3V(±0.3V) power supply

automatically go to a low power standby mode and will remain

in standby as long as CS remains HIGH. Furthermore, under

full standby mode (CS at CMOS level, f=0), power consump-

tion is guaranteed to always be less than 6.6mW and typically

will be much smaller.

The IDT71V256SB is packaged in 28-pin 300 mil SOJ and

28-pin300 mil TSOP Type I packaging.

FUNCTIONAL BLOCK DIAGRAM

GND

262,144 BIT

MEMORY ARRAY

ADDRESS

DECODER

I/O

I/O CONTROL

INPUT

DATA

CIRCUIT

I/O

CONTROL

CIRCUIT

3770 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGES

JANUARY 1997

1997 Integrated Device Technology, Inc.

3770/1

7.??

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol

Rating

Com’l.

Unit

(2)

VTERM

Terminal Voltage with

Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with

Respect to GND

–0.5 to VCC+0.5

SO28-5

Operating Temperature

Temperature Under Bias

Storage Temperature

Power Dissipation

0 to +70

–55 to +125

1.0

°C

A10

TBIAS

TSTG

°C

I/O

IOUT

DC Output Current

GND

NOTES:

3770 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

3770 drw 02

SOJ

TOP VIEW

2. Vcc terminals only.

3. Input, Output, and I/O terminals; 4.6V maximum.

I/O

VCC

SO28-8

GND

CAPACITANCE

(TA = +25°C, f = 1.0MHz, SOJ package)

I/O

(1)

Symbol

Parameter

Conditions

VIN = 3dV

Max. Unit

CIN

Input Capacitance

Output Capacitance

COUT

VOUT = 3dV

3770 drw 03

NOTE:

3770 tbl 04

TSOP

TOP VIEW

1. This parameter is determined by device characterization, but is not

production tested.

PIN DESCRIPTIONS

Name

Description

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

A0–A14

I/O0–I/O7

Addresses

Data Input/Output

Grade

Temperature

GND

VCC

Chip Select

Write Enable

Output Enable

Ground

Commercial

0°C to +70°C

3.3V ± 0.3V

3770 tbl 05

GND

VCC

Power

3770 tbl 01

RECOMMENDED DC OPERATING

CONDITIONS

TRUTH TABLE⁽¹⁾

I/O

Function

Standby (ISB)

Standby (ISB1)

Output Disable

Read

Symbol

Parameter

Supply Voltage

Min. Typ. Max. Unit

High-Z

VCC

3.0

3.3

3.6

VHC

GND

VIH

Input High Voltage - Inputs 1.8

—

5.0

DOUT

DIN

VIH

Input High Voltage - I/O

Input Low Voltage

1.8

–0.5⁽¹⁾

Vcc+0.3

0.8

Write

NOTE:

1. H = VIH, L = VIL, X = Don’t Care

3770 tbl 02

VIL

NOTE:

3770 tbl 06

1. VIL (min.) = –1.0V for pulse width less than 5ns, once per cycle.

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS^{(1, 2)}

(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V)

71V256SB12 71V256SB15 71V256SB20

Symbol

Parameter

Com’l

Com’l.

Unit

ICC

Dynamic Operating Current CS ≤ VIL, Outputs

Open, VCC = Max., f = fMAX

(2)

ISB

Standby Power Supply Current (TTL Level)

CS = VIH, VCC = Max., Outputs Open, f = fMAX

(2)

ISB1

Full Standby Power Supply Current (CMOS Level)

CS ≥ VHC, VCC = Max., Outputs Open, f = 0⁽²⁾

VIN ≤ VLC or VIN ≥ VHC

NOTES:

3770 tbl 07

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.

DC ELECTRICAL CHARACTERISTICS

VCC = 3.3V± 0.3V

IDT71V256SB

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

|ILI|

Input Leakage Current

VCC = Max., VIN = GND to VCC

—

µA

|ILO|

VOL

VOH

Output Leakage Current VCC = Max., CS= VIH, VOUT = GND to VCC

Output Low Voltage

Output High Voltage

IOL = 8mA, VCC = Min.

IOH = –4mA, VCC = Min.

—

0.4

—

2.4

3770 tbl 08

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

3ns

1.5V

See Figures 1 and 2

3770 tbl 09

3.3V

320

320Ω

Ω

DATAOUT

350

Ω

350Ω

30pF*

5pF*

3770 drw 04

3770 drw 05

Figure 2. AC Test Load

Figure 1. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)

*Includes scope and jig capacitances

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 0.3V, Commercial Temperature Range)

71V256SA12

71V256SA15

71V256SA20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle

tRC

tAA

Read Cycle Time

Address Access Time

—

tACS

Chip Select Access Time

(1)

tCLZ

tCHZ

tOE

Chip Select to Output in Low-Z

Chip Select to Output in High-Z

Output Enable to Output Valid

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

Output Hold from Address Change

(1)

—

(1)

tOLZ

—

(1)

tOHZ

tOH

—

Write Cycle

tWC

tAW

tCW

Write Cycle Time

—

Address Valid to End-of-Write

Chip Select to End-of-Write

Address Set-up Time

tAS

tWP

tWR

Write Pulse Width

Write Recovery Time

tDW

tDH

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End-of-Write

Write Enable to Output in High-Z

(1)

tOW

(1)

tWHZ

NOTE:

3770 tbl 10

1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.

TIMING WAVEFORM OF READ CYCLE NO. 1⁽¹⁾

tRC

ADDRESS

tAA

tOH

tOE

(2)

tOHZ

tCHZ

tOLZ

tACS

(2)

tCLZ

DATAOUT

DATA VALID

3770 drw 06

NOTES:

1. WE is HIGH for Read cycle.

2. Transition is measured ±200mV from steady state.

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 2^{(1, 2, 4)}

tRC

ADDRESS

tAA

tOH

PREVIOUS DATA VALID

DATA VALID

DATAOUT

3770 drw 07

TIMING WAVEFORM OF READ CYCLE NO. 3^{(1, 3, 4)}

ACS

(5)

CLZ

(5)

CHZ

DATA VALID

DATAOUT

3770 drw 08

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

CONTROLLED TIMING)^{(1, 2, 3, 5, 7)}

ADDRESS

(6)

OHZ

(7)

(6)

WHZ

DATAOUT

DATAIN

(4)

t DH

DATA VALID

3770 drw 09

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

be as short as the spectified tWP.

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CONTROLLED TIMING)^{(1, 2, 3, 4)}

tWC

ADDRESS

tAW

(5)

tAS

tCW

tWR

tDW

t DH

DATA VALID

DATAIN

3770 drw 10

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

be as short as the spectified tWP.

ORDERING INFORMATION

IDT 71V256

Device Power/ Speed

Type Rev

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

300 mil SOJ (SO28-5)

TSOP Type I (SO28-8)

Speed in nanoseconds

Standard Power, 2.5V

Compatible Inputs

3770 drw 11

IDT71V256SB15PZ [IDT]

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