IDT71V2577SA75BQ_技术文档

IDT71V2577S

IDT71V2579S

IDT71V2577SA

IDT71V2579SA

128K x 36, 256K x 18

3.3V Synchronous SRAMs

2.5V I/O, Flow-Through Outputs

Burst Counter, Single Cycle Deselect

Description

Features

◆

The IDT71V2577/79 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,

address andcontrolregisters.Therearenoregisters inthedataoutput

path (flow-through architecture). Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

128K x 36, 256K x 18 memory configurations

◆

Supports fast access times:

Commercial:

– 7.5ns up to 117MHz clock frequency

CommercialandIndustrial:

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array (fBGA)

theendofthewritecycle.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata

fora single address presentedtothe SRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe

arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof

the same cycle. If burst mode operation is selected (ADV=LOW), the

subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe

next three rising clock edges. The order of these three addresses are

definedbytheinternalburstcounterandtheLBOinputpin.

◆

The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Synchronous

Asynchronous

Synchronous

Chip Enable

CE

CS⁰, CS¹

OE

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

GW

BWE

(1)

BW¹, BW², BW³, BW⁴

CLK

ADV

ADSC

ADSP

LBO

Clock

Input

Output

Input

I/O

N/A

Synchronous

DC

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

ZZ

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

V^SS

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

4877 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V2579.

JUNE 2003

1

DSC-4877/08

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

PinDefinition⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A0-A17

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of

CLK and ADSC Low or ADSP Low and CE Low.

Address Status

(Cache Controller)

I

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the

ADSC

ADSP

ADV

address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the

address registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst

counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst

counter is not incremented; that is, there is no address advance.

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs BW¹-BW⁴. If BWE is LOW at the rising edge of

CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs

are blocked and only GW can initiate a write cycle.

BWE

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables. BW¹controls I/O0-7, I/OP1, BW²controls I/O8-15, I/OP2, etc. Any active

BW¹-BW⁴

byte write causes all outputs to be disabled.

Chip Enable

Synchronous chip enable. CE is used with CS0 and CS¹to enable the IDT71V2577/79. CE also gates

ADSP.

CE

CLK

CS0

CS¹

GW

Clock

I

N/A

This is the clock input. All timing references for the device are made with respect to this input.

Synchronous active HIGH chip select. CS0 is used with CE and CS¹to enable the chip.

Synchronous active LOW chip select. CS¹is used with CE and CS0 to enable the chip.

Chip Select 0

Chip Select 1

HIGH

LOW

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising

edge of CLK. GW supersedes individual byte write enables.

I/O0-I/O31

I/OP1-I/OP4

Data Input/Output

I/O

I

N/A

Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge

of CLK. The data output path is flow-through (no output register).

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is

selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not

change state while the device is operating.

LBO

OE

Output Enable

I

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the

chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.

TMS

TDI

Test ModeSelect

Test Data Input

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

I

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the

TAP controller.

Test DataOutput

O

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST

can be left floating. This pin has an internal pullup. Only available in BGA package.

JTAG Reset

(Optional)

I

LOW

HIGH

TRST

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V2577/79

to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal

pull down.

ZZ

Sleep Mode

VDD

VDDQ

VSS

Power Supply

Ground

N/A

3.3V core power supply.

2.5V I/O Supply.

Ground.

NC

No Connect

NC pins are not electrically connected to the device.

4877 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

2

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

LBO

ADV

CEN

INTERNAL

ADDRESS

Burst

Sequence

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

CLK

2

Burst

Logic

17/18

Binary

Counter

ADSC

A0*

A1*

Q0

Q1

CLR

ADSP

2

CLK EN

A0,A1

A2 - A17

ADDRESS

REGISTER

A0 - A16/17

GW

36/18

17/18

BWE

Byte 1

Write Register

Byte 1

Write Driver

BW1

9

Byte 2

Write Register

Byte 2

Write Driver

2

BW

Byte 3

Write Register

Byte 3

Write Driver

BW3

BW4

9

Byte 4

Write Register

Byte 4

Write Driver

CE

Q

D

CS⁰

Enable

DATA INPUT

REGISTER

1

CS

Register

CLK EN

ZZ

Powerdown

OE

OUTPUT

BUFFER

OE

,

36/18

I/O0 - I/O31

I/OP1 - I/OP4

4877 drw 01

TMS

TDI

TCK

JTAG

(SA Version)

TDO

TRST

(Optional)

6.42

3

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Commerical &

Industrial Values

Symbol

Rating

Unit

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

V

SS

DD

DDQ

V

Grade

(2)

TERM

V

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

Commercial

Industrial

0V

3.3V±5%

2.5V±5%

(3,6)

(4,6)

(5,6)

TERM

DD

V

Terminal Voltage with

Respect to GND

-0.5 to V

V

4877 tbl 04

NOTES:

1. TA is the “instant on” case temperature.

TERM

V

DD

Terminal Voltage with

Respect to GND

-0.5 to V +0.5

TERM

V

DDQ

Terminal Voltage with

Respect to GND

-0.5 to V +0.5

V

RecommendedDCOperating

Conditions

Commercial

Operating Temperature

-0 to +70

-40 to +85

-55 to +125

^oC

W

Symbol

VDD

VDDQ

VSS

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min.

3.135

2.375

0

Typ.

Max.

Unit

V

(7)

A

T

3.3

3.465

2.625

0

Industrial

Operating Temperature

2.5

V

BIAS

T

Temperature

Under Bias

0

V

____

VIH

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

1.7

VDD + 0.3

V

STG

T

Storage

(1)

____

VIH

1.7

VDDQ + 0.3

V

Temperature

(2)

VIL

-0.3

0.7

V

T

P

Power Dissipation

DC Output Current

2.0

50

4877 tbl 05

NOTES:

OUT

I

mA

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

4877 tbl 03

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the “instant on” case temperature.

100PinTQFPCapacitance

(TA = +25°C, f = 1.0MHz)

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

CIN

7

pF

CIN

5

7

pF

CI/O

pF

CI/O

pF

4877 tbl 07a

4877 tbl 07

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

CIN

7

pF

CI/O

pF

4877 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

4

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

VDDQ

I/O9

I/O8

VSS

NC

I/OP3

2

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

3

78

77

4

5

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

I/O22

I/O23

(1)

VSS

VDD

NC

VSS

VDD

ZZ⁽²⁾

I/O7

I/O6

VDDQ

VSS

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

VDDQ

I/O30

I/O31

I/OP4

I/O5

I/O4

I/O3

I/O2

VSS

VDDQ

I/O1

I/O0

I/OP1

,

31

33 34 35 36

38 39 40 41 42 43 44 45 46 47 48 49 50

37

32

4877 drw 02a

100TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 18

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

A10

NC

VDDQ

VSS

NC

I/O8

I/O9

VSS

2

3

78

77

4

VDDQ

VSS

NC

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

NC

VDD

ZZ⁽²⁾

I/O3

I/O2

VDDQ

VSS

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

69

68

67

66

I/O10

I/O11

(1)

VSS

VDD

NC

VSS

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

I/O12

I/O13

VDDQ

VSS

I/O14

I/O15

I/OP2

NC

VSS

VDDQ

NC

I/O1

I/O0

NC

VSS

VDDQ

NC

,

NC

31

33 34 35 36

38 39 40 41 42 43 44 45 46 47 48 49 50

37

32

4877 drw 02b

100TQFP

Top View

NOTES:

1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

2

9

1

CS

NC

CS

NC

0

7

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

CE

V

17

I/O

18

19

13

12

14

I/O

DDQ

V

DDQ

V

I/O

OE

20

21

3

2

BW

11

10

I/O

G

H

J

BW

ADV

GW

22

I/O

23

I/O

SS

V

9

I/O

8

I/O

V

DDQ

DD

V

DD

DDQ

7

V

NC

V

24

I/O

26

I/O

SS

V

SS

V

6

I/O

CLK

NC

I/O

K

L

25

I/O

27

I/O

4

BW

1

BW

4

I/O

5

I/O

DDQ

28

SS

3

DDQ

1

V

I/O

V

I/O

V

M

N

P

R

T

BWE

29

I/O

30

I/O

1

A

2

I/O

0

I/O

31

P4

I/O

0

A

P1

I/O

NC

I/O

NC

5

DD

11

13

A

NC

V

A

LBO

(3)

10

A

14

A

,

A

NC

TRST

ZZ

(2)

(2,4)

V

DDQ

V

DDQ

U

NC/TMS

NC/TDI

NC/TCK

NC/TDO

NC/

4877 drw 02c

Top View

Pin Configuration 256K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

A

DDQ

V

A

B

C

D

E

F

V

A

ADSP

ADSC

3

2

9

1

CS

NC

CS

NC

0

7

DD

V

13

17

A

8

I/O

SS

2

SS

7

I/O

NC

V

NC

CE

V

9

6

I/O

NC

I/O

NC

DDQ

V

5

I/O

DDQ

V

OE

10

I/O

4

G

H

J

NC

I/O

NC

BW

ADV

GW

11

I/O

SS

3

I/O

NC

V

DDQ

V

DD

12

DD

V

DD

DDQ

V

NC

V

SS

V

SS

V

2

K

L

NC

I/O

NC

CLK

NC

I/O

NC

SS

V

13

I/O

1

I/O

BW

DDQ

15

14

SS

DDQ

V

I/O

NC

V

A

NC

M

N

P

R

T

BWE

1

A

0

I/O

NC

P2

I/O

0

A

P1

I/O

NC

5

DD

V

SS

14

12

11

NC

A

NC

LBO

(3)

10

15

A

ZZ

A

NC

A

(2)

(2,4)

,

DDQ

V

DDQ

V

U

NC/TDO

NC/TMS

NC/TDI

NC/TCK

NC/TRST

4877 drw 02d

NOTES:

Top View

1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. T7 can be left unconnected and the device will always remain in active mode.

4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.42

7

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 165 fBGA

1

2

3

4

5

6

7

8

9

10

A8

11

(4)

A

B

C

D

E

F

NC

A7

NC

CE¹

BW³

BW⁴

VSS

VDD

VSS

A2

BW²

BW¹

VSS

TRST^{(2, 5)}

CS¹

CLK

VSS

BWE

GW

VSS

NC

ADSC

OE

ADV

(4)

NC

A6

CS0

A9

NC

ADSP

VDDQ

NC

I/OP3

I/O17

I/O19

I/O21

I/O23

VSS⁽¹⁾

I/O25

I/O27

I/O29

I/O31

I/OP4

NC

VDDQ

NC

VSS

VDD

VSS

A10

NC

I/OP2

I/O14

I/O12

I/O10

I/O8

I/O16

I/O18

I/O20

I/O22

NC

I/O15

I/O13

I/O11

I/O9

NC

G

H

J

(3)

ZZ

I/O24

I/O26

I/O28

I/O30

NC

VDDQ

A5

VDDQ

A13

I/O7

I/O5

I/O3

I/O1

NC

I/O6

I/O4

I/O2

I/O0

I/OP1

K

L

M

N

P

(4)

NC

NC/

(4)

(2)

(4)

NC

NC/TDI

NC/TMS⁽²⁾

A1

A0

NC/TDO

A14

A15

NC

(4)

(2)

R

NC

A4

A3

NC/TCK

A11

A12

A16

LBO

4877 tbl 17

Pin Configuration 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

9

10

A8

11

(4)

A

B

C

D

E

F

NC

A7

NC

A10

CE

BW²

NC

CS¹

CLK

VSS

BWE

GW

VSS

ADSC

OE

ADV

(4)

A6

CS0

A9

NC

BW¹

VSS

ADSP

VDDQ

NC

I/O8

I/O9

I/O10

VDDQ

VSS

VDD

VSS

VDD

NC

I/O3

I/O2

I/O1

I/O0

NC

A15

A16

I/OP1

I/O7

I/O6

I/O5

NC

G

H

J

NC

I/O

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

4

11

DDQ

VSS⁽¹⁾

I/O12

I/O13

I/O14

I/O15

I/OP2

NC

VDDQ

A5

VDD

VSS

A2

VSS

NC

VDD

VSS

A11

NC

VDDQ

A14

ZZ

(3)

NC

K

L

M

N

P

(4)

NC

A1

A0

NC/

TRST^{(2, 5)}

(4)

(2)

(4)

NC

NC/TDI

NC/TDO

NC

(4)

(2)

R

NC

A4

A3

NC/TMS⁽²⁾

NC/TCK

A12

A13

A17

LBO

4877 tbl 17a

NOTES:

1. H1 does not have to be directly VSS as long as input voltage is < VIL.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. H11 can be left unconnected and the device will always remain in active mode.

4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

6.42

8

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

|I^LI

|I_LO

Parameter

Test Conditions

Min.

Max.

Unit

___

|

Input Le akage Curre nt

V

^DD= Max., V^IN= 0V to V^DD

5

µA

ZZ, LBO and JTAG Input Leakage Curre nt⁽¹⁾

Output Leakage Curre nt

___

|

V

^DD= Max., V^IN= 0V to V^DD

30

5

µA

V

|

V_OUT= 0V to V_DDQ, De vice De se le cted

^OL= +6mA, V^DD= Min.

^OH= -6mA, V^DD= Min.

V

OL

Output Low Voltage

I

0.4

___

V

OH

Output High Voltage

I

2.0

V

4877 tbl 08

NOTE:

1. The LBO, TMS, TDI, TCK, and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾

7.5ns

8ns

8.5ns

Com'l

Symbol

Parameter

Test Conditions

Com'l Only Com'l

Ind

Unit

Operating Power Supply Current

Device Selected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VIH or < VIL, f = fMAX

255

30

200

30

210

180

190

mA

IDD

(2)

ISB1

CMOS Standby Power Supply

Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = 0^(2,3)

35

95

35

30

35

90

35

mA

SB2

I

DD

Clock Running Power Supply

Current

Device Deselected, Outputs Open, V = Max.,

90

85

80

(2,3)

VDDQ = Max., VIN > VHD or < VLD, f = fMAX

IZZ

Full Sleep Mode Supply Current

ZZ > VHD, VDD = Max.

30

mA

4877 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

AC Test Conditions

AC Test Load

V

DDQ/2

(VDDQ = 2.5V)

50

Ω

Input Pulse Levels

0 to 2.5V

2ns

I/O

0 Ω

Z = 50

Input Rise/Fall Times

,

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

(VDDQ/2)

See Figure 1

4877d03

Figure 1. AC Test Load

6

5

4

4877 tbl 10

3

∆tCD

(Typical, ns)

2

1

,

20 30 50

80 100

Capacitance (pF)

200

4877d05

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

9

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousTruthTable^(1,3)

CE

CS

1

ADSP ADSC ADV

GW

BWE BW

x

OE⁽²⁾

Operation

Address

CS

0

CLK

I/O

Used

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

H

L

X

L

X

H

X

H

X

L

X

L

X

L

X

L

X

H

L

X

H

L

X

H

L

X

L

↑

HI-Z

None

L

None

L

X

L

X

L

None

L

External

H

X

L

D

OUT

Read Cycle, Begin Burst

L

H

L

HI-Z

Read Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

D

OUT

Read Cycle, Begin Burst

L

D

OUT

Read Cycle, Begin Burst

L

H

X

L

HI-Z

Write Cycle, Begin Burst

L

D

IN

OUT

HI-Z

Write Cycle, Begin Burst

L

X

H

X

H

X

L

X

H

X

H

L

D

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

L

D

H

L

D

OUT

H

L

HI-Z

D

OUT

H

L

HI-Z

D

OUT

H

X

L

HI-Z

D

IN

OUT

HI-Z

X

L

X

L

D

H

L

D

X

H

X

H

X

L

X

H

X

H

L

D

Current

H

L

D

H

L

D

OUT

H

L

HI-Z

D

OUT

H

L

HI-Z

D

OUT

H

X

HI-Z

D

IN

4877 tbl 11

X

L

X

L

D

H

L

D

X

D

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

10

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table^{(1, 2)}

GW

H

L

BWE

H

L

BW¹

BW²

X

BW³

X

BW⁴

X

Operation

Read

X

Read

H

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

X

L

X

H

L

H

L

H

L

H

L

H

L

H

L

H

L

4877 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V2579.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

OE

ZZ

I/O Status

Power

Read

L

H

X

L

H

Data Out

High-Z

Active

Read

Write

High-Z – Data In

High-Z

Active

Deselected

Sleep Mode

Standby

Sleep

High-Z

4877 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

0

A1

A0

1

First Address

0

1

0

1

0

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

4877 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

0

A0

0

A1

0

A0

1

A1

1

A0

0

A1

1

A0

1

First Address

Second Address

Third Address

0

1

0

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

4877 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.42

11

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

7.5ns⁽⁵⁾

8ns

8.5ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max. Unit

Clock Parameter

____

tCYC

Clock Cycle Time

8.5

3

10

4

11.5

4.5

ns

(1)

CH

Clock High Pulse Width

Clock Low Pulse Width

t

____

(1)

3

4

4.5

tCL

Output Parameters

____

CD

t

Clock High to Valid Data

7.5

8

8.5

ns

____

tCDC

Clock High to Data Change

Clock High to Output Active

Clock High to Data High-Z

Output Enable Access Time

Output Enable Low to Output Active

2

0

2

0

2

0

____

(2)

tCLZ

(2)

2

3.5

2

3.5

2

3.5

ns

tCHZ

____

tOE

3.5

____

(2)

0

tOLZ

____

(2)

OHZ

Output Enable High to Output High-Z

3.5

t

Set Up Times

____

tSA

Address Setup Time

1.5

2

ns

SS

t

Address Status Setup Time

Data In Setup Time

SD

t

SW

t

Write Setup Time

tSAV

tSC

Address Advance Setup Time

Chip Enable/Select Setup Time

Hold Times

____

tHA

tHS

Address Hold Time

0.5

ns

Address Status Hold Time

Data In Hold Time

tHD

tHW

tHAV

tHC

Write Hold Time

Address Advance Hold Time

Chip Enable/Select Hold Time

Sleep Mode and Configuration Parameters

____

tZZPW

tZZR⁽³⁾

tCFG ⁽⁴⁾

ZZ Pulse Width

100

34

100

40

100

50

ns

ZZ Recovery Time

Configuration Set-up Time

ns

4877 tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

5. Commercial temperature range only.

6.42

12

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Flow-Through Read Cycle^(1,2)

,

6.42

13

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Flow-Through Read and Write Cycles^(1,2,3)

,

6.42

14

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 - GW Controlled^(1,2,3)

,

6.42

15

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled^(1,2,3)

,

6.42

16

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes^(1,2,3)

,

6.42

17

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW, BWE, BWx

CE, CS1

CS0

OE

(Av)

(Aw)

(Ax)

(Ay)

DATAOUT

,

4877 drw 10

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW

CE, CS1

CS0

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATAIN

,

4877 drw 11

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.42

18

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

t

JCYC

t

JR

tJF

t

JCL

t

JCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

t

JDC

t

JS

t

JH

Device Outputs⁽²⁾/

TDO

t

JRSR

t

JCD

3)

(

x

TRST

M4877 drw 01

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

tJCYC

tJCH

tJCL

tJR

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

ScanRegisterSizes

____

Register Name

Instruction (IR)

Bit Size

____

ns

4

1

40

ns

Bypass (BYR)

5⁽¹⁾

ns

____

JTAG Identification (JIDR)

Boundary Scan (BSR)

32

tJF

5⁽¹⁾

ns

____

Note (1)

____

tJRST

tJRSR

tJCD

tJDC

tJS

50

ns

I4877 tbl 03

____

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

20

ns

____

0

ns

____

25

ns

tJH

JTAG Hold

ns

I4877 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42

19

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field

Revision Number (31:28)

Value

Description

0x2

0x22D, 0x22F

0x33

Reserved for version number.

IDT Device ID (27:12)

Defines IDT part number 71V2577SA and 71V2579SA, respectively.

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

1

I4877 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I4877 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

20

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

OrderingInformation

IDT XXX

Device

X

S

XX

X

Power Speed

Package

Process/

Temperature

Range

Type

Blank

I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

PF**

BG

BQ

100-pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

75*

80

85

Access Time in Tenths of Nanoseconds

Standard Power

Standard Power with JTAG Interface

S

SA

First Generation or current stepping

Second Generation die step

Blank

Y

,

71V2577

71V2579

128K x 36 Flow-Through Burst Synchronous SRAM with 2.5V I/O

256K x 18 Flow-Through Burst Synchronous SRAM with 2.5V I/O

4877 drw 12

*Commercial temperature range only.

** JTAG (SA version) is not available with 100 pin TQFP package

PackageInformation

100-Pin Thin Quad Plastic Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

Information available on the IDT website

6.42

21

IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History

7/23/99

9/17/99

Updatedtonewformat

RevisedI/Opindescription

Revisedblockdiagramforflow-throughfunctionality

Revised ISB1 and IZZ for speeds 7.5 to 8.5ns

Added119-leadBGApackagediagram

Pg. 2

Pg. 3

Pg. 8

Pg. 18

Pg. 20

AddedDatasheetDocumentHistory

12/31/99 Pg. 1, 4, 8, 11, 19

04/04/00 Pg. 18

Pg. 4

AddedIndustrialTemperaturerangeofferings

Add100pinTQFPPackageDiagramOutline

AddcapacitancetableforBGApackage;AddIndustrialtemperaturetotable;insertnoteto

AbsoluteMaxRatingtableandRecommendedOperatingTemperaturetables.

Addnewpackage offering, 13x15mm165fBGA

Correct119BGAPackageDiagramOutline

06/01/00

Pg. 20

07/15/00 Pg. 7

Pg. 8

AddnotereferencetoBG119pinout

AddDNUreference note toBQ165pinout

Pg. 20

UpdateBG119PackageDiagramOutlineDimensions

RemovePreliminarystatus

10/25/00

Pg. 8

Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST

Updated165BGAtableinformationfromTBDto7

UpdateddatasheetwithJTAGinformation

Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiringNCorconnectiontoVss.

04/22/03 Pg.4

06/30/03 Pg. 1,2,3,5-9

Pg. 5-8

Pg. 19,20

Pg. 21-23

Pg. 24

AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions

Removedoldpackageinformationfromthedatasheet

UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation

regardingpackages available IDTwebsite.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726, x4033

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

22


型号：	IDT71V2577SA75BQ
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	128K x 36,256K x 18 3.3V Synchronous SRAMs 2.5V I/O,Flow-Through Outputs Burst Counter,Single Cycle Deselect 128K X 36,256K ×18 3.3V同步SRAM 2.5VI / O，流通型输出突发计数器，单周期取消计数器存储内存集成电路静态存储器时钟
文件：	总22页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V2577SA75BQ [IDT]

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