IDT71V3556SA166BGI_技术文档

IDT71V3556S

IDT71V3558S

IDT71V3556SA

IDT71V3558SA

128K x 36, 256K x 18

3.3VSynchronousZBTSRAMs

3.3V I/O, Burst Counter

PipelinedOutputs

Description

Features

◆

TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

Address and control signals are applied to the SRAM during one

clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit

read or write.

The IDT71V3556/58 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Internally synchronized output buffer enable eliminates the

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

Optional- Boundary Scan JTAG Interface (IEEE 1149.1

◆

Therearethreechipenablepins(CE¹,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, anypendingdata transfers (reads orwrites)willbe

completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected

orawriteisinitiated.

compliant)

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

PinDescriptionSummary

A⁰-A¹⁷

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE2

Output Enable

OE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW4

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

ZZ

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

5281 tbl 01

SEPTEMBER 2004

1

DSC-5281/08

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Descriptioncontinued

The IDT71V3556/58 has an on-chip burst counter. In the burst externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

mode, the IDT71V3556/58 can provide four cycles of data for a single (ADV/LD = HIGH).

address presented to the SRAM. The order of the burst sequence is

The IDT71V3556/58 SRAMs utilize IDT's latest high-performance

defined by the LBO input pin. The LBO pin selects between linear and CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

interleaved burst sequence. The ADV/LD signal is used to load a new 100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Definition⁽¹⁾

Symbol

Pin Function

I/O

Active Description

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

A0-A17

Address Inputs

I

N/A

ADV/LD low, CEN low, and true chip enables.

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it

is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip

deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter

is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled

high.

ADV/LD

Advance / Load

I

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write

access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.

R/

W

Read / Write

Clock Enable

I

Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are

LOW ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low

to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.

CEN

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles

(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte

Individual Byte

Write Enables

I

LOW

write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is

sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be

tied low if always doing write to the entire 36-bit word.

BW1-BW4

CE1, CE2

Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V3556/58. (CE1 or

CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.

The ZBT^TMhas a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.

Chip Enables

Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted

polarity but otherwise identical to CE1 and CE2.

CE2

Chip Enable

Clock

I

HIGH

N/A

This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with

respect to the rising edge of CLK.

CLK

I/O0-I/O31

I/OP1-I/OP4

Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and

triggered by the rising edge of CLK.

Data Input/Output

Linear Burst Order

I/O

I

N/A

Burst order selection input. When LBO is high the Interleaved burstsequence is selected. When LBO is low

the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.

LOW

LBO

OE

Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins

LOW are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal

operation, OE can be tied low.

Output Enable

I

TMS

TDI

Test Mode Select

Test Data Input

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal

pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

I

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP

controller.

Test Data Output

O

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can

JTAG Reset

(Optional)

I

TRST

be left floating. This pin has an internal pullup. Only available in BGA package.

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to

HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal

pulldown.

ZZ

Sleep Mode

VDD

VDDQ

VSS

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

Ground.

5281 tbl 02

NOTE:

1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.

6.422

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

128Kx36 BIT

MEMORY ARRAY

LBO

Address A [0:16]

D

Q

Address

C E1, CE2, CE2

W

R/

Control

CEN

ADV/LD

BW x

DI

DO

D

Q

Control Logic

Clk

Mux

Sel

D

Output Register

Q

Clock

Gate

O E

5281 drw 01a

,

TMS

TDI

TCK

Data I/O [0:31],

I/O P[1:4]

JTAG

(SA Version)

TDO

TRST

(optional)

6.42

3

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

256x18 BIT

MEMORY ARRAY

LBO

Address A [0:17]

D

Q

Address

C E1, CE2, CE2

R/W

CEN

Control

ADV/LD

BW x

DI

DO

D

Q

Control Logic

Clk

Mux

Sel

D

Output Register

Q

Clock

Gate

O E

5281 drw 01b

,

TMS

TDI

TCK

Data I/O [0:15],

I/O P[1:2]

JTAG

(SA Version)

TDO

TRST

(optional)

RecommendedDCOperating

Conditions

Symbol

VDD

VDDQ

VSS

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min.

3.135

0

Typ.

Max.

3.465

0

Unit

V

3.3

V

0

V

____

VIH

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

VDD +0.3

V

(2)

____

VIH

2.0

VDDQ +0.3

0.8

V

(1)

VIL

-0.3

V

5281 tbl 04

NOTES:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

6.442

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

RecommendedOperating

TemperatureandSupplyVoltage

Grade

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

V^SS

0V

V^DD

V^DDQ

Commercial

Industrial

3.3V±5%

5281 tbl 05

NOTES:

1. TA is the "instant on" case temperature.

Pin Configuration - 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

I/OP3

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

2

79

78

77

3

4

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

I/O22

I/O23

VDDQ

I/O9

I/O8

69

68

67

66

(1)

VDD

VSS

VDD

(1)

VDD

(1)

VDD

65

64

VDD

VSS/ZZ⁽³⁾

I/O7

I/O6

VDDQ

VSS

I/O5

I/O4

I/O3

I/O2

VSS

VDDQ

I/O1

I/O0

I/OP1

VSS

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

63

62

61

60

59

58

57

56

55

,

54

53

VDDQ

I/O30

I/O31

I/OP4

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5281 drw 02

Top View

100TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this

pin supports ZZ (sleep mode).

6.42

5

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration - 256K x 18

Absolute Maximum Ratings ⁽¹⁾

Commercial &

Industrial Values

Symbol

Rating

Unit

(2)

V^TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

NC

DDQ

10

A

(3,6)

2

V^TERM

NC

Terminal Voltage with

Respect to GND

-0.5 to V^DD

-0.5 to V^DD+0.5

-0.5 to V^DDQ+0.5

-0 to +70

V

3

4

V

DDQ

V

5

SS

V

76

75

74

73

72

71

70

SS

(4,6)

V^TERM

Terminal Voltage with

Respect to GND

6

NC

I/OP1

7

8

I/O

7

I/O

9

6

I/O

(5,6)

V^TERM

Terminal Voltage with

Respect to GND

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SS

V

SS

V

DDQ

V

DDQ

69

68

67

66

10

I/O

5

I/O

Commercial

Operating Temperature

^oC

W

11

I/O

4

I/O

(1)

DD

V

SS

(1)

DD

V

(7)

DD

(1)

V

DD

T^A

65

64

63

62

DD

(3)

SS

V

SS

V

Industrial

Operating Temperature

-40 to +85

/ZZ

12

I/O

3

I/O

13

I/O

2

61

60

59

DDQ

V

Temperature

Under Bias

-55 to +125

T^BIAS

SS

V

SS

14

I/O

1

I/O

58

57

56

55

15

I/O

0

I/O

NC

P2

I/O

NC

VSS

DDQ

T^STG

Storage

Temperature

-55 to +125

SS

V

54

53

,

V

DDQ

NC

P^T

Power Dissipation

DC Output Current

2.0

50

52

51

I^OUT

mA

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5281 drw 02a

5281 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed VDDQ during power

supply ramp up.

Top View

100TQFP

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as

the input voltage is ≥ VIH.

2. Pins 83 and 84 are reserved for future 8M and 16M respectively.

3. Pin 64 does not have to be connected directly to VSS as long as the input

voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep

mode).

7. TA is the "instant on" case temperature.

100Pin TQFPCapacitance⁽¹⁾

(TA = +25° C, f = 1.0MHz)

119BGACapacitance⁽¹⁾

(TA = +25° C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

V^IN= 3dV

V^OUT= 3dV

Max. Unit

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

C^IN

5

7

pF

7

pF

CI/O

pF

C^I/O

pF

5281 tbl 07

5281 tbl 07a

165fBGACapacitance⁽¹⁾

(TA = +25° C, f = 1.0MHz)

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

TBD pF

CI/O

TBD pF

5281 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.462

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration - 128K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

V

A

NC(2)

2

3

2

9

A

NC

CE

NC

2

CE

LD

ADV/

7

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

V

17

I/O

18

I/O

13

I/O

14

I/O

1

CE

DDQ

V

19

I/O

12

I/O

DDQ

V

OE

20

21

11

10

I/O

NC(2)

I/O

G

H

J

BW

2

3

BW

22

I/O

23

I/O

SS

V

SS

9

I/O

8

I/O

V

R/W

DDQ

DD

V

DD

DDQ

V

DD(1)

V

DD(1)

V

24

26

SS

6

7

I/O

V

CLK

NC

V

I/O

K

L

25

I/O

27

I/O

4

I/O

5

I/O

4

BW

BW 1

DDQ

28

SS

V

3

DDQ

V

M

N

P

R

T

V

I/O

V

I/O

CEN

29

I/O

30

I/O

1

SS

2

I/O

1

I/O

A

V

0

I/O

31

I/O

P4

0

P1

I/O

V

,

5

DD

V

VDD(1)

14

13

NC

A

NC

A

NC

LBO

(5)

10

11

A

NC

A

NC

NC/ZZ

(3)

NC/TDO

NC/TRST^(3,4)

DDQ

V

DDQ

V

NC/TMS

NC/TDI

NC/TCK

U

5281 drw 13A

Top View

Pin Configuration - 256K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

NC(2)

ADV/LD

3

2

9

NC

CE2

NC

2

CE

7

A

DD

V

13

17

A

8

I/O

SS

P1

I/O

NC

V

NC

V

9

I/O

7

I/O

NC

CE1

DDQ

V

6

I/O

DDQ

V

NC

O E

10

I/O

5

I/O

NC

G

H

J

NC(2)

BW 2

11

I/O

SS

4

I/O

NC

V

NC

R/

W

DD(1)

DDQ

V

DD

V

DD

DDQ

V

12

I/O

SS

3

I/O

NC

V

CLK

NC

K

L

13

I/O

SS

2

I/O

NC

V

NC

1

BW

DDQ

V

14

I/O

SS

DDQ

V

NC

M

N

P

R

T

CEN

15

I/O

1

0

SS

1

I/O

NC

A

NC

P2

I/O

0

I/O

NC

A

NC

5

A

DD

V

12

A

NC

VDD(1)

LBO

(5)

10

15

A

14

A

11

A

NC/ZZ

A

NC

,

NC/TRST^(3,4)

(3)

NC/TDO

(3)

DDQ

V

DDQ

V

NC/TMS

NC/TDI

NC/TCK

U

5281drw 13B

Top View

NOTES:

1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. G4 and A4 are reserved for future 8M and 16M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

6.42

7

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration - 128K x 36, 165 fBGA

1

2

3

4

5

6

7

8

ADV/LD

OE

9

10

A8

11

(2)

A

B

C

D

E

F

NC

A7

NC

CE1

BW3

BW4

VSS

VDD

VSS

A2

BW2

BW1

VSS

TRST^{(3, 4)}

CE2

CLK

VSS

NC

CEN

R/W

VSS

(2)

NC

A6

CE2

NC

A9

NC

I/OP3

I/O17

I/O19

I/O21

I/O23

NC

VDDQ

NC

VSS

VDDQ

NC

I/OP2

I/O14

I/O12

I/O10

I/O8

I/O16

I/O18

I/O20

I/O22

VDD

VSS

I/O15

I/O13

I/O11

I/O9

NC

G

H

J

(1)

(5)

VDD

NC/ZZ

I/O25

I/O27

I/O29

I/O31

I/OP4

NC

I/O24

I/O26

I/O28

I/O30

NC

VDDQ

A5

VDDQ

A13

I/O7

I/O5

I/O3

I/O1

NC

I/O6

K

L

M

N

P

I/O4

I/O2

I/O0

(1)

VDD

I/OP1

NC

NC/

(2)

(3)

NC

NC/TDI

NC/TMS⁽³⁾

A1

NC/TDO

A10

A14

A15

(2)

(3)

R

NC

A4

A3

A0

NC/TCK

A11

A12

A16

LBO

5281 tbl 25

Pin Configuration - 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

9

10

A8

11

(2)

A

B

C

D

E

F

NC

A7

NC

ADV/LD

NC

A10

CE1

BW2

NC

CE2

CLK

VSS

NC

CEN

R/W

VSS

(2)

A

6

CE

NC

A

9

NC

2

BW1

VSS

TRST^{(3, 4)}

OE

NC

I/O8

I/O9

I/O10

I/O11

VDDQ

NC

VSS

VDD

VSS

A2

VSS

VDD

VSS

A11

VDDQ

NC

I/O3

I/O2

I/O1

I/O0

NC

A15

I/OP1

I/O7

I/O6

I/O5

I/O4

G

H

J

(1)

(5)

VDD

I/O12

I/O13

I/O14

I/O15

I/OP2

NC

VDD

NC/ZZ

NC

VDDQ

A5

VDDQ

A14

NC

K

L

M

N

P

(1)

VDD

NC/

(2)

(3)

NC

NC/TDI

NC/TMS⁽³⁾

A1

NC/TDO

(2)

(3)

R

NC

A

4

A

3

A

0

NC/TCK

A

12

A

13

A

16

A

17

LBO

5281 tbl 25a

NOTES:

1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.

2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).

6.482

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Synchronous Truth Table ⁽¹⁾

Chip^{(5 )}

Enable

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

CEN

BWx

R/W

(2 cycles later)

(7 )

L

H

X

Select

X

L

H

Valid

X

External

Internal

X

LOAD WRITE

LOAD READ

D

(7 )

Q

(7 )

Valid

LOAD WRITE /

BURST WRITE

D

(Advance burst counter)^{(2 )}

(7 )

L

X

H

X

Internal

LOAD READ /

BURST READ

Q

(Advance burst counter)^{(2 )}

L

H

X

Deselect

L

H

X

DESELECT or STOP^{(3 )}

NOOP

HiZ

X

DESELECT / NOOP

X

(4 )

SUSPEND

Previous Value

5281 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires CE¹= L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

Partial Truth Table for Writes ⁽¹⁾

(3 )

BW1

X

BW2

X

BW3

BW4

OPERATION

R/W

H

L

READ

X

L

X

L

WRITE ALLBYTES

WRITE BYTE 1 (I/O[0:7], I/O^P1)

L

(2 )

L

H

L

H

L

WRITE BYTE 2 (I/O[8:15], I/O^P2)

L

H

L

(2,3)

WRITE BYTE 3 (I/O[16:23], I/O^P3)

L

H

(2,3)

WRITE BYTE 4 (I/O[24:31], I/O^P4)

L

H

NO WRITE

L

H

5281 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

6.42

9

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Interleaved Burst Sequence Table (LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

A0

0

A1

A0

First Address

0

1

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5281 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

0

A1

1

A0

First Address

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5281 tbl 11

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Functional Timing Diagram ⁽¹⁾

CYCLE

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

CLOCK

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A16)

(2)

CONTROL

(R/W , ADV/LD , BW x)

(2)

DATA

D/Q27

D/Q28

D/Q29

D/Q30

D/Q32

D/Q33

D/Q34

D/Q35

D/Q31

I/O [0:31], I/O P[1:4]

,

5281 drw 03

NOTES:

1. This assumes CEN, CE1, CE2, CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.1402

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Device Operation - Showing Mixed Load, Burst,

Deselect and NOOP Cycles ⁽²⁾

CE^{(1 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

L

X

L

X

Load read

Burst read

Load read

n+1

X

L

n+2

A¹

X

Q⁰

n+3

H

X

L

Q⁰⁺¹Deselect or STOP

n+4

X

L

Q¹

Z

NOOP

n+5

A²

X

L

Load read

Burst read

Deselect or STOP

n+6

X

H

L

Z

n+7

X

Q²

n+8

A³

X

L

Q²⁺¹Load write

n+9

X

L

X

L

X

L

Z

Burst write

Load write

n+10

n+11

n+12

n+13

n+14

n+15

n+16

n+17

n+18

n+19

A⁴

X

L

D³

X

L

H

X

L

X

L

D³⁺¹Deselect or STOP

X

D⁴

Z

NOOP

A⁵

A⁶

A⁷

X

Load write

Load read

Load write

Burst write

Load read

H

L

X

L

Z

L

D⁵

Q⁶

D⁷

X

H

X

L

X

L

A⁸

X

L

X

L

X

L

D⁷⁺¹Burst read

A⁹

Q⁸

Load write

5281 tbl 12

NOTES:

1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

2. H = High; L = Low; X = Don’t Care; Z = High Impedance.

Read Operation ⁽¹⁾

CE⁽²⁾

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

L

X

L

X

L

X

Address and Control meet setup

Clock Setup Valid

n+1

n+2

X

Q⁰

Contents of Address A⁰Read Out

5281 tbl 13

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.42

11

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Burst Read Operation ⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

L

H

L

X

L

X

Address and Control meet setup

Clock Setup Valid, Advance Counter

Address A⁰Read Out, Inc. Count

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

X

L

X

Q⁰

X

Q⁰⁺¹Address A⁰⁺¹Read Out, Inc. Count

X

Q⁰⁺²

Q⁰⁺³

Q⁰

Address A⁰⁺²Read Out, Inc. Count

Address A⁰⁺³Read Out, Load A¹

Address A⁰Read Out, Inc. Count

Address A¹Read Out, Inc. Count

A¹

X

H

L

X

L

X

Q¹

A²

Q¹⁺¹Address A¹⁺¹Read Out, Load A²

5281 tbl 14

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation ⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

X

L

X

Address and Control meet setup

Clock Setup Valid

n+1

n+2

X

D⁰

Write to Address A⁰

5281 tbl 15

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Burst Write Operation ⁽¹⁾

CE^{(2 )}

L

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

H

L

X

Address and Control meet setup

Clock Setup Valid, Inc. Count

Address A⁰Write, Inc. Count

Address A⁰⁺¹Write, Inc. Count

Address A⁰⁺²Write, Inc. Count

Address A⁰⁺³Write, Load A¹

Address A⁰Write, Inc. Count

Address A¹Write, Inc. Count

Address A¹⁺¹Write, Load A²

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

X

L

X

D⁰

X

D⁰⁺¹

D⁰⁺²

D⁰⁺³

D⁰

X

A1

X

L

H

L

X

L

X

D¹

A²

D¹⁺¹

5281 tbl 16

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.1422

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used ⁽¹⁾

CE^{(2 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

H

X

H

X

H

L

X

L

X

L

H

L

H

L

X

L

X

Address and Control meet setup

Clock n+1 Ignored

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

L

A¹

X

Clock Valid

X

L

Q⁰

Q¹

Q²

Clock Ignored. Data Q⁰is on the bus.

Address A⁰Read out (bus trans.)

Address A¹Read out (bus trans.)

X

A²

A³

A⁴

L

Address A²Read out (bus trans.)

5281 tbl 17

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation with Clock Enable Used ⁽¹⁾

CE^{(2 )}

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

n

A⁰

X

L

X

L

X

L

X

L

X

L

H

L

H

L

X

L

X

L

X

Address and Control meet setup.

Clock n+1 Ignored.

Clock Valid.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

L

A¹

X

L

X

Clock Ignored.

X

Clock Ignored.

A²

A³

A⁴

D⁰

D¹

D²

Write Data D⁰

L

Write Data D¹

L

Write Data D²

5281 tbl 18

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.42

13

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Read Operation with CHIP Enable Used ⁽¹⁾

CE^{(2 )}

H

L

(3 )

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

Comments

I/O

n

X

H

X

H

X

H

X

L

X

L

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Deselected.

A⁰

X

Z

Address and Control meet setup

Deselected or STOP.

Address A⁰Read out. Load A¹.

Deselected or STOP.

H

L

Z

A¹

X

Q⁰

Z

H

L

X

L

X

Q₁

Z

Address A Read out. Deselected.

1

A²

X

L

Address and control meet setup.

Deselected or STOP.

H

Z

X

Q²

Address A²Read out. Deselected.

5281 tbl 19

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

Write Operation with Chip Enable Used ⁽¹⁾

CE^{(2 )}

H

L

(3 )

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

Comments

I/O

n

X

L

X

L

X

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

?

Deselected.

A⁰

X

Z

Address and Control meet setup

Deselected or STOP.

X

L

H

L

X

L

Z

A¹

X

D⁰

Z

Address D⁰Write in. Load A¹.

Deselected or STOP.

X

L

H

L

X

L

X

D¹

Z

Address D¹Write in. Deselected.

Address and control meet setup.

Deselected or STOP.

A²

X

H

X

Z

X

D²

Address D²Write in. Deselected.

5281 tbl 20

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.1442

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(VDD = 3.3V +/-5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

V^DD= Max., V^IN= 0V to V^DD

5

µA

(1 )

___

LBO, JTAG and ZZ Input Leakage Current

DD

IN

|I^LI|

V

= Max., V = 0V to V

DD

30

5

µA

V

|I^LO|

V^OL

V^OH

Output Leakage Current

V^OUT= 0V to V^DDQ, Device Deselected

I^OL= +8mA, V^DD= Min.

Output Low Voltage

0.4

___

Output High Voltage

I^OH= -8mA, V^DD= Min.

2.4

V

5281 tbl 21

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range ⁽¹⁾(VDD = 3.3V +/-5%)

200MHz

166MHz

133MHz

100MHz

Symbol

Parameter

Test Conditions

Com'l Only Com'l

Ind

Com'l

Ind

Com'l

Ind

Unit

I^DD

Device Selected, Outputs Open,

ADV/LD = X, V^DD= Max.,

Operating Power

Supply Current

400

40

350

40

360

300

40

310

250

40

255

mA

(2)

V^IN> V^IHor < V^IL, f = f^MAX

I^SB1

Device Deselected, Outputs Open,

V^DD= Max., V^IN> V^HDor < V^LD, f

CMOS Standby

Power Supply Current

45

130

45

120

45

110

45

mA

(2,3)

= 0

I^SB2

Device Deselected, Outputs Open,

V^DD= Max., V^IN> V^HDor < V^LD, f

Clock Running Power

Supply Current

130

40

120

40

110

40

100

40

(2.3)

= f^MAX

I^SB3

Device Selected, Outputs Open,

CEN > V^IH, V^DD= Max.,

Idle Power

Supply Current

mA

(2,3)

V^IN> V^HDor < V^LD, f = f^MAX

5281 tbl 22

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.

AC Test Loads

AC Test Conditions

VDDQ/2

50Ω

(VDDQ = 3.3V)

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

,

6

5

4

Input Rise/Fall Times

5281 drw 04

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

See Figure 1

3

∆tCD

(Typical, ns)

5281 tbl 23

2

1

,

20 30 50

80 100

Capacitance (pF)

200

5281 drw 05

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

15

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)

200MHz⁽⁶⁾

166MHz

133MHz

100MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

tCYC

Clock Cycle Time

5

6

7.5

10

ns

MHz

ns

____

(1)

Clock Frequence

200

166

133

100

tF

____

(2)

Clock High Pulse Width

Clock Low Pulse Width

1.8

2.2

3.2

tCH

____

(2)

CL

ns

t

Output Parameters

____

tCD

Clock High to Valid Data

3.2

3.5

4.2

5

ns

____

tCDC

Clock High to Data Change

Clock High to Output Active

Clock High to Data High-Z

1

____

(3,4,5)

tCLZ

(3,4,5)

1

3

1

3

1

3

1

3.3

ns

tCHZ

____

tOE

Output Enable Access Time

Output Enable Low to Data Active

Output Enable High to Data High-Z

3.2

3.5

4.2

5

____

(3,4)

0

tOLZ

____

(3,4)

3.5

4.2

5

tOHZ

Set Up Times

____

tSE

Clock Enable Setup Time

Address Setup Time

1.5

1.7

2.0

ns

tSA

tSD

Data In Setup Time

tSW

Read/Write (R/W) Setup Time

tSADV

Advance/Load (ADV/ ) Setup Time

LD

tSC

Chip Enable/Select Setup Time

tSB

Byte Write Enable (BWx) Setup Time

Hold Times

____

tHE

Clock Enable Hold Time

0.5

ns

HA

t

Address Hold Time

tHD

Data In Hold Time

tHW

tHADV

tHC

Read/Write (R/W) Hold Time

Advance/Load (ADV/LD) Hold Time

Chip Enable/Select Hold Time

Byte Write Enable (BWx) Hold Time

tHB

ns

5281 tbl 24

NOTES:

1. tF = 1/tCYC.

2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

3. Transition is measured ±200mV from steady-state.

4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.

The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,

which is a Max. parameter (worse case at 70 deg. C, 3.135V).

6. Commercial temperature range only.

6.1462

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle ^(1,2,3,4)

,

6.42

17

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycles ^(1,2,3,4,5)

,

6.1482

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Read and Write Cycles ^(1,2,3)

,

6.42

19

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CEN Operation ^(1,2,3,4)

,

6.2402

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation ^(1,2,3,4)

,

6.42

21

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

t

JCYC

t

JR

t

JF

t

JCL

t

JCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

JDC

t

JS

t

JH

Device Outputs⁽²⁾/

TDO

t

JRSR

t

JCD

3)

(

x

TRST

M5281 drw 01

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

t^JCYC

t^JCH

t^JCL

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

ScanRegisterSizes

____

Register Name

Instruction (IR)

Bit Size

____

ns

4

1

40

ns

Bypass (BYR)

t^JR

5^{(1 )}

ns

____

JTAG Identification (JIDR)

Boundary Scan (BSR)

32

t^JF

5^{(1 )}

ns

____

Note (1)

____

t^JRST

t^JRSR

t^JCD

t^JDC

t^JS

50

ns

I5281 tbl 03

____

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

20

ns

____

0

ns

____

25

ns

t^JH

JTAG Hold

ns

I5281 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.2422

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field

Revision Number (31:28)

Value

Description

0x2

0x208, 0x20A

0x33

Reserved for version number.

IDT Device ID (27:12)

Defines IDT part number 71V3556SA and 71V3558SA, respectively.

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

1

I5281 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I5281 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

23

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline

6.2442

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

25

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.2462

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation ⁽¹⁾

OE

tOE

tOHZ

tOLZ

DATAOUT

Valid

,

5281 drw 11

NOTE:

1. A read operation is assumed to be in progress.

OrderingInformation

X

IDT

XXXX

XX

X

Process/

Temperature

Range

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Blank

I

Restricted Hazardous Substance Device

,

G

PF**

BG

BQ

100-pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

200*

166

133

100

Clock Frequency in Megahertz

Standard Power

Standard Power with JTAG interface

S

SA

128Kx36 Pipelined ZBT SRAM with 3.3V I/O

256Kx18 Pipelined ZBT SRAM with 3.3V I/O

IDT71V3556

IDT71V3558

5281 drw 12

*

C o m m e rcia l tem p era tu re ran ge only

** JT A G (S A V e rsio n) is n ot a va ilab le w ith 1 0 0-pin T Q FP p ackag e

6.42

27

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

DatasheetDocumentHistory

6/30/99

8/23/99

Updatedtonewformat

AddedSmartZBTfunctionality

Pg. 4, 5

Pg. 6

Added Note 4 and changed Pins 38, 42, and 43 to DNU

Changed U2–U6 to DNU

Pg. 14

Pg. 15

AddedSmartZBTACElectricalCharacteristics

ImprovedtCD andtOE(MAX)at166MHz

Revised tCHZ(MIN) for f ≤ 133 MHz

Revised tOHZ (MAX) for f ≤ 133 MHz

ImprovedtCH, tCL forf≤166MHz

Improvedsetuptimesfor100–200MHz

Pg. 22

Pg. 24

Pg. 14

Pg. 15

AddedBGApackagediagrams

AddedDatasheetDocumentHistory

RevisedACElectricalCharacteristicstable

Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz

RemovedSmartfunctionality

AddedIndustrialTemperaturerangeofferings atthe100to166MHzspeedgrades.

InsertclarificationnotetoRecommendedOperatingTemperature andAbsoluteMax

Ratingstables

10/4/99

12/31/99

04/30/00

Pg. 5, 6

Pg. 6

AddBGAcapacitancetable

Pg. 5,6, 7

Pg. 21

AddnotetoTQFPandBGAPinConfigurations;correctedtypoinpinout

Add100pinTQFPpackageDiagramOutline

Add new package offering, 13 x 15mm 165 fBGA

Correct119BGAPackageDiagramOutline

AddZZsleepmode reference note toBG119, PK100andBQ165pinouts

UpdateBQ165pinout

05/26/00

07/26/00

Pg. 23

Pg. 5-8

Pg. 8

Pg. 23

UpdateBG119packagediagramoutlinedimensions

RemovePreliminarystatus

10/25/00

Pg. 8

Pg. 1-8, 15,22,23,27

Pg. 7

Add note to pin N5 on BQ165, reserved for JTAG TRST

AddedJTAG"SA"versionfunctionality

Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)

and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).

Adding"Restrictedhazardoussubstancedevice"toorderinginformation.

1/24/02

9/30 /04

Pg. 27

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

ZBT^®andZeroBusTurnaroundaretrademarksofIntegratedDeviceTechnology,Inc.andthearchitectureissupportedbyMicronTechnologyandMotorolaInc.

6.2482


型号：	IDT71V3556SA166BGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	暂无描述计数器静态存储器
文件：	总28页 (文件大小：1011K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V3556SA166BGI [IDT]

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