IDT71V3557S85PF9_技术文档

128K x 36, 256K x 18,

IDT71V3557S

IDT71V3559S

IDT71V3557SA

IDT71V3559SA

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

Features

it read or write.

◆

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

The IDT71V3557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted

when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

selectedorawriteisinitiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates

the need to control OE

◆

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

◆

Description

TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

TM

given the name ZBT , or Zero Bus Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE², CE²

Output Enable

OE

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW⁴

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

ZZ

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

Static

5282 tbl 01

MAY 2002

1

DSC-5282/06

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Definitions ⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁷

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

ADV/LD low, CEN low, and true chip enables.

ADV/LD

Advance / Load

I

N/A

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it

is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip

deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is

sampled high.

R/W

Read / Write

Clock Enable

I

N/A

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write

access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.

LOW

Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock

are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if

the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge

of clock.

CEN

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write

cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW¹-BW⁴) must be valid.

The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when

R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW¹-BW⁴

can all be tied low if always doing write to the entire 36-bit word.

BW BW

¹-

4

Chip Enables

Synchronous active low chip enable. CE¹and CE²are used with CE²to enable the IDT71V3557/59. (CE¹or

CE¹, CE²

2

CE sampled high or CE sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect

cycle. The ZBT^TMhas a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is

initiated.

2

1

2

CE

Chip Enable

Clock

I

HIGH

N/A

Synchronous active high chip enable. CE is used with CE and CE to enable the chip. CE has inverted

polarity but otherwise identical to CE¹and CE².

CLK

This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made

with respect to the rising edge of CLK.

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

Linear Burst Order

Output Enable

I/O

I

N/A

Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data

output path is flow-through (no output register).

LOW

Burstorder selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low

the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation..

LBO

OE

I

Asynchronous output enable. OE must be low to read data from the 71V3557/59. When OE is HIGH the I/O

pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In

normal operation, OE can be tied low.

TMS

TDI

Test Mode Select

Test Data Input

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

I

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the

TAP c o ntro lle r.

Test Data Output

O

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can

be left floating. This pin has an internal pullup.

JTAG Reset

(Optional)

I

LOW

HIGH

TRST

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to

its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal

pulldown.

ZZ

Sleep Mode

V^DD

V^DDQ

V^SS

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

Ground.

5282 tbl 02

NOTE:

1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.

6.42

2

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram 128K x 36

LBO

128K x 36 BIT

MEMORY ARRAY

Address A [0:16]

D

Q

Address

CE1, CE2 CE2

R/

W

Control

CEN

ADV/LD

DI

DO

BWx

D

Q

Control Logic

Clk

Mux

Sel

Clock

Gate

OE

TMS

TDI

TCK

Data I/O [0:31], I/O P[1:4]

,

JTAG

(SA Version)

TDO

5282 drw 01

TRST

(optional)

6.42

3

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Functional Block Diagram 256K x 18

256K x 18 BIT

MEMORY ARRAY

LBO

Address A [0:17]

D

Q

Address

CE1, CE2 CE2

R/W

CEN

Control

ADV/LD

BWx

DI

DO

D

Q

Control Logic

Clk

Mux

Sel

Clock

Gate

OE

,

Data I/O [0:15], I/O P[1:2]

TMS

TDI

TCK

JTAG

(SA Version)

5282 drw 01a

TDO

TRST

(optional)

RecommendedDCOperating

Conditions

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Ground

Min. Typ.

3.135 3.3

Max.

3.465

0

Unit

DD

V

DDQ

V

SS

V

0

____

IH

V

DD

+ 0.3

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

V

(2)

____

IH

V

DDQ

2.0

V

+ 0.3

-0.3⁽¹⁾

0.8

V

IL

V

5282 tbl 04

NOTES:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

6.42

4

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

RecommendedOperating

TemperatureandSupplyVoltage

Grade

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

VSS

0V

VDD

VDDQ

Commercial

Industrial

3.3V±5%

5282 tbl 05

NOTES:

1. TA is the "instant on" case temperature.

Pin Configuration 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

2

3

4

V

DDQ

VDDQ

5

VSS

76

75

74

73

V

SS

6

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

SS

VDDQ

V

DDQ

69

68

67

66

I/O22

I/O

9

I/O8

I/O23

(1)

VSS

V

SS

(1)

V

DD

V

SS

(2)

65

64

63

62

V

DD

V

DD

(1,4)

V

SS/ZZ

V

SS

I/O24

I/O25

I/O

7

6

61

60

59

V

DDQ

V

DDQ

SS

V

SS

I/O26

I/O27

I/O28

I/O29

I/O

5

58

57

56

55

4

3

2

V

SS

V

SS

54

53

V

DDQ

VDDQ

I/O30

I/O31

I/OP4

I/O

1

0

52

51

,

I/OP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5282 drw 02

Top View

100TQFP

NOTES:

1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL.

2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.

3. Pins 83 and 84 are reserved for future 8M and 16M respectively.

4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.

6.42

5

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 18

Absolute Maximum Ratings ⁽¹⁾

Commercial &

Industrial Values

Symbol

Rating

Unit

(2)

TERM

V

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

NC

VDDQ

VSS

NC

I/O8

I/O9

VSS

VDDQ

I/O10

I/O11

VSS

VDD

A10

NC

VDDQ

VSS

NC

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

(3,6)

(4,6)

(5,6)

TERM

DD

V

Terminal Voltage with

Respect to GND

-0.5 to V

V

2

3

4

5

76

75

74

73

TERM

V

DD

Terminal Voltage with

Respect to GND

-0.5 to V +0.5

6

7

8

9

72

71

TERM

V

DDQ

Terminal Voltage with

Respect to GND

-0.5 to V +0.5

V

10

11

70

69

68

67

66

65

64

63

62

61

60

59

12

Commercial

Operating Temperature

-0 to +70

-40 to +85

-55 to +125

^oC

W

13

(1)

14

(7)

(1)

A

T

15

VSS

(2)

16

VDD

VSS/ZZ

I/O3

I/O2

VDDQ

Industrial

Operating Temperature

(1,4)

17

VSS

I/O12

I/O13

VDDQ

VSS

I/O14

18

19

20

BIAS

T

Temperature

Under Bias

21

VSS

I/O1

22

23

I/O15

I/OP2

NC

VSS

VDDQ

NC

58

57

56

55

I/O0

NC

VSS

VDDQ

NC

24

STG

T

Storage

Temperature

25

26

,

27

54

53

T

28

P

Power Dissipation

DC Output Current

2.0

50

29

NC

52

51

NC

30

OUT

I

mA

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5282 tbl 06

5282 drw 02a

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed VDDQ during power

supply ramp up.

Top View

100TQFP

NOTES:

1. Pins14,64,and66donothavetobeconnecteddirectlytoVSSaslongastheinputvoltage

is < VIL.

2. Pin 16 does not have to be connected directly to VDD as long as the input voltage

is > VIH.

3. Pins 83 and 84 are reserved for future 8M and 16M respectively.

4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.

7. TA is the "instant on" case temperature.

100TQFPCapacitance⁽¹⁾

(TA = +25°C, F = 1.0MHZ)

119BGACapacitance⁽¹⁾

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

(TA = +25°C, F = 1.0MHZ)

Symbol

CIN

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

5

7

pF

7

pF

CI/O

pF

5282 tbl 07

CI/O

pF

5282 tbl 07a

119BGACapacitance⁽¹⁾

(TA = +25°C, F = 1.0MHZ)

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

TBD

pF

CI/O

pF

5282 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

6

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

NC(3)

ADV/LD

2

3

2

9

NC

CE

NC

2

CE

7

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

V

17

I/O

18

I/O

13

I/O

14

I/O

1

CE

DDQ

V

19

I/O

12

I/O

DDQ

V

OE

20

21

11

10

I/O

NC(3)

I/O

G

H

J

2

BW3

BW

22

I/O

23

I/O

SS

V

SS

V

9

I/O

8

I/O

R/W

DDQ

DD

V

DD

DDQ

V

DD(2)

SS(1)

V

24

I/O

26

I/O

SS

4

SS

6

I/O

7

I/O

CLK

NC

V

K

L

25

I/O

27

I/O

4

I/O

5

I/O

1

BW

DDQ

28

SS

3

DDQ

V

I/O

V

I/O

M

N

P

R

T

CEN

29

I/O

30

I/O

1

0

2

I/O

1

I/O

A

31

I/O

P4

I/O

0

I/O

P1

I/O

A

5

DD

V

VSS(1)

14

13

NC

A

NC

LBO

(6)

10

11

A

NC

A

NC

NC/ZZ

,

(4)

(4,5)

DDQ

V

DDQ

V

NC/TDI

NC/TCK

NC/TMS

U

NC/TRST

NC/TDO

5282 drw 13A

Top View

Pin Configuration - 256K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

NC(3)

ADV/LD

3

2

9

NC

CE2

NC

2

CE

7

A

DD

V

13

17

A

8

I/O

SS

7

I/O

NC

V

NC

V

9

6

I/O

NC

DDQ

I/O

NC

1

CE

NC

5

I/O

DDQ

V

OE

10

4

I/O

NC

I/O

NC

G

H

J

NC(3)

BW2

11

I/O

SS

V

SS

3

I/O

V

NC

R/W

DD(2)

SS(1)

DDQ

V

DD

V

DD

DDQ

V

12

SS

2

I/O

NC

I/O

NC

CLK

NC

V

NC

K

L

13

I/O

SS

1

I/O

V

NC

1

BW

DDQ

V

14

SS

DDQ

V

I/O

NC

V

NC

M

N

P

R

T

CEN

15

1

0

I/O

NC

A

NC

P2

I/O

P1

I/O

A

NC

5

A

DD

V

12

A

NC

DDQ

VSS(1)

14

LBO

NC

(6)

10

15

11

A

NC/ZZ

A

NC

A

,

(4)

(4,5)

(4)

DDQ

V

NC/TDI

NC/TCK

NC/TDO

NC/TRST

V

NC/TMS

U

5282 drw 13B

Top View

NOTES:

1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.

2. J3 does not have to be directly connected directly to VDD as long as the input voltage is ≥VIH.

3. G4 and A4 are reserved for future 8M and 16M respectively.

4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.

6. Pin T7 supports ZZ (sleep mode) for the latest die revisions.

6.42

7

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 165 fBGA

1

2

3

4

5

BW²

BW¹

VSS

6

7

8

9

10

A8

11

(3)

A

B

C

D

E

F

NC

A7

ADV/LD

NC

CE¹

BW³

BW⁴

VSS

VDD

VSS

A2

CE²

CLK

VSS

NC

CEN

R/W

VSS

VSS⁽¹⁾

(3)

NC

A6

CE2

NC

A9

NC

OE

I/OP3

I/O17

I/O19

I/O21

I/O23

VSS⁽¹⁾

I/O25

I/O27

I/O29

I/O31

I/OP4

NC

VDDQ

NC

VSS

VDD

VSS

A10

VDDQ

NC

I/OP2

I/O14

I/O12

I/O10

I/O8

I/O16

I/O18

I/O20

I/O22

VSS

I/O15

I/O13

I/O11

I/O9

NC

VSS

G

H

J

VSS

(2)

(6)

VDD

VSS

NC/ZZ

I/O24

I/O26

I/O28

I/O30

NC

VDDQ

A5

VSS

VDDQ

A13

I/O7

I/O5

I/O3

I/O1

NC

I/O6

K

L

M

N

P

VSS

I/O4

VSS

I/O2

VSS

I/O0

NC/TRST^{(4, 5)}

I/OP1

NC

(3)

(4)

NC

NC/TDI

A1

NC/TDO

A14

A15

(3)

(4)

R

NC

A4

A3

NC/TMS⁽⁴⁾

A0

NC/TCK

A11

A12

A16

LBO

5282 tbl 25

Pin Configuration - 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

(3)

A

B

C

D

E

F

NC

A

NC

BW

ADV/LD

OE

NC

A

8

A

7

10

CE

BW

CE

CEN

R/W

1

2

(3)

A

6

CE

2

NC

CLK

NC

A

9

NC

1

NC

I/O

V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

NC

I/O

P1

DDQ

NC

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

7

8

DDQ

NC

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

6

9

DDQ

NC

I/O

10

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

5

DDQ

G

H

J

NC

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

4

11

DDQ

Vss⁽¹⁾

V

DD

NC

V

DD

V

SS

V

SS

V

SS

V

DD

NC

NC/ZZ

(2)

(6)

I/O

NC

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

3

NC

12

DDQ

K

L

M

N

P

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

2

NC

13

DDQ

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

1

NC

14

DDQ

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

0

NC

15

DDQ

(1)

I/O

V

DDQ

V

SS

TRST^{(4, 5)}

NC

V

SS

V

SS

V

DDQ

NC

P2

NC/

(3)

(4)

NC

LBO

NC

A

5

A

2

NC/TDI

A

1

NC/TDO

A

11

A

15

NC

14

(3)

(4)

R

NC

A

4

A

3

NC/TMS⁽⁴⁾

A

0

NC/TCK

A

12

A

16

A

17

13

5282 tbl 25a

NOTES:

1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.

2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.

3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively.

4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.

5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.

6. Pin H11 supports ZZ (sleep mode) for the latest die revisions.

6.42

8

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Synchronous Truth Table ⁽¹⁾

,

1

CEN

CE

BWx

R/W

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(5)

2

(One cycle later)

(7)

L

H

X

L

X

L

H

Valid

X

External

Internal

X

LOAD WRITE

LOAD READ

D

(7)

Q

(7)

Valid

LOAD WRITE /

BURST WRITE

D

(Advance burst counter)⁽²⁾

(7)

L

X

H

X

Internal

LOAD READ /

BURST READ

Q

(Advance burst counter)⁽²⁾

L

H

X

H

X

L

H

X

DESELECT or STOP⁽³⁾

NOOP

HIZ

DESELECT / NOOP

X

(4)

SUSPEND

Previous Value

5282 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state one cycle after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires CE¹= L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z during device power-up.

7. Q - data read from the device, D - data written to the device.

Partial Truth Table for Writes ⁽¹⁾

(3)

1

2

3

4

BW

X

L

BW

X

L

BW

OPERATION

R/W

H

L

READ

X

L

X

L

WRITE ALL BYTES

(2)

P1

WRITE BYTE 1 (I/O[0:7], I/O )

L

H

L

H

L

H

L

P2

WRITE BYTE 2 (I/O[8:15], I/O )

L

H

(2,3)

P3

WRITE BYTE 3 (I/O[16:23], I/O )

L

H

(2,3)

P4

WRITE BYTE 4 (I/O[24:31], I/O )

L

H

NO WRITE

L

H

5282 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for x18 configuration.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

A0

0

A1

1

A0

First Address

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5282 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

6.42

9

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

A0

0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5282 tbl 11

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Functional Timing Diagram ⁽¹⁾

CYCLE

CLOCK

n+29

n+30

n+31

n+32

n+33

n+34

n+35

n+36

n+37

(2)

ADDRESS

A29

C29

A30

C30

A31

C31

A32

C32

A33

C33

A34

C34

A35

C35

A36

C36

A37

C37

(A0 - A16)

CONTROL

(R/W, ADV/LD, BWx)

(2)

DATA

D/Q28

D/Q29

D/Q30

D/Q31

D/Q32

D/Q33

D/Q34

D/Q35

D/Q36

,

I/O [0:31], I/O P[1:4]

5282 drw 03

NOTES:

1. This assumes CEN, CE¹, CE2 and CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

6.42

10

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Device Operation - Showing Mixed Load, Burst,

Deselect and NOOP Cycles ⁽²⁾

(1)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

CE¹

0

1

n

A

H

X

H

X

H

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

L

X

L

D

Load read

Burst read

0

Q

n+1

X

L

1

A

0+1

n+2

L

Q

Load read

Deselect or STOP

NOOP

1

Q

n+3

X

H

X

L

n+4

X

L

Z

2

A

n+5

Load read

Burst read

Deselect or STOP

Load write

Burst write

Load write

Deselect or STOP

NOOP

2

Q

n+6

X

H

L

2+1

Q

n+7

L

3

A

n+8

X

L

Z

3

D

n+9

X

L

X

L

4

A

3+1

D

n+10

n+11

n+12

n+13

n+14

n+15

n+16

n+17

n+18

n+19

L

4

D

X

L

H

X

L

X

L

Z

A⁵

Load write

Load read

Load write

Burst write

Load read

Burst read

Load write

6

A

5

D

H

L

X

L

7

A

6

Q

L

7

D

X

H

X

L

X

L

X

L

8

A

7+1

D

X

L

8

Q

X

L

9

A

8+1

Q

L

5282 tbl 12

NOTES:

1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

2. H = High; L = Low; X = Don't Care; Z = High Impedence.

6.42

11

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

0

n

A

H

X

L

X

L

X

Address and Control meet setup

0

Q

0

n+1

X

Contents of Address A Read Out

5282 tbl 13

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE²timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Burst Read Operation ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

n

A0

X

A1

X

H

X

H

X

H

L

H

L

X

L

X

L

X

Address and Control meet setup

Address A0 Read Out, Inc. Count

n+1

n+2

n+3

n+4

n+5

n+6

n+7

Q0

Q0+1 Address A0+1 Read Out, Inc. Count

Q0+2

Q0+3

Q0

Address A0+2 Read Out, Inc. Count

Address A0+3 Read Out, Load A1

Address A0 Read Out, Inc. Count

1

Q

1

H

L

X

L

Address A Read Out, Inc. Count

2

A

1+1

Q

1+1

2

Address A Read Out, Load A

5282 tbl 14

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Write Operation ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

n

A0

X

L

X

Address and Control meet setup

0

D

0

n+1

X

Write to Address A

5282 tbl 15

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE²timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Burst Write Operation ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

0

n

A

L

X

L

H

L

X

L

X

Address and Control meet setup

0

D

0

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

Address A Write, Inc. Count

0+1

D

0+1

Address A Write, Inc. Count

0+2

D

0+2

Address A Write, Inc. Count

0+3

D

0+3

1

Address A Write, Load A

1

A

0

D

0

Address A Write, Inc. Count

1

D

1

X

L

H

L

X

L

Address A Write, Inc. Count

2

A

1+1

D

1+1

2

Address A Write, Load A

5282 tbl 16

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

6.42

12

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

0

n

A

H

X

H

X

H

L

X

L

X

L

X

L

X

L

H

L

H

L

X

L

X

AddressA and Control meet setup

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

Clock n+1 Ignored

1

A

0

Q

0

1

Address A Read out, Load A

0

Q

0

X

Clock Ignored. Data Q is on the bus.

0

Q

0

Clock Ignored. Data Q is on the bus.

2

A

1

Q

1

2

Address A Read out, Load A

3

A

2

Q

2

3

Address A Read out, Load A

4

A

3

Q

3

4

Address A Read out, Load A

5282 tbl 17

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE²timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

Write Operation with Clock Enable Used ⁽¹⁾

(2)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

I/O

Comments

1

CE

0

n

A

L

X

L

X

L

X

L

X

L

X

L

X

L

H

L

H

L

X

L

X

L

X

Address A and Control meet setup.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

X

Clock n+1 Ignored.

1

A

0

D

0

1

Write data D , Load A .

X

Clock Ignored.

2

A

1

D

1

2

Write Data D , Load A

3

A

2

D

2

3

Write Data D , Load A

4

A

3

D

3

4

Write Data D , Load A

5282 tbl 18

NOTES:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE²timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

6.42

13

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Read Operation with Chip Enable Used ⁽¹⁾

(2)

(3)

CEN

BWx

OE

Cycle

Address

R/W

ADV/LD

Comments

1

CE

I/O

n

X

H

X

H

X

H

X

L

H

L

X

L

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

Z

0

A

0

Address A and Control meet setup.

0

X

H

L

Q

Z

Address A read out, Deselected.

1

A

1

X

L

Address A and Control meet setup.

1

X

H

L

Q

Z

Address A read out, Deselected.

X

L

Deselected.

2

A

2

Address A and Control meet setup.

2

Q

2

X

H

Address A read out, Deselected.

X

Z

Deselected.

5282 tbl 19

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

3. Device outputs are ensured to be in High-Z during device power-up.

Write Operation with Chip Enable Used ⁽¹⁾

CE⁽²⁾

CEN

BWx

OE

Cycle

Address

R/

W

ADV/LD

I/O

Comments

n

X

L

H

L

X

L

X

?

Deselected.

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

X

L

H

Z

0

A

0

L

Address A and Control meet setup

0

X

L

H

X

L

D

Data D Write In, Deselected.

1

A

1

L

Z

Address A and Control meet setup

1

X

L

H

X

L

D

Data D Write In, Deselected.

H

Z

Deselected.

2

A

2

L

Address A and Control meet setup

2

X

H

X

D

Data D Write In, Deselected.

H

Z

Deselected.

5282 tbl 20

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.

2. CE = L is defined as CE¹= L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

6.42

14

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

LI

|I |

DD

V

IN

DD

Input Leakage Current

= Max., V = 0V to V

5

µA

(1)

___

LBO, JTAG and ZZ Input Leakage Current

Output Leakage Current

Output Low Voltage

LI

DD

IN

DD

|I |

V

= Max., V = 0V to V

OUT

V = 0V to V

30

5

µA

V

LO

|I |

CC

OL

V

OL

DD

I

= +8mA, V = Min.

0.4

___

OH

V

OH

I

DD

Output High Voltage

= -8mA, V = Min.

2.4

V

5282 tbl 21

NOTE:

1. The LBO, JTAG and ZZ pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.

DC Electrical Characterics Over the Operating

Temperature and Supply Voltage Range ⁽¹⁾(VDD = 3.3V +/-5%)

7.5ns

Com'l Only

275

8ns

8.5ns

Symbol

Parameter

Test Conditions

Com'l

Ind

Com'l

Ind

Unit

Operating Power

Supply Current

Device Selected, Outputs Open,

250

260

225

235

mA

DD

I

DD

ADV/LD = X, V = Max.,

(2)

IN

IH

IL

MAX

V > V or < V , f = f

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open,

40

105

40

100

40

45

110

45

40

95

40

45

105

45

mA

SB1

I

DD

IN HD LD

= Max., V > V or < V ,

V

(2,3)

f = 0

Clock Running Power

Supply Current

Device Deselected, Outputs Open,

SB2

I

DD

IN HD LD

= Max., V > V or < V ,

V

(2,3)

MAX

f = f

Idle Power

Device Selected, Outputs Open,

mA

SB3

I

IH DD

Supply Current

CEN > V , V = Max.,

(2,3)

IN

HD

LD

MAX

V > V or < V , f = f

5282 tbl 22

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

VDDQ/2

AC Test Loads

AC Test Conditions (VDDQ = 3.3V)

Input Pulse Levels

0 to 3V

50Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

2ns

I/O

0

Ω

Z = 50

,

1.5V

5282 drw 04

6

5

4

3

Figure 1. AC Test Load

1.5V

Figure 1

5282 tbl 23

∆tCD

(Typical, ns)

2

1

20 30 50

80 100

Capacitance (pF)

200

,

5282 drw 05

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

15

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)

7.5ns⁽⁵⁾

8ns

8.5ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

____

CYC

t

Clock Cycle Time

10

2.5

10.5

2.7

11

3.0

ns

(1)

Clock High Pulse Width

Clock Low Pulse Width

CH

t

____

(1)

2.7

CL

t

Output Parameters

____

CD

t

Clock High to Valid Data

7.5

8

8.5

ns

____

CDC

t

Clock High to Data Change

Clock High to Output Active

Clock High to Data High-Z

Output Enable Access Time

2

____

(2, 3,4)

3

CLZ

t

____

(2, 3,4)

5

ns

CHZ

t

____

OE

t

5

____

(2,3)

Output Enable Low to Data Active

Output Enable High to Data High-Z

0

OLZ

t

____

5

OHZ

t

Set Up Times

____

SE

t

Clock Enable Setup Time

2.0

ns

SA

t

Address Setup Time

SD

t

Data In Setup Time

SW

t

Read/Write (R/W) Setup Time

Advance/Load (ADV/LD) Setup Time

Chip Enable/Select Setup Time

Byte Write Enable (BWx) Setup Time

SADV

t

SC

t

SB

t

Hold Times

____

HE

t

Clock Enable Hold Time

0.5

ns

HA

t

Address Hold Time

HD

t

Data In Hold Time

HW

t

Read/Write (R/W) Hold Time

Advance/Load (ADV/LD) Hold Time

Chip Enable/Select Hold Time

Byte Write Enable (BWx) Hold Time

HADV

t

HC

t

HB

t

ns

5282 tbl 24

NOTES:

1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.

2. Transition is measured ±200mV from steady-state.

3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.

4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and

voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions

(0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V).

5. Commercial temperature range only.

6.42

16

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle ^(1,2,3,4)

.

,

6.42

17

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycles ^(1,2,3,4,5)

.

,

6.42

18

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Read and Write Cycles ^(1,2,3)

.

,

6.42

19

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CEN Operation ^(1,2,3,4)

.

,

6.42

20

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation ^(1,2,3,4)

.

,

6.42

21

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

t

JCYC

tJR

tJF

t

JCL

t

JCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

t

JDC

t

JS

t

JH

Device Outputs⁽²⁾/

TDO

t

JRSR

t

JCD

3)

(

x

TRST

M5282 drw 01

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

tJCYC

tJCH

tJCL

tJR

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

ScanRegisterSizes

____

Register Name

Instruction (IR)

Bit Size

____

ns

4

1

40

ns

Bypass (BYR)

5⁽¹⁾

ns

____

JTAG Identification (JIDR)

Boundary Scan (BSR)

32

tJF

5⁽¹⁾

ns

____

Note (1)

____

tJRST

tJRSR

tJCD

tJDC

tJS

50

ns

I5282 tbl 03

____

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

20

ns

____

0

ns

____

25

ns

tJH

JTAG Hold

ns

I5282 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42

22

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field

Revision Number (31:28)

Value

Description

0x2

0x209, 0x20B

0x33

Reserved for version number.

IDT Device ID (27:12)

Defines IDT part number 71V3557SA and 71V3559SA, respectively.

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

1

I5282 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I5282 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

23

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline

6.42

24

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

25

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.42

26

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation ⁽¹⁾

OE

tOE

tOHZ

tOLZ

DATA Out

Q

,

5282 drw 11

NOTE:

1. A read operation is assumed to be in progress.

OrderingInformation

IDT

XXXX

XX

X

XX

Device

Type

Power Speed

Package Process/

Temperature

Range

Blank Commercial (0°C to +70°C)

I

Industrial (-40°C to +85°C)

PF**

BG

BQ

100-Pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

75*

80

85

,

Access time (tCD) in tenths of nanoseconds

Standard Power

Standard Power with JTAG Interface

S

SA

IDT71V3557

IDT71V3559

128Kx36 Flow-Through ZBT SRAM with 3.3V I/O

256Kx18 Flow-Through ZBT SRAM with 3.3V I/O

5282 drw 12

*Commercial temperature range only.

** JTAG (SA version) is not available with 100-pin TQFP package

6.42

27

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History

6/30/99

8/23/99

Updated to new format

Added Pin 64 to Note 1 and changed Pins 38, 42, and 43 to DNU

Changed U2–U6 to DNU

Pg. 5, 6

Pg. 7

Pg. 15

Improved tCH, tCL; revised tCLZ

Pg. 21

Added BGA package diagrams

Pg. 23

AddedDatasheetDocumentHistory

12/31/99

05/02/00

Pg. 5, 14, 15, 22

Pg. 5,6

AddedIndustrialTemperaturerangeofferings

InsertclarificationnotetoRecommendedOperatingTemperatureandAbsoluteMaxratings

tables

Pg. 5,6,7

Pg. 6

ClarifynoteonTQFPandBGApinconfigurations;correctedtypoinpinout

Add BGAcapacitancetable

Pg. 21

AddTQFPPackageDiagramOutline

05/26/00

07/26/00

Add new package offering 13 x 15mm 165 fBGA

Correct119BGAPackageDiagramOutline

Add ZZ sleep mode reference note to TQFP, BG119 and BQ165

UpdateBQ165pinout

Pg. 23

Pg. 5-8

Pg. 8

Pg. 23

UpdateBG119pinoutpackagediagramdimensions

Removepreliminarystatus

10/25/00

05/20/02

Pg. 8

Pg. 1-8,15,22,23,27

Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST

AddedJTAG"SA"versionfunctionalityandupdatedZZpindescriptions andnotes.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726, x4033

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

6.42

28


型号：	IDT71V3557S85PF9
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	ZBT SRAM, 128KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100 静态存储器内存集成电路
文件：	总28页 (文件大小：511K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V3557S85PF9 [IDT]

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