IDT71V35761SA183B [IDT]
Cache SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119;型号: | IDT71V35761SA183B |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Cache SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119 静态存储器 内存集成电路 |
文件: | 总22页 (文件大小:622K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
128K x 36, 256K x 18
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
3.3VSynchronousSRAMs
3.3VI/O,PipelinedOutputs
BurstCounter,SingleCycleDeselect
Features
Description
◆
128K x 36, 256K x 18 memory configurations
The IDT71V35761/781 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof
thewritecycle.
◆
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
CommercialandIndustrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
◆
◆
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
◆
◆
◆
◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter
compliant)
andthe LBO inputpin.
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
grid array
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and 165 fine pitch ball grid array.
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
NOTE:
5301 tbl 01
1. BW3 and BW4 are not applicable for the IDT71V35781.
JUNE 2003
1
©2003IntegratedDeviceTechnology,Inc.
DSC-5301/03
11
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination ofthe rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
ADSC
ADSP
ADV
address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
1
-BW . If BWE is LOW at the rising edge of CLK
4
BWE
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
BW
1
-BW
4
write causes all outputs to be disabled.
Chip Enable
Synchronous chip enable. CE is used with CS
ADSP.
0
and CS to enable the IDT71V35761/781. CE also gates
1
CE
CLK
Clock
I
I
I
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
0
is used with CE and CS
1
to enable the chip.
1
is used with CE and CS0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
OE
TMS
TDI
Test ModeSelect
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test DataOutput
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
HIGH
TRST
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781
to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal
pull down.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
V
V
NC
No Connect
NC pins are not electrically connected to the device.
5301tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
17/18
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2–A17
A0 -
A16/17
ADDRESS
REGISTER
36/18
36/18
17/18
GW
Byte 1
Write Register
BWE
Byte 1
Write Driver
BW
1
2
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW
Byte 3
Write Register
Byte 3
Write Driver
BW
3
4
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW
OUTPUT
REGISTER
CE
CS
CS
Q
D
0
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
,
36/18
I/O0
— I/O31
I/OP1 — I/OP4
5301 drw 01
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(Optional)
6.42
3
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
VDDQ
Commercial &
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
VDD
Symbol
Rating
Industrial
Unit
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
5301 tbl 04
NOTES:
1. TA is the "instant on" case temperature.
VTERM
Terminal Voltage with
Respect to GND
VTERM
Terminal Voltage with
Respect to GND
V
RecommendedDCOperating
Conditions
Commercial
Operating Temperature
oC
oC
oC
oC
W
Symbol
Parameter
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
V
T (7)
A
VDD
Core Supply Voltage
3.465
3.465
0
Industrial
Operating Temperature
-40 to +85
VDDQ I/O Supply Voltage
V
V
SS
IH
IH
IL
Supply Voltage
0
2.0
0
V
Temperature
Under Bias
-55 to +125
TBIAS
____
V
InputHigh Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
V
DD +0.3
V
Storage
Temperature
-55 to +125
TSTG
DDQ +0.3(1)
0.8
V
____
____
V
2.0
V
V
-0.3(2)
V
PT
Power Dissipation
DC Output Current
2.0
50
5301 tbl 06
NOTES:
IOUT
mA
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
5301 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
119BGACapacitance
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
7
7
pF
CI/O
V
pF
CI/O
V
pF
5301 tbl 07
5301 tbl 07a
165fBGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5301 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
70
VDDQ
VDDQ
69
68
67
66
65
64
I/O22
I/O23
DD / NC(1)
I/O9
I/O8
V
VSS
VDD
NC
NC
V
DD
ZZ(2)
V
SS
I/O24
I/O25
63
62
I/O7
I/O6
61
60
59
58
57
56
55
54
53
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
,
52
51
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5301drw 02
100TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
A
NC
NC
10
2
3
4
V
DDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
NC
NC
I/O8
NC
I/OP1
I/O
7
8
7
9
I/O9
72
71
I/O
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
70
69
68
67
66
65
64
V
DDQ
VDDQ
I/O10
I/O11
DD / NC(1)
I/O
I/O
5
4
V
VSS
VDD
NC
NC
V
DD
ZZ(2)
V
SS
I/O12
I/O13
63
62
61
60
59
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
58
57
56
55
0
VSS
VSS
,
54
53
V
DDQ
VDDQ
NC
NC
NC
NC
NC
NC
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5301 drw 03
100TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
3
2
9
NC
NC
CS
NC
NC
1
CS
0
7
A
DD
V
12
15
A
A
16
P3
I/O
SS
SS
SS
SS
SS
SS
P2
15
I/O
I/O
I/O
V
V
V
NC
CE
V
V
V
I/O
I/O
I/O
I/O
17
18
I/O
13
12
11
9
14
I/O
DDQ
19
I/O
DDQ
V
V
V
V
OE
20
I/O
22
I/O
21
I/O
10
I/O
G
H
J
2
3
BW
ADV
GW
BW
23
I/O
SS
V
SS
V
8
I/O
I/O
DDQ
DD
DD
DD
V
DDQ
V
V
NC
V
NC
24
25
26
I/O
SS
SS
6
I/O
7
I/O
K
L
I/O
V
CLK
NC
V
27
I/O
4
I/O
5
I/O
I/O
4
BW
1
BW
DDQ
28
I/O
SS
V
SS
V
3
I/O
DDQ
M
N
P
R
T
V
BWE
29
31
30
I/O
SS
1
A
SS
2
I/O
1
I/O
I/O
V
V
V
V
P4
I/O
SS
0
A
SS
0
I/O
P1
I/O
I/O
(1)
DD / NC
NC
5
DD
13
A
V
NC
NC
A
NC
V
A
LBO
(3)
,
10
11
(2)
14
A
A
NC
ZZ
(2)
(2)
(2)
(2,4)
DDQ
NC/TDO
DDQ
V
V
NC/TMS
NC/TDI
NC/TCK
NC/TRST
U
5301 drw 04
Top View
Pin Configuration – 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
3
A
9
NC
NC
CS
NC
NC
NC
1
CS
0
7
2
A
DD
13
17
A
A
V
A
8
I/O
SS
SS
SS
SS
SS
7
I/O
NC
V
V
V
NC
V
V
V
V
V
9
SS
SS
6
I/O
NC
I/O
NC
NC
CE
OE
DDQ
5
I/O
DDQ
V
V
10
I/O
4
I/O
NC
NC
G
H
J
BW
2
ADV
GW
11
I/O
SS
SS
3
I/O
NC
V
NC
DDQ
DD
DD
DD
DDQ
V
V
V
NC
V
NC
V
12
SS
SS
2
NC
I/O
NC
V
CLK
NC
V
NC
I/O
K
L
13
I/O
SS
1
I/O
V
V
V
V
NC
1
BW
DDQ
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
V
NC
M
N
P
R
T
BWE
15
I/O
1
0
0
NC
A
A
I/O
NC
NC
P2
P1
NC
I/O
I/O
NC
(1)
DD / NC
5
DD
12
11
NC
NC
DDQ
A
V
A
A
V
LBO
,
(3)
10
15
14
A
A
A
NC
ZZ
(2)
(2)
(2)
(2)
(2,4)
NC/TRST
NC/TDO
DDQ
V
NC/TMS
NC/TDI
NC/TCK
V
U
5301 drw 05
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
7
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
A
7
A
8
NC
CE
1
BW
3
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(4)
NC
A6
CS
0
CLK
A9
NC
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
I/O22
NC
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
I/O23
VDDQ
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
I/O
NC
9
I/O8
(1)
(3)
V
DD
NC
V
V
V
V
V
NC
ZZ
I/O
I/O
I/O
I/O
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
1
0
(4)
V
V
NC/TRST(2, 5)
NC
NC
V
V
I/OP1
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A14
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A12
A15
A16
LBO
5301 tbl 17
Pin Configuration – 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(4)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A
7
NC
A
8
A
CE
1
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
10
(4)
A6
CS
0
NC
CLK
A9
NC
BW1
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
I/O
I/O10
I/O11
NC
9
V
V
V
V
V
V
V
6
V
V
V
V
V
V
V
5
G
H
J
VDDQ
V
V
V
V
V
V
4
(1)
(3)
V
DD
NC
V
V
V
V
V
NC
ZZ
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
I/O
NC
3
NC
NC
NC
NC
NC
K
L
M
N
P
NC
V
V
V
V
V
V
V
2
NC
V
V
V
V
V
V
V
1
NC
V
V
V
V
V
V
V
0
NC/TRST(2, 5)
(4)
NC
V
V
NC
NC
V
V
(4)
(2)
(2)
(4)
NC
A5
A2
NC/TDI
A1
NC/TDO
A
A
A15
NC
(4)
(2)
R
NC
A4
A3
NC/TMS(2)
A0
NC/TCK
A
A
A16
A17
LBO
5301 tbl 17a
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
6.42
8
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
ZZ, LBO and JTAG Input Leakage Current(1)
Output Leakage Current
___
___
___
|ILZZ
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +8mA, VDD = Min.
OH = -8mA, VDD = Min.
30
5
µA
µA
V
|ILO|
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.4
V
5301 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
200MHz
Com'l
360
183MHz
Com'l
166 MHz
Com'l
Symbol
Parameter
Test Conditions
Ind
Ind
Unit
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
340
350
320
330
mA
IDD
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
130
30
30
35
130
35
30
35
120
35
mA
mA
V
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
120
30
110
30
(2,3)
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
ZZ > VHD,
VDD = Max.
Full Sleep Mode Supply
Current
mA
I
ZZ
5301 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
V
DDQ/2
(VDDQ = 3.3V)
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
5301 drw 06
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
Figure 1. AC Test Load
6
5
4
3
1.5V
See Figure 1
5301 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5301 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
Operation
Address
Used
CS
0
CLK
I/O
CE
CS
1
ADSP ADSC ADV
GW
BWE
BWx
OE
(2)
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
5301tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
10
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousWrite Function Truth Table(1, 2)
Operation
Read
GW
H
H
L
BWE
H
L
BW
X
H
X
L
1
BW
X
H
X
L
2
BW
X
H
X
L
3
BW4
X
Read
H
X
L
Write all Bytes
Write all Bytes
Write Byte 1(3)
Write Byte 2(3)
Write Byte 3(3)
Write Byte 4(3)
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
5301 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V35781.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
Read
ZZ
I/O Status
Power
OE
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Read
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5301 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5301 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5301 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
200MHz(5)
183MHz
166MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CY C
Clock Cycle Time
5
2
2
—
—
—
5.5
2.2
2.2
—
—
—
6
—
—
—
ns
ns
ns
(1)
CH
Clock High Pulse Width
Clock Low Pulse Width
2.4
2.4
t
(1)
CL
t
Output Parameters
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
—
1.0
0
3.1
—
—
—
1.0
0
3.3
—
—
—
1.0
0
3.5
—
—
ns
ns
ns
tCDC
(2)
CLZ
t
(2)
Clock High to Data High-Z
1.5
—
0
3.1
3.1
—
1.5
—
0
3.3
3.3
—
1.5
—
0
3.5
3.5
—
ns
ns
ns
ns
t
CHZ
tOE
Output Enable Access Time
(2)
(2)
Output Enable Low to Output Active
Output Enable High to Output High-Z
t
OLZ
—
3.1
—
3.3
—
3.5
t
OHZ
Set Up Times
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.2
1.2
1.2
1.2
1.2
1.2
—
—
—
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
—
—
—
—
—
—
1.5
1.5
1.5
1.5
1.5
1.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.4
0.4
0.4
0.4
0.4
0.4
—
—
—
—
—
—
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep Mode and Configuration Parameters
t
ZZPW
ZZ Pulse Width
100
100
20
—
—
—
100
100
22
—
—
—
100
100
24
—
—
—
ns
ns
(3)
ZZR
ZZ Recovery Time
Configuration Set-up Time
t
(4)
CFG
ns
t
5301tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.42
12
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
,
6.42
13
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
6.42
14
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)
,
6.42
15
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)
,
6.42
16
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
17
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
0
CS
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5301 drw 14
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBOis Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Forreadcycles, ADSP andADSCfunctionidenticallyandare therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5301 drw 15
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5301 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
(1)
____
t
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1)
____
t
5
ns
Note (1)
____
____
t
50
ns
I5301 tbl 03
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5301 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
19
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number.
IDT Device ID (27:12)
0x23C, 0x23E
Defines IDT part number 71V35761SA and 71V35781SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
0x33
1
ID Register Indicator Bit (Bit 0)
I5301 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5301 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
20
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
X
IDT
XXX
S
X
XX
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
PF**
BG
BQ
200*
183
166
Frequency in Megahertz
,
S
SA
Standard Power
Standard Power with JTAG interface
Blank
Y
First Generation or current stepping
Second Generation die step
128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O
256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O
71V35761
71V35781
*Commercial temperature range only
** JTAG (SA version) is not available with 100 pin TQFP package.
5301 drw 13
PackageInformation
100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
21
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/04/00
Creatednewdatasheetfrom71v3576and71v3578datasheet.
Addedindustrialtemperaturerangeofferingfrom166MHzand183MHz
Added100pinTQFPpackage DiagramOutline
Pg. 1, 4, 8, 11, 19
Pg. 18
Pg. 4
AddBGAcapacitancetable;Addindustrialtempertauretotable;InsertnotetoAbsoluteMax
RatingandRecommendedOperatingTemperaturetables
Addnewpackagediagramoutline,13x15mm165fBGA
CorrectBG119PackageDiagramOutline
06/01/00
07/15/00
Pg. 20
Pg. 7
AddnotereferencetoBG119pinout
Pg. 8
AddDNUreference note toBQ165pinout
Pg. 20
UpdateBG119PackageDiagramOutlineDimensions
RemovePreliminarystatus
10/25/00
Pg. 8
Pg.4
Add reference note to N5 on the BQ165 pinout, reserved for JTAG TRST
Updated165BGAtableinformationfromTBDto7
04/22/03
06/30/03
Pg. 1,2,3,5-9
Pg. 5-8
UpdateddatasheetwithJTAGinformation
Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiringNCorconnectiontoVss.
Pg. 19,20
Pg. 21-23
Pg. 24
AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions
Removedoldpackageinformationfromthedatasheet
UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation
regardingpackages availableIDTwebsite.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
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