IDT71V3576S150PFG_技术文档

128K x 36, 256K x 18

IDT71V3576S

IDT71V3578S

IDT71V3576SA

IDT71V3578SA

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V3576/78 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V3576/78SRAMs containwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

CommercialandIndustrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

◆

Theburstmodefeatureoffersthehighestlevelofperformancetothe

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array (fBGA)

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CE

CS

0

, CS

1

Chip Selects

Output Enable

OE

GW

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

1

2

, BW

3

, BW ⁽¹⁾

4

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

DC

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

TRST

ZZ

I/O

0

-I/O31, I/OP1-I/OP4

DD, VDDQ

SS

Data Input / Output

Core Power, I/O Power

Ground

V

Supply

V

N/A

5279 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

JANUARY 2004

1

DSC-5279/04

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

Synchronous Address inputs. The address register is triggered by a combination of the rising edge

of CLK and ADSC Low or ADSP Low and CE Low.

A0-A17

Address Inputs

I

N/A

Address Status

(Cache Controller)

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load

I

LOW

ADSC

ADSP

the address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the

address registers with new addresses. ADSP is gated by CE.

Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst

counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst

counter is not incremented; that is, there is no address advance.

Burst Address

Advance

I

LOW

ADV

Synchronous byte write enable gates the byte write inputs BW

1

-BW . If BWE is LOW at the rising

4

Byte Write Enable

edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the

byte write inputs are blocked and only GW can initiate a write cycle.

BWE

Individual Byte

Write Enables

Synchronous byte write enables. BW

1

controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active

I

LOW

BW

1

-BW

4

byte write causes all outputs to be disabled.

Synchronous chip enable. CE is used with CS

ADSP.

0

and CS to enable the IDT71V3576/78. CE also gates

1

Chip Enable

CE

CLK

Clock

I

N/A

HIGH

LOW

This is the clock input. All timing references for the device are made with respect to this input.

CS0

Chip Select 0

Chip Select 1

Synchronous active HIGH chip select. CS

Synchronous active LOW chip select. CS

0

is used with CE and CS

1

to enable the chip.

1

is used with CE and CS0 to enable the chip.

CS1

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising

edge of CLK. GW supersedes individual byte write enables.

I

LOW

N/A

GW

I/O -I/O31

0

Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered

and triggered by the rising edge of CLK.

Data Input/Output

Linear Burst Order

I/O

I/OP1-I/OP4

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is

selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must

not change state while the device is operating.

I

LOW

LBO

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if

the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.

Output Enable

Test ModeSelect

Test Data Input

Test Clock

I

LOW

N/A

OE

TMS

TDI

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal

pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has

an internal pullup.

I

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of

TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

I

Serial output of registers placed between TDI and TDO. This output is active depending on the state

of the TAP controller.

Test DataOutput

O

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG

reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not

used TRST can be left floating. This pin has an internal pullup. Only available in BGA package.

JTAG Reset

(Optional)

I

LOW

HIGH

TRST

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep

Mode.This pin has an internal pull down.

ZZ

Sleep Mode

V

DD

DDQ

SS

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

Ground.

V

NC

No Connect

NC pins are not electrically connected to the device.

5279 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

2

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

LBO

ADV

CEN

INTERNAL

ADDRESS

Burst

Sequence

128K x 36/

256K x 18-

BIT

MEMORY

CLK

2

Burst

Logic

17/18

Binary

Counter

ADSC

A0*

Q0

CLR

A1*

Q1

ADSP

ARRAY

2

CLK EN

A0,A1

A2–A17

A0 -

A16/17

ADDRESS

REGISTER

36/18

17/18

GW

Byte 1

Write Register

BWE

Byte 1

Write Driver

BW

1

9

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

BW

3

9

Byte 4

Write Register

Byte 4

Write Driver

BW4

OUTPUT

REGISTER

CE

CS

Q

D

0

Enable

DATA INPUT

REGISTER

1

Register

CLK EN

ZZ

Powerdown

D

Q

Enable

Delay

Register

OE

OUTPUT

BUFFER

OE

,

36/18

I/O

0 — I/O31

I/OP1 — I/OP4

5279 drw 01

TMS

TDI

TCK

JTAG

(SA Version)

TDO

TRST

(Optional)

6.42

3

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Commercial &

Symbol

Rating

Industrial

Unit

Grade

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

V

SS

VDD

VDDQ

(2)

V

TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

Commercial

Industrial

0V

3.3V±5%

(3,6)

TERM

V

Terminal Voltage with

Respect to GND

-0.5 to VDD

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

-0 to +70

V

5279 tbl 04

NOTES:

1. TA is the "instant on" case temperature.

(4,6)

TERM

V

Terminal Voltage with

Respect to GND

(5,6)

TERM

RecommendedDCOperating

Conditions

V

Terminal Voltage with

Respect to GND

V

Commercial

^oC

W

Symbol

Parameter

Min.

3.135

0

Typ.

Max.

Unit

Operating Temperature

T ⁽⁷⁾

A

VDD

Core Supply Voltage

3.3

3.465

0

V

Industrial

-40 to +85

VDDQ I/O Supply Voltage

3.3

Operating Temperature

V

SS

IH

IL

Supply Voltage

0

Temperature

Under Bias

-55 to +125

TBIAS

____

V

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

VDD +0.3

V

2.0

V

DDQ +0.3⁽¹⁾

____

Storage

-55 to +125

TSTG

Temperature

V

-0.3⁽²⁾

0.8

V

5279 tbl 06

P

T

Power Dissipation

DC Output Current

2.0

50

NOTES:

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

IOUT

mA

5279 tbl 03

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

100PinTQFPCapacitance

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

CIN

V

5

7

pF

CIN

V

7

pF

CI/O

VOUT = 3dV

pF

CI/O

V

pF

5279 tbl 07

5279 tbl 07a

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

IN = 3dV

Max. Unit

CIN

V

7

pF

CI/O

VOUT = 3dV

pF

5279 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

4

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

I/OP3

I/O16

I/O17

I/OP2

I/O15

I/O14

2

79

78

77

3

4

V

DDQ

VDDQ

5

V

SS

76

75

74

73

V

SS

6

I/O18

I/O19

I/O20

I/O21

I/O13

I/O12

I/O11

I/O10

7

8

9

72

71

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

VSS

70

69

68

67

66

V

DDQ

VDDQ

I/O22

I/O23

I/O

9

8

V

DD / NC⁽¹⁾

VSS

VDD

NC

65

64

NC

V

DD

ZZ⁽²⁾

V

SS

I/O24

I/O25

63

62

I/O7

I/O6

61

60

59

58

57

56

55

V

DDQ

V

DDQ

SS

V

SS

I/O26

I/O27

I/O28

I/O29

I/O

5

4

3

2

V

SS

VSS

54

53

52

51

V

DDQ

VDDQ

I/O30

I/O31

I/OP4

I/O

I/OP1

1

,

0

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5279 drw 02

TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 256K x 18

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

NC

A

NC

10

2

79

78

77

3

4

V

DDQ

V

DDQ

5

V

SS

76

75

74

73

V

SS

6

NC

I/O8

NC

I/OP1

I/O

7

8

7

9

I/O9

72

71

70

I/O

6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

V

SS

V

DDQ

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

I/O10

I/O11

DD / NC⁽¹⁾

I/O

5

4

V

SS

VDD

NC

V

DD

ZZ⁽²⁾

V

SS

I/O12

I/O13

I/O

3

2

V

DDQ

V

DDQ

SS

V

SS

I/O14

I/O15

I/OP2

NC

I/O

NC

1

0

V

SS

V

SS

,

54

53

V

DDQ

NC

DDQ

NC

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5279 drw 03

TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

A

9

NC

1

CS

0

7

2

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

15

V

NC

V

I/O

17

I/O

18

I/O

SS

13

12

11

9

14

CE

OE

DDQ

V

19

I/O

DDQ

V

20

I/O

21

I/O

10

I/O

G

H

J

2

3

BW

ADV

GW

BW

22

I/O

23

I/O

SS

V

8

I/O

V

I/O

DDQ

V

DD

DDQ

V

NC

V

NC

V

24

26

SS

4

SS

6

7

I/O

V

CLK

NC

V

I/O

K

L

25

I/O

27

I/O

4

I/O

5

I/O

1

BW

DDQ

28

SS

3

DDQ

V

I/O

V

I/O

M

N

P

R

T

BWE

29

I/O

30

I/O

1

A

2

I/O

1

I/O

31

P4

0

A

P1

I/O

NC

I/O

0

I/O

(1)

DD / NC

5

DD

13

A

V

NC

V

LBO

(4)

,

10

11

14

A

NC

A

NC

ZZ

(2)

(2,3)

(2)

DDQ

V

DDQ

V

NC/TMS

NC/TCK

NC/TDO

NC/TRST

U

NC/TDI

5279 drw 04

Top View

Pin Configuration – 256K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

A

9

NC

CS

NC

1

CS

0

7

2

A

DD

13

17

A

V

A

8

SS

7

I/O

NC

V

NC

V

9

I/O

SS

6

I/O

NC

CE

OE

DDQ

V

5

I/O

DDQ

V

NC

10

I/O

4

I/O

G

H

J

NC

BW

2

ADV

GW

11

I/O

SS

3

I/O

NC

V

NC

DDQ

V

DD

DDQ

V

NC

V

NC

V

12

SS

2

NC

I/O

NC

V

CLK

NC

V

NC

I/O

K

L

13

I/O

SS

1

I/O

V

NC

1

BW

DDQ

14

SS

DDQ

V

I/O

V

NC

M

N

P

R

T

BWE

15

1

A

0

I/O

NC

P2

0

A

I/O

P1

I/O

NC

(1)

VDD / NC

5

DD

12

A

NC

DDQ

A

V

NC

LBO

,

(4)

10

15

14

11

A

NC

A

ZZ

(2)

(2,3)

(2)

DDQ

V

NC/TMS

NC/TCK

NC/TDO

NC/TRST

U

V

NC/TDI

5279 drw 05

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

3. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

4. T7 can be left unconnected and the device will always remain in active mode.

6.42

7

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration – 128K x 36, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

(2)

A

B

C

D

E

F

NC

A

7

A

8

NC

CE

1

BW

3

BW

2

CS

1

BWE

GW

ADSC

OE

ADV

ADSP

(2)

NC

A6

CS

0

CLK

A9

NC

BW4

BW

1

I/OP3

I/O17

I/O19

I/O21

NC

V

DDQ

V

SS

DD

SS

V

SS

V

SS

V

SS

V

SS

DD

SS

10

11

V

DDQ

NC

I/OP2

I/O14

I/O12

I/O10

I/O16

I/O18

I/O20

I/O22

NC

V

I/O15

I/O13

I/O11

V

G

H

J

I/O23

VDDQ

V

I/O

NC

I/O

9

I/O8

(1)

(5)

V

DD

NC

V

NC

ZZ

I/O

I/O25

I/O27

I/O29

I/O31

I/OP4

NC

I/O24

I/O26

I/O28

I/O30

NC

V

DDQ

V

DDQ

13

7

6

K

L

M

N

P

V

5

4

V

3

2

V

I/O

1

0

NC/TRST^{(3, 4)}

(2)

V

NC

V

NC

I/OP1

(2)

(3)

(2)

NC

A5

A2

NC/TDI

A1

NC/TDO

A

A14

NC

(2)

(3)

R

NC

A4

A3

NC/TMS⁽³⁾

A0

NC/TCK

A

A12

A15

A16

LBO

5279 tbl 17

Pin Configuration – 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

(2)

A

B

C

D

E

F

NC

A

7

NC

A

8

A10

CE

1

BW

2

CS

1

BWE

GW

ADSC

OE

ADV

ADSP

(2)

A6

CS

0

NC

CLK

A9

NC

BW1

NC

V

DDQ

V

SS

DD

SS

V

SS

V

SS

V

SS

V

SS

DD

SS

11

12

V

DDQ

NC

I/OP1

I/O

8

V

I/O

7

I/O

9

V

6

I/O10

I/O11

NC

V

5

G

H

J

V

4

(1)

(5)

V

DD

NC

V

NC

ZZ

I/O12

I/O13

I/O14

I/O15

I/OP2

NC

V

DDQ

V

DDQ

14

13

I/O

3

NC

K

L

M

N

P

NC

V

2

NC

V

1

NC

V

I/O

0

(2)

NC

V

NC/TRST^{(3, 4)}

NC

V

NC

(2)

(3)

(2)

NC

A5

A2

NC/TDI

A1

NC/TDO

A

A15

NC

(2)

(3)

R

NC

A4

A3

NC/TMS⁽³⁾

A0

NC/TCK

A

A16

A17

LBO

5279 tbl 17a

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.

4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.

5. H11 can be left unconnected and the device will always remain in active mode.

6.42

8

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

5

µA

(1)

___

ZZ, LBO and JTAG Input Leakage Current

Output Leakage Current

Output Low Voltage

|I^LZZ

|

V

DD = Max., VIN = 0V to VDD

OUT = 0V to VDDQ, Device Deselected

OL = +8mA, VDD = Min.

OH = -8mA, VDD = Min.

30

5

µA

V

|I^LO|

V

VOL

I

0.4

___

VOH

Output High Voltage

I

2.4

V

5279 tbl 08

NOTE:

1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.

DC Electrical Characteristics Over the Operating

TemperatureandSupplyVoltageRange⁽¹⁾

150MHz

133MHz

Com'l

Symbol

Parameter

Test Conditions

Com'l

Ind

Unit

Operating Power Supply

Current

Device Selected, Outputs Open, VDD = Max.,

295

30

305

250

260

mA

I

DD

(2)

VDDQ = Max., VIN > VIH or < VIL, f = fMAX

ISB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

DDQ = Max., VIN > VHD or < VLD, f = 0^(2,3)

35

115

35

30

35

110

35

mA

V

ISB2

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

105

30

100

30

(2,3)

V

DDQ = Max., VIN > VHD or < VLD, f = fMAX

ZZ > VHD,

VDD = Max.

Full Sleep Mode Supply

Current

mA

IZZ

5279 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

AC Test Conditions

AC Test Load

V

DDQ/2

(VDDQ = 3.3V)

50Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

,

5279 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

6

5

4

3

1.5V

See Figure 1

5279 tbl 10

∆tCD

(Typical, ns)

2

1

20 30 50

80 100

Capacitance (pF)

200

5279 drw 07

,

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

9

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousTruthTable^(1,3)

CE

CS1

ADSP ADSC ADV

GW

BWE BWx

OE

(2)

Operation

Address

Used

CS0

CLK

I/O

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

H

L

X

L

X

H

X

H

X

L

X

L

X

L

X

L

X

H

L

X

H

L

X

H

L

X

L

-

HI-Z

None

L

None

L

X

L

X

L

None

L

External

H

X

L

DOUT

Read Cycle, Begin Burst

L

H

L

HI-Z

Read Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

DOUT

Read Cycle, Begin Burst

L

DOUT

Read Cycle, Begin Burst

L

H

X

L

HI-Z

Write Cycle, Begin Burst

L

D

IN

OUT

Write Cycle, Begin Burst

L

X

H

X

H

X

L

X

H

X

H

L

D

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

L

D

H

L

HI-Z

DOUT

H

L

HI-Z

DOUT

H

L

HI-Z

DOUT

H

X

L

HI-Z

D

IN

OUT

X

L

X

L

D

H

L

D

X

H

X

H

X

L

X

H

X

H

L

D

Current

H

L

D

H

L

HI-Z

DOUT

H

L

HI-Z

DOUT

H

L

HI-Z

DOUT

H

X

HI-Z

D

IN

5279 tbl 11

X

L

X

L

D

H

L

D

X

D

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

10

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousWrite Function Truth Table^{(1, 2)}

GW

H

L

BWE

H

L

BW

X

H

X

L

1

BW

X

H

X

L

2

BW

X

H

X

L

3

BW4

Operation

Read

X

Read

H

X

L

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

X

L

H

L

H

L

H

L

H

L

H

L

H

L

H

5279 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW³andBW4 are not applicable for the IDT71V3578.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

OE

ZZ

I/O Status

Power

Read

L

H

X

L

H

Data Out

High-Z

Active

Write

High-Z – Data In

High-Z

Active

Deselected

Sleep Mode

Standby

Sleep

High-Z

5279 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

5279 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

0

A0

0

A1

0

A0

1

A1

1

A0

0

A1

1

A0

First Address

1

Second Address

Third Address

0

1

0

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5279 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.42

11

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

150MHz

133MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

CY C

Clock Cycle Time

6.7

2.6

7.5

3

ns

(1)

CH

Clock High Pulse Width

Clock Low Pulse Width

t

(1)

CL

____

3

t

Output Parameters

____

t

CD

Clock High to Valid Data

3.8

4.2

ns

____

tCDC

Clock High to Data Change

1.5

0

1.5

0

____

(2)

CLZ

Clock High to Output Active

Clock High to Data High-Z

t

(2)

1.5

3.8

1.5

4.2

ns

tCHZ

____

tOE

Output Enable Access Time

Output Enable Low to Output Active

Output Enable High to Output High-Z

3.8

4.2

____

(2)

0

tOLZ

____

3.8

4.2

tOHZ

Set Up Times

____

t

SA

SS

SD

SW

SAV

SC

Address Setup Time

1.5

ns

t

Address Status Setup Time

Data In Setup Time

t

Write Setup Time

t

Address Advance Setup Time

Chip Enable/Select Setup Time

t

Hold Times

____

t

HA

HS

HD

HW

HAV

HC

Address Hold Time

0.5

ns

t

Address Status Hold Time

Data In Hold Time

t

Write Hold Time

t

Address Advance Hold Time

Chip Enable/Select Hold Time

t

Sleep Mode and Configuration Parameters

____

t

ZZPW

ZZ Pulse Width

100

27

100

30

ns

(3)

ZZR

ZZ Recovery Time

Configuration Set-up Time

t

____

(4)

CFG

ns

t

5279 tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

6.42

12

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Pipelined Read Cycle^(1,2)

,

6.42

13

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles^(1,2,3)

,

6.42

14

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 - GW Controlled^(1,2,3)

,

6.42

15

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled^(1,2,3)

,

6.42

16

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes^(1,2,3)

,

6.42

17

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW, BWE, BWx

CE, CS

1

0

CS

OE

(Av)

(Aw)

(Ax)

(Ay)

DATAOUT

,

5279 drw 14

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBOis Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Forreadcycles, ADSP andADSCfunctionidenticallyandare therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW

CE, CS

1

CS0

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATA^IN

,

5279 drw 15

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.42

18

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Interface Specification (SA Version only)

t

JCYC

t

JR

tJF

tJCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

tJDC

tJS

tJH

Device Outputs⁽²⁾/

TDO

t

JRSR

tJCD

3)

(

x

TRST

M5279 drw 01

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS and TRST.

2. Device outputs = All device outputs except TDO.

3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

ScanRegisterSizes

____

t

JCYC

JCH

JCL

JR

JF

JRST

JRSR

JCD

JDC

JS

JH

Register Name

Bit Size

____

t

ns

Instruction (IR)

4

1

t

40

ns

Bypass (BYR)

(1)

____

t

5

ns

JTAG Identification (JIDR)

Boundary Scan (BSR)

32

(1)

____

t

5

ns

Note (1)

____

t

50

ns

I5279 tbl 03

t

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

NOTE:

1. The Boundary Scan Descriptive Language (BSDL) file for this device is available

by contacting your local IDT sales representative.

____

t

20

ns

____

t

0

ns

____

t

25

ns

t

JTAG Hold

ns

I5279 tbl 01

NOTES:

1. Guaranteed by design.

2. AC Test Load (Fig. 1) on external output signals.

3. Refer to AC Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.

6.42

19

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

JTAG Identification Register Definitions (SA Version only)

Instruction Field

Value

Description

Revision Number (31:28)

0x2

0x238, 0x23A

0x33

Reserved for version number.

IDT Device ID (27:12)

Defines IDT part number 71V3576SA and 71V3578SA, respectively.

Allows unique identification of device vendor as IDT.

Indicates the presence of an ID register.

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

1

I5279 tbl 02

AvailableJTAGInstructions

Instruction

Description

OPCODE

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

EXTEST

0000

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the boundary scan cells via the TDI.

SAMPLE/PRELOAD

0001

Loads the JTAG ID register (JIDR) with the vendor ID code and places

the register between TDI and TDO.

DEVICE_ID

HIGHZ

0010

0011

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

RESERVED

0100

0101

0110

0111

Several combinations are reserved. Do not use codes other than those

identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,

VALIDATE and BYPASS instructions.

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

1000

RESERVED

1001

1010

1011

1100

Same as above.

Automatically loaded into the instruction register whenever the TAP

controller passes through the CAPTURE-IR state. The lower two bits '01'

are mandated by the IEEE std. 1149.1 specification.

VALIDATE

1101

RESERVED

BYPASS

Same as above.

1110

1111

The BYPASS instruction is used to truncate the boundary scan register

as a single bit in length.

I5279 tbl 04

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

6.42

20

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

OrderingInformation

X

IDT

XXX

X

S

X

XX

X

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

G

Restricted hazardous substance device

PF*

BG

BQ

100-pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

150

133

Frequency in Megahertz

Standard Power

Standard Power with JTAG Interface

S

SA

First generation or current stepping

Second generation die step

Blank

Y

,

128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O

256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O

71V3576

71V3578

5279 drw 13

* Note: JTAG (SA version) is not available with 100-pin TQFP package.

PackageInformation

100-Pin Thin Quad Plastic Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

Information available on the IDT website

6.42

21

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History

7/26/99

9/17/99

Updatedtonewformat

Revised ISB1 and IZZ for speeds 100–200MHz

Pg. 8

Pg. 11

Revised tCDC (min.) at 166MHz

Pg. 18

Added119BGApackagediagram

Pg. 20

AddedDatasheetDocumentHistory

12/31/99

04/04/00

Pg. 1, 8, 11, 19

Removed 166, 183, and 200MHz speed grade offerings

(see IDT71V35761 and IDT71V35781)

AddedIndustrialTemperaturerangeofferings

Pg. 1, 4, 8, 11, 19

Pg.18

Added100TQFPPackageDiagramOutline

Pg. 4

AddcapacitanccetablefortheBGApackage;AddIndustrialtemperaturetotable;

InsertnotetoAbsoluteMaxRatingandRecommendedOperatingTemperaturetables

AddnotetoBGApinconfigurations;correctedtypoinpinout

Addnewpackageoffering,13x15mmfBGA

Pg. 7

06/01/00

07/15/00

Pg. 20

Pg. 7

CorrectBG119PackageDiagramOutline

AddnotereferencetoBG119pinout

Pg. 8

AddDNUreference note toBQ165pinout

Pg. 20

UpdateBG119PackageDiagramOutlineDimensions

RemovePreliminaryStatus

10/25/00

Pg. 8

Pg. 4

Pg. 1,2,3,5-9

Pg. 5-8

Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST

Updated165BGAtableinformationfromTBDto7

UpdateddatasheetwithJTAGinformation

Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))

requiringNCorconnectiontoVss.

04/22/03

06/30/03

Pg. 19,20

Pg. 21-23

Pg. 24

AddedtwopagesofJTAGSpecification,ACElectrical,DefinitionsandInstructions

Removedoldpackageinformationfromthedatasheet

UpdatedorderinginformationwithJTAGandYsteppinginformation. Addedinformation

regardingpackages availableIDTwebsite.

01/ /04

Pg.21

Added"Restrictedhazardoussubstancedevice"toorderinginformation.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

ipchelp@idt.com

800-345-7015

800-345-7015 or

408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

22


型号：	IDT71V3576S150PFG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100 时钟静态存储器内存集成电路
文件：	总22页 (文件大小：622K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V3576S150PFG [IDT]

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