IDT71V35781166PFI_技术文档

128K x 36, 256K x 18

IDT71V35761

IDT71V35781

3.3VSynchronousSRAMs

3.3VI/O,PipelinedOutputs

BurstCounter,SingleCycleDeselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V35761/781 are high-speed SRAMs organized as

128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

CommercialandIndustrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO input selects interleaved or linear burst mode

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array.

PinDescriptionSummary

0

17

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CE

0

1

CS , CS

Chip Selects

Output Enable

OE

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

GW

BWE

(1)

¹,

²,

³,

4

BW BW BW BW

CLK

ADV

ADSC

ADSP

LBO

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

DC

ZZ

Asynchronous

Synchronous

N/A

0

31

P1

P4

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

V , V

Supply

SS

V

N/A

5301 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V35781.

OCTOBER 2000

1

DSC-5301/01

11

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁷

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

Address Status

(Cache Controller)

I

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

ADSC

ADSP

ADV

used to load the address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs BW¹-BW⁴. If BWE is LOW at the

rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

BWE

Individual Byte

Write Enables

I

LOW

N/A

Synchronous byte write enables. BW¹controls I/O^0-7, I/O^P1, BW²controls I/O^8-15, I/O^P2, etc.

BW¹-BW⁴

CE

Any active byte write causes all outputs to be disabled.

Chip Enable

Synchronous chip enable. CE is used with CS⁰and CS¹to enable the IDT71V35761/781.

CE also gates ADSP.

CLK

Clock

This is the clock input. All timing references for the device are made with respect to this

input.

CS⁰

Chip Select 0

Chip Select 1

I

HIGH

LOW

Synchronous active HIGH chip select. CS⁰is used with CE and CS¹to enable the chip.

Synchronous active LOW chip select. CS¹is used with CE and CS⁰to enable the chip.

1

CS

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

GW

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

I/O

I

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

LBO

OE

Output Enable

I

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

V^DD

V^DDQ

V^SS

NC

Power Supply

Ground

N/A

I

N/A

3.3V core power supply.

3.3V I/O Supply.

N/A

Ground.

No Connect

Sleep Mode

N/A

NC pins are not electrically connected to the device.

ZZ

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V35761/781 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

5301tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.422

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

LBO

ADV

CEN

INTERNAL

ADDRESS

Burst

Sequence

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

CLK

2

Burst

Logic

17/18

Binary

Counter

ADSC

A0*

A1*

Q0

Q1

CLR

ADSP

2

CLK EN

A0,A1

A2–A17

A0 - A16/17

GW

ADDRESS

REGISTER

36/18

17/18

Byte 1

Write Register

BWE

Byte 1

Write Driver

1

BW

9

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

BW3

BW4

9

Byte 4

Write Register

Byte 4

Write Driver

OUTPUT

REGISTER

CE

Q

D

CS⁰

Enable

DATA INPUT

REGISTER

1

CS

Register

CLK EN

ZZ

Powerdown

D

Q

Enable

Delay

Register

OE

OUTPUT

BUFFER

OE

,

36/18

I/O0 — I/O31

I/OP1 — I/OP4

5301 drw 01

6.42

3

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Commercial &

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

V

Symbol

Rating

Industrial

Unit

SS

DD

DDQ

V

Grade

(2)

VTERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

Commercial

Industrial

0V

3.3V±5%

(3,6)

VTERM

Terminal Voltage with

Respect to GND

-0.5 to VDD

-0.5 to VDD +0.5

-0.5 to VDDQ +0.5

-0 to +70

V

5301 tbl 04

NOTES:

1. TA is the "instant on" case temperature.

(4,6)

VTERM

Terminal Voltage with

Respect to GND

(5,6)

VTERM

Terminal Voltage with

Respect to GND

V

RecommendedDCOperating

Conditions

Commercial

^oC

W

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min. Typ.

3.135 3.3

Max.

Unit

V

Operating Temperature

(7)

TA

DD

V

3.465

0

Industrial

-40 to +85

DDQ

V

Operating Temperature

SS

V

0

V

Temperature

Under Bias

-55 to +125

TBIAS

TSTG

____

IH

DD

V

Input High Voltage - Inputs

Input High Voltage -I/O

Input Low Voltage

2.0

V

+0.3

V

Storage

-55 to +125

(1)

____

IH

V

DDQ

2.0

V

+0.3

0.8

V

Temperature

-0.3⁽²⁾

V

IL

V

PT

Power Dissipation

DC Output Current

2.0

50

5301 tbl 06

NOTES:

IOUT

mA

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

5301 tbl 03

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

100 Pin TQFP Capacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

CIN

5

7

pF

7

pF

CI/O

pF

CI/O

pF

5301 tbl 07

5301 tbl 07a

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

CIN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

TBD

pF

CI/O

pF

5301 tbl 07b

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.442

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

I/OP3

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

2

79

78

77

3

4

5

76

75

74

73

6

7

8

9

72

71

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

70

69

68

67

66

VDDQ

I/O22

I/O23

VDD / NC⁽¹⁾

VDD

VDDQ

I/O9

I/O8

VSS

NC

65

64

NC

VSS

VDD

ZZ⁽³⁾

I/O7

I/O6

VDDQ

VSS

I/O5

I/O4

I/O3

I/O2

VSS

63

62

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

VDDQ

I/O30

I/O31

I/OP4

61

60

59

58

57

56

55

54

53

52

51

VDDQ

I/O1

I/O0

I/OP1

,

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5301 drw 02

100TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins 38 and 39 can be either NC or connected to VSS.

3. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 18

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

NC

VDDQ

VSS

NC

I/O8

I/O9

VSS

A10

NC

2

3

4

VDDQ

VSS

NC

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

NC

VDD

ZZ⁽³⁾

I/O3

I/O2

VDDQ

VSS

I/O1

I/O0

NC

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

I/O10

I/O11

VDD / NC⁽¹⁾

VDD

69

68

67

66

65

64

63

62

61

60

59

NC

VSS

I/O12

I/O13

VDDQ

VSS

I/O14

I/O15

I/OP2

NC

VSS

VDDQ

NC

58

57

56

55

54

53

NC

VSS

VDDQ

NC

,

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5301 drw 03

100TQFP

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins 38 and 39 can be either NC or connected to VSS.

3. Pin 64 can be left unconnected and the device will always remain in active mode.

6.462

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

2

9

NC

CS

NC

1

CS

0

7

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

CE

V

17

I/O

18

I/O

13

I/O

14

I/O

DDQ

V

19

I/O

12

I/O

DDQ

V

OE

20

21

11

10

I/O

G

H

J

2

3

BW

ADV

GW

BW

22

I/O

23

I/O

SS

V

SS

V

9

I/O

8

I/O

DDQ

DD

V

DD

DDQ

V

NC

V

24

26

SS

4

SS

6

7

I/O

V

CLK

V

I/O

K

L

(2)

25

I/O

27

I/O

4

I/O

5

I/O

NC

1

BW

DDQ

28

SS

3

I/O

DDQ

V

I/O

V

M

N

P

R

T

BWE

29

I/O

30

I/O

1

0

SS

V

2

I/O

1

I/O

A

31

I/O

P4

SS

V

0

I/O

P1

I/O

A

(1)

NC

5

DD

11

DD

13

A

/ NC

V

NC

A

V

LBO

(3)

10

A

14

A

NC

A

NC

DNU

,

ZZ

(4)

(2,4)

(4)

DDQ

V

DDQ

V

DNU

U

5301 drw 04

Top View

Pin Configuration 256K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

2

9

NC

CS

NC

1

CS

0

7

A

DD

V

13

17

A

8

SS

7

I/O

NC

V

NC

V

9

I/O

6

I/O

NC

CE

OE

DDQ

V

5

I/O

DDQ

V

NC

10

I/O

4

I/O

NC

G

H

J

BW2

ADV

GW

11

I/O

SS

V

SS

3

I/O

NC

V

NC

DDQ

V

DD

V

DD

DDQ

V

NC

V

12

SS

2

I/O

NC

I/O

V

CLK

V

NC

K

L

(2)

13

I/O

SS

1

NC

V

I/O

NC

1

BW

DDQ

V

14

I/O

SS

V

DDQ

V

M

N

P

R

T

BWE

15

SS

1

SS

0

I/O

NC

A

V

I/O

NC

P2

I/O

0

SS

P1

I/O

(1)

VDD / NC

5

DD

V

12

A

NC

DDQ

A

NC

LBO

(3)

,

10

15

14

A

11

A

NC

ZZ

(2,4)

(4)

DDQ

V

DNU

U

DNU

5301 drw 05

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. L4 and U4 can be either NC or connected to VSS.

3. T7 can be left unconnected and the device will always remain in active mode.

4. DNU = Do not use; Pins U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST on future revisions. Within this

current version, these pins are not connected.

6.42

7

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 128K x 36, 165 fBGA

1

2

3

4

5

6

7

8

ADSC

OE

9

10

A8

11

(4)

A

B

C

D

E

F

NC

A7

NC

CE¹

BW³

BW⁴

VSS

VDD

VSS

A2

BW²

BW¹

VSS

CS¹

CLK

VSS

BWE

GW

VSS

ADV

(4)

NC

A6

CS0

A9

NC

ADSP

VDDQ

NC

I/OP3

I/O17

I/O19

I/O21

I/O23

NC

VDDQ

NC

VSS

VDD

VSS

A10

NC

I/OP2

I/O14

I/O12

I/O10

I/O8

I/O16

I/O18

I/O20

I/O22

I/O15

I/O13

I/O11

I/O9

NC

G

H

J

(1)

(2)

(3)

VDD

NC

ZZ

I/O25

I/O27

I/O29

I/O31

I/OP4

NC

I/O24

I/O26

I/O28

I/O30

NC

VDDQ

A5

VDDQ

A13

I/O7

I/O5

I/O3

I/O1

NC

I/O6

I/O4

I/O2

I/O0

I/OP1

K

L

M

N

P

(5)

(4)

(2)

DNU

NC

(4)

(5)

(4)

NC

DNU

A1

A0

DNU

A14

A15

NC

(4)

(5)

R

NC

A4

A3

DNU

A11

A12

A16

LBO

5301 tbl 17

Pin Configuration 256K x 18, 165 fBGA

1

2

3

4

5

6

7

8

ADSC

OE

9

10

A8

11

(4)

A

B

C

D

E

F

NC

A7

NC

A

CE¹

BW²

NC

CS¹

CLK

VSS

BWE

GW

VSS

ADV

10

(4)

A6

CS0

A9

NC

BW¹

VSS

ADSP

VDDQ

NC

VDDQ

NC

VSS

VDD

VSS

A2

VSS

VDD

VSS

A11

NC

I/O3

I/O2

I/O1

I/O0

NC

A15

A16

I/OP1

I/O7

I/O6

I/O5

I/O4

I/O8

I/O9

I/O10

I/O11

G

H

J

(1)

(2)

(3)

VDD

I/O12

I/O13

I/O14

I/O15

I/OP2

NC

ZZ

NC

VDDQ

A5

VDDQ

A14

NC

K

L

M

N

P

(5)

(4)

(2)

DNU

NC

(4)

(5)

(4)

NC

DNU

A1

A0

DNU

NC

(4)

(5)

R

NC

A4

A3

DNU

A12

A13

A17

LBO

5301 tbl 17a

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. H2 and N7 can be either NC or connected to VSS.

3. H11 can be left unconnected and the device will always remain in active mode.

4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.

5. DNU = Do not use; Pins P5, P7, R5, R7 and N5 are reserved for respective JTAG Pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within the

current version these pins are not connected.

6.482

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

V^DD= Max., V^IN= 0V to V^DD

5

µA

(1)

___

ZZ and LBO Input Leakage Current

Output Leakage Current

Output Low Voltage

|I^LZZ|

|I^LO|

V^OL

V^OH

V^DD= Max., V^IN= 0V to V^DD

V^OUT= 0V to V^DDQ, Device Deselected

I^OL= +8mA, V^DD= Min.

30

5

µA

V

0.4

___

Output High Voltage

I^OH= -8mA, V^DD= Min.

2.4

V

5301 tbl 08

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating

TemperatureandSupplyVoltageRange⁽¹⁾

200MHz

Com'l

360

183MHz

Com'l

166 MHz

Com'l

Symbol

Parameter

Test Conditions

Ind

Unit

Operating Power Supply

Current

Device Selected, Outputs Open, V^DD= Max.,

V^DDQ= Max., V^IN> V^IHor < V^IL, f = f^MAX

340

350

320

330

mA

I^DD

(2)

I^SB1

I^SB2

I^ZZ

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, V^DD= Max.,

V^DDQ= Max., V^IN> V^HDor < V^LD, f = 0^(2,3)

30

130

30

35

130

35

30

35

120

35

mA

Clock Running Power

Supply Current

Device Deselected, Outputs Open, V^DD= Max.,

120

30

110

30

(2,3)

V^DDQ= Max., V^IN> V^HDor < V^LD, f = f^MAX

ZZ > V^HD,V^DD= Max.

Full Sleep Mode Supply

Current

mA

5301 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

AC Test Conditions

AC Test Load

VDDQ/2

(VDDQ = 3.3V)

50Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

,

5301 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

6

5

4

3

1.5V

See Figure 1

5301 tbl 10

∆tCD

(Typical, ns)

2

1

20 30 50

80 100

Capacitance (pF)

200

5301 drw 07

,

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

9

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousTruthTable^(1,3)

Operation

Address

CS

0

CLK

I/O

CE

CS

1

ADSP ADSC ADV

GW

BWE

BWx

OE

Used

(2)

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

H

L

X

L

X

H

X

H

X

L

X

L

X

L

X

L

X

H

L

X

H

L

X

H

L

X

L

-

HI-Z

None

L

None

L

X

L

X

L

None

L

External

H

X

L

D

OUT

Read Cycle, Begin Burst

L

H

L

HI-Z

Read Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

D

OUT

Read Cycle, Begin Burst

L

D

OUT

Read Cycle, Begin Burst

L

H

X

L

HI-Z

Write Cycle, Begin Burst

L

D

IN

OUT

HI-Z

Write Cycle, Begin Burst

L

X

H

X

H

X

L

X

H

X

H

L

D

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

L

D

H

L

D

OUT

H

L

HI-Z

D

OUT

H

L

HI-Z

D

OUT

H

X

L

HI-Z

D

IN

OUT

HI-Z

X

L

X

L

D

H

L

D

X

H

X

H

X

L

X

H

X

H

L

D

Current

H

L

D

H

L

D

OUT

H

L

HI-Z

D

OUT

H

L

HI-Z

D

OUT

H

X

HI-Z

D

IN

5301tbl 11

X

L

X

L

D

H

L

D

X

D

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.1402

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table^{(1, 2)}

Operation

GW

H

L

BWE

H

L

BW¹

BW²

X

BW³

X

BW⁴

X

Read

X

Read

H

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

X

L

X

H

L

H

L

H

L

H

L

H

L

H

L

H

L

5301 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW3 and BW4 are not applicable for the IDT71V35781.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

ZZ

I/O Status

Power

OE

Read

L

H

X

L

H

Data Out

High-Z

Active

Write

High-Z – Data In

High-Z

Active

Deselected

Sleep Mode

Standby

Sleep

High-Z

5301 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

0

A1

A0

First Address

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5301 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

0

A0

0

A1

0

A0

1

A1

1

A0

0

A1

1

A0

First Address

1

Second Address

Third Address

0

1

0

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5301 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.42

11

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

200MHz⁽⁵⁾

183MHz

166MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC

t

Clock Cycle Time

5

2

—

5.5

2.2

—

6

—

ns

(1)

CH

Clock High Pulse Width

Clock Low Pulse Width

2.4

t

(1)

CL

t

Output Parameters

CD

t

Clock High to Valid Data

—

1.0

0

3.1

—

1.0

0

3.3

—

1.0

0

3.5

—

ns

CDC

t

Clock High to Data Change

(2)

Clock High to Output Active

Clock High to Data High-Z

CLZ

t

(2)

1.5

—

0

3.1

—

1.5

—

0

3.3

—

1.5

—

0

3.5

—

ns

CHZ

t

OE

t

Output Enable Access Time

Output Enable Low to Output Active

Output Enable High to Output High-Z

(2)

OLZ

t

—

3.1

—

3.3

—

3.5

OHZ

t

Set Up Times

SA

t

Address Setup Time

1.2

—

1.5

—

1.5

—

ns

SS

t

Address Status Setup Time

Data In Setup Time

SD

t

SW

t

Write Setup Time

SAV

t

Address Advance Setup Time

Chip Enable/Select Setup Time

SC

t

Hold Times

HA

t

Address Hold Time

0.4

—

0.5

—

0.5

—

ns

HS

t

Address Status Hold Time

Data In Hold Time

HD

t

HW

t

Write Hold Time

HAV

t

Address Advance Hold Time

Chip Enable/Select Hold Time

HC

t

Sleep Mode and Configuration Parameters

ZZPW

t

ZZ Pulse Width

100

20

—

100

22

—

100

24

—

ns

(3)

ZZR

ZZ Recovery Time

Configuration Set-up Time

t

(4)

CFG

ns

t

5301tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

5. Commercial temperature range only.

6.1422

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Pipelined Read Cycle^(1,2)

,

6.42

13

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles^(1,2,3)

,

6.1442

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 - GW Controlled^(1,2,3)

,

6.42

15

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled^(1,2,3)

,

6.1462

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes^(1,2,3)

,

6.42

17

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW, BWE, BWx

CE, CS¹

CS⁰

OE

(Av)

(Aw)

(Ax)

(Ay)

DATA^OUT

,

5301 drw 14

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Forreadcycles, ADSP andADSCfunctionidenticallyandare therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW

CE, CS¹

CS⁰

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATA^IN

,

5301 drw 15

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.1482

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline

6.42

19

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.2402

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.42

21

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

OrderingInformation

IDT

XXX

S

X

XX

X

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

100-pin Plastic Thin Quad Flatpack (TQFP)

119 Ball Grid Array (BGA)

165 Fine Pitch Ball Grid Array (fBGA)

PF

BG

BQ

200*

183

166

Frequency in Megahertz

,

128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O

256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O

71V35761

71V35781

*Commercial temperature range only

5301 drw 13

6.2422

IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History

12/31/99

04/04/00

Creatednewdatasheetfrom71v3576and71v3578datasheet.

Addedindustrialtemperaturerangeofferingfrom166MHzand183MHz

Added100pinTQFPpackage DiagramOutline

Pg. 1, 4, 8, 11, 19

Pg. 18

Pg. 4

AddBGAcapacitancetable;Addindustrialtempertauretotable;InsertnotetoAbsoluteMax

RatingandRecommendedOperatingTemperaturetables

Addnewpackagediagramoutline,13x15mm165fBGA

CorrectBG119PackageDiagramOutline

06/01/00

07/15/00

Pg. 20

Pg. 7

AddnotereferencetoBG119pinout

Pg. 8

AddDNUreference note toBQ165pinout

Pg. 20

UpdateBG119PackageDiagramOutlineDimensions

RemovePreliminarystatus

10/25/00

Pg. 8

Add reference note to N5 on the BQ165 pinout, reserved for JTAG TRST

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726, x4033

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

23


型号：	IDT71V35781166PFI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, PLASTIC, TQFP-100 时钟静态存储器内存集成电路
文件：	总23页 (文件大小：519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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