IDT71V416YFS15BE [IDT]
Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 9 X 9 MM, POWER, BGA-48;
| 型号： | IDT71V416YFS15BE |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 9 X 9 MM, POWER, BGA-48 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
IDT71V416S
IDT71V416L
Description
Features
◆
TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized
as256Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
256K x 16 advanced high-speed CMOS Static RAM
◆
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
◆
– CommercialandIndustrial:10/12/15ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
◆
◆
TheIDT71V416has anoutputenablepinwhichoperates as fastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
noclocks orrefreshforoperation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mmpackage.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
◆
◆
◆
◆
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
FunctionalBlockDiagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 - A17
High
8
8
8
8
Byte
Output
Buffer
I/O 15
I/O 8
Chip
Select
Buffer
CS
High
Byte
Write
Buffer
Sense
Amps
and
Write
Drivers
4,194,304-bit
Memory
Array
16
Write
Enable
Buffer
Low
Byte
8
8
8
8
WE
I/O 7
I/O 0
Output
Buffer
Low
Byte
Write
Buffer
BHE
BLE
Byte
Enable
Buffers
3624 drw 01
NOVEMBER 2002
1
©2002IntegratedDeviceTechnology,Inc.
DSC-3624/06
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations - SOJ/TSOP
Pin Configurations - 48 BGA
A0
A1
A2
A3
A4
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
1
2
3
4
5
6
A16
A15
OE
A
B
C
D
E
A0
A1
A2
NC
BLE
OE
3
4
I/O0
I/O1
VSS
VDD
I/O6
I/O7
NC
A3
A5
A4
A6
I/O8
I/O9
VDD
VSS
BHE
I/O2
I/O3
I/O4
I/O5
NC
CS
5
BHE
BLE
6
CS
I/O10
I/O11
I/O12
I/O13
WE
I/O 0
I/O 1
I/O 2
I/O 3
7
I/O 15
I/O 14
I/O 13
I/O 12
8
A17
NC
A14
A12
A9
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A16
A15
A13
A10
SO44-1
SO44-2
DD
V
V
V
V
SS
DD
SS
F
I/O14
I/O15
I/O 4
I/O 5
I/O 6
I/O 7
WE
A5
I/O 11
I/O 10
I/O 9
G
H
I/O 8
NC*
A14
A13
A12
A8
A11
NC
3624 tbl 11
A6
A7
A8
A11
A10
A9
3624 drw 02
*Pin 28 can either be a NC or connected to Vss
Top View
SOJCapacitance
(TA = +25°C, f = 1.0MHz)
PinDescriptions
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max. Unit
A0 - A17
Address Inputs
Input
Symbol
CIN
Chip Select
Input
Input
Input
Input
Input
I/O
CS
VIN = 3dV
7
8
pF
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
WE
CI/O
VOUT = 3dV
pF
3624 tbl 02
OE
BHE
48BGACapacitance
(TA = +25°C, f = 1.0MHz)
BLE
I/O0 - I/O15
VDD
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Pwr
6
7
pF
VSS
Ground
Gnd
CI/O
pF
3624 tbl 01
3624 tbl 02b
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.422
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupply
Voltage
Symbol
Rating
Value
Unit
V
VDD
Supply Voltage Relative to VSS
-0.5 to +4.6
-0.5 to VDD+0.5
Grade
Commercial
Industrial
Temperature
0OC to +70OC
–40OC to +85OC
VSS
0V
0V
VDD
Terminal Voltage Relative to
VSS
V
See Below
See Below
VIN, VOUT
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
oC
oC
W
3624 tbl 05
-55 to +125
1
RecommendedDCOperating
Conditions
IOUT
DC Output Current
50
mA
3624 tbl 04
NOTE:
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
Max.
3.6
0
Unit
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
VDD
3.3
VSS
0
V
(1 )
____
VDD+0.3
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
V
-0.3(2 )
____
V
3624 tbl 06
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Truth Table(1)
I/O0-I/O7
High-Z
I/O8-I/O15
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
CS
H
L
L
L
L
L
L
L
L
OE
X
L
WE
X
H
H
H
L
BLE
X
L
BHE
X
H
L
DATAOUT
High-Z
High-Z
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
DATAOUT
DATAIN
DATAIN
High-Z
X
X
X
H
X
L
L
Word Write
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
L
H
X
H
DATAIN
High-Z
H
X
X
H
High-Z
High-Z
High-Z
3624 tbl 03
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.42
3
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V416
Symbol
|ILI|
Parameter
Input Leakage Current
Test Conditions
VCC = Max., VIN = VSS to VDD
Min.
Max.
Unit
µA
µA
V
___
5
5
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
VDD = Max., CS = VIH, VOUT = VSS to VDD
IOL = 8mA, VDD = Min.
VOL
0.4
___
VOH
IOH = -4mA, VDD = Min.
2.4
V
3624 tbl 07
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V416S/L10
Com'l.
Ind.(5 )
200 200
71V416S/L12
71V416S/L15
Com'l.
Ind.
180
170
60
Com'l.
Ind.
170
160
50
Symbol
Parameter
Dynamic Operating Current
Unit
ICC
S
L
S
L
S
L
180
170
60
170
160
50
mA
(4 )
MAX
CS
LC
DD
< V , Outputs Open, V = Max., f = f
180
70
50
20
10
—
70
—
20
—
ISB
Dynamic Standby Power Supply Current
CS > VHC, Outputs Open, VDD = Max., f = fMAX
mA
(4 )
45
45
40
40
ISB1
Full Standby Power Supply Current (static)
mA
20
20
20
20
CS > VHC, Outputs Open, VDD = Max., f = 0(4 )
10
10
10
10
3624 tbl 08
NOTES:
IDT71V416S/71V416L
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
3.3V
320
AC Test Loads
+1.5V
Ω
50
Ω
DATA OUT
I/O
0
Z = 50Ω
5pF*
350
Ω
30pF
3624 drw 03
3624 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
•
AC Test Conditions
∆t
AA, tACS
5
4
3
2
1
(Typical, ns)
Input Pulse Levels
GND to 3.0V
1.5ns
•
•
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
•
•
•
1.5V
•
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
1.5V
3624 drw 05
Figures 1,2 and 3
Figure 3. Output Capacitive Derating
3624 tbl 09
6.442
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10(2)
71V416S/L12
71V416S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
tAA
tACS
Read Cycle Time
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
Address Access Time
Chip Select Access Time
10
12
15
____
____
____
10
12
15
(1)
____
____
____
tCL Z
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
4
4
4
(1)
____
____
____
tCHZ
5
6
7
____
____
____
tOE
5
6
7
(1)
____
____
____
tOLZ
0
0
0
(1)
____
____
____
tOHZ
5
6
7
____
____
____
tOH
tBE
4
4
4
____
____
____
5
6
7
(1)
____
____
____
tBLZ
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
0
0
0
(1)
____
____
____
tBHZ
5
6
7
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tAW
tCW
tBW
tAS
Write Cycle Time
10
8
8
8
0
0
8
5
0
12
8
8
8
0
0
8
6
0
15
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
tWR
tWP
tDW
tDH
Address Hold from End of Write
Write Pulse Width
0
10
7
Data Valid to End of Write
Data Hold Time
0
(1)
tOW
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
3
3
3
(1)
____
____
____
tWHZ
6
7
7
ns
3624 tbl 10
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
t
OH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
3624 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
t
RC
ADDRESS
t
OH
t
AA
OE
CS
(3)
t
OHZ
(3)
t
OE
(3)
t
OLZ
(2)
t
ACS
(3)
t
CHZ
t
CLZ
BLE
BHE,
(2)
t
BE
(3)
(3)
BHZ
t
t
BLZ
DATAOUT
DATAOUT VALID
3624 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
t
WC
ADDRESS
CS
t
AW
(2)
(5)
(5)
t
CW
t
CHZ
t
BW
BHE
,
BLE
WE
t
WR
t
BHZ
t
WP
t
AS
(5)
t
WHZ
(5)
t
OW
PREVIOUS DATA VALID (3)
DATA VALID
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
3624 drw 0
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.462
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)
t
WC
ADDRESS
CS
t
AW
(2)
t
AS
t
CW
t
BW
BHE, BLE
t
WP
t
WR
WE
DATAOUT
t
DH
t
DW
DATA
IN
IN
DATA VALID
3624 drw 09
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)(1,3)
t
WC
ADDRESS
CS
t
AW
(2)
t
CW
t
AS
t
BW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
t
DH
t
DW
DATAIN VALID
3624 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.42
7
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
OrderingInformation
IDT
71V416
X
X
XX
XXX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Y
PH
BE
44-pin, 400-mil SOJ (SO44-1)
44-pin TSOP Type II (SO44-2)
48 Ball Grid Array
10*
12
Speed in nanoseconds
15
S
L
Standard Power
Low Power
Blank
YF
First Generation or current stepping being shipped
Second Generation die step
* Commercial only for low power 10ns (L10) speed grade and
Industrial only for standard power 10ns (S10) speed grade.
3624 drw 11a
6.482
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
08/5/99
Updatedtonewformat
RevisedfootnotefortCW onWriteCycleNo.1diagram
Pg 6
08/31/99
Pg. 1–9
Pg. 9
Pg. 6
AddedIndustrialtemperaturerangeoffering
AddedDatasheetDocumentHistory
ChangednotetoWritecycleNo.1accordingtofootnotes
Add 48 ball grid array package offering
Correct TTL to LVTTL
03/24/00
08/10/00
Pg. 1
Pg. 2
Pg. 8
09/11/ 02
11/26/02
UpdatedTBDinformationforthe48BGACapacitancetable
Added"DieRevision"toorderinginformation
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726, x4033
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
9
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