IDT71V67702S80BGI [IDT]
256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect; 256K X 36 ， 512K X 18 3.3V同步SRAM 2.5VI / O，突发流量计数器，通过输出，单周期取消
| 型号： | IDT71V67702S80BGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect |
| 文件： | 总23页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K X 36, 512K X 18
3.3VSynchronousSRAMs
2.5V I/O, Burst Counter
IDT71V67702
IDT71V67902
Flow-ThroughOutputs,SingleCycleDeselect
Features
◆
data, address and control registers. There are no registers in the data
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
theendofthewritecycle.
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67702/7902canprovidefourcyclesof
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
256K x 36, 512K x 18 memory configurations
◆
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol( ),bytewrite
◆
◆
enable (
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball
grid array (fBGA).
), and byte writes ( x)
◆
◆
◆
◆
the same cycle. If burst mode operation is selected (
=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandthe
inputpin.
TheIDT71V67702/7902SRAMsutilizeIDT’slatesthigh-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
Description
The IDT71V67702/7902 are high-speed SRAMs organized as
256Kx36/512Kx18.TheIDT71V67702/7902SRAMs containwrite,
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS0, CS1
OE
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
GW
BWE
(1)
BW1, BW2, BW3, BW4
CLK
Clock
Input
Input
Input
Input
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
VSS
Core Power, I/O Power
Ground
Supply
Supply
N/A
5317 tbl 01
NOTE:
1.
3 and
4 are not applicable for the IDT71V67902.
DECEMBER 2003
1
©2002IntegratedDeviceTechnology,Inc.
DSC-5317/08
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSC
ADSP
ADV
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; thatis, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BWE
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
BW1-BW4
CE
Chip Enable
Synchronous chip enable. CEis used with CS0 and CS1 to enable the IDT71V67702/7902.
CE also gates ADSP.
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS0
CS1
GW
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by
the rising edge of CLK. The data output path is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
VDD
VDDQ
VSS
NC
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
1
N/A
N/A
3.3V core power supply.
2.5V I/O Supply.
N/A
Ground.
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
ZZ
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down
the IDT71V67702/7902 to its lowest power consumption level. Data retention is guaranteed
in Sleep Mode.
5317t tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
18/19
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
0
A ,A
1
2 - 18
A A
ADDRESS
REGISTER
A A
0– 17/18
36/18
36/18
18/19
G W
BW E
Byte 1
Write Register
Byte 1
Write Driver
BW
BW
1
2
9
9
Byte 2
Write Register
Byte 2
Write Driver
Byte 3
Write Register
Byte 3
Write Driver
BW
BW
3
4
9
9
Byte 4
Write Register
Byte 4
Write Driver
CE
CS
Q
D
0
Enable
Register
CLK EN
DATA INPUT
REGISTER
1
CS
ZZ
Powerdown
OE
OUTPUT
BUFFER
O E
,
36/18
I/O
0
–I/O31
I/OP1–I/OP4
5317 drw 01
6.42
3
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureSupplyVoltage
Symbol
Rating
Commercial
Unit
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
VSS
0V
0V
VDD
VDDQ
(2)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
3.3V±5%
3.3V±5%
2.5V±5%
(3,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
V
V
2.5V±5%
5317 tbl 04
NOTE:
1. TA is the "instant on" case temperature.
(4,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
(5,6)
RecommendedDCOperating
Conditions
VTERM
Terminal Voltage with
Respect to GND
Commercial
Industrial
-0 to +70
-40 to +85
-55 to +125
oC
oC
oC
Symbol
Parameter
Min. Typ.
3.135 3.3
2.375 2.5
Max.
Unit
V
(7)
TA
VDD
Core Supply Voltage
3.465
2.625
Temperature
Under Bias
TBIAS
VDDQ I/O Supply Voltage
V
VSS
VIH
VIH
VIL
Ground
0
1.7
0
0
V
Storage
Temperature
-55 to +125
oC
TSTG
____
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
VDD +0.3
VDDQ +0.3
0.7
V
____
____
1.7
V
PT
Power Dissipation
DC Output Current
2.0
50
W
-0.3(1 )
V
IOUT
mA
5317 tbl 06
5317 tbl 03
NOTE:
NOTES:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100-PinTQFPCapacitance
(TA = +25° C, f = 1.0MHz)
165 fBGA Capacitance
(TA = +25° C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
Symbol
CIN
5
7
pF
7
7
pF
CI/O
pF
CI/O
pF
5317 tbl 07
5317 tbl 07b
119BGACapacitance
(TA = +25° C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
7
pF
CI/O
pF
5317 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/OP3
2
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
3
78
77
4
5
76
75
74
73
6
7
8
9
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
I/O22
I/O23
(1)
VSS
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
,
I/O0
I/OP1
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5317 drw 02a
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
NC
NC
NC
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
2
3
78
77
4
5
76
75
74
73
72
71
70
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
69
68
67
66
I/O10
I/O11
(1)
VSS
VDD
NC
VSS
65
64
63
62
61
60
59
58
57
56
55
54
53
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
,
52
51
NC
NC
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5317 drw 02b
TopView
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
A17
NC
NC
CS0
NC
NC
7
A
DD
V
12
A
15
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
V
V
OE
21
23
11
I/O
BW3
ADV
GW
BW2
I/O
I/O
I/O
G
H
J
22
I/O
SS
V
SS
V
9
I/O
8
I/O
I/O
DDQ
24
DD
26
DD
V
DD
6
DDQ
7
V
NC
NC
V
V
SS
V
SS
V
K
L
I/O
I/O
CLK
NC
I/O
I/O
25
I/O
27
I/O
4
I/O
5
I/O
BW4
BW1
DDQ
29
28
I/O
SS
V
SS
V
3
I/O
DDQ
V
M
N
P
R
T
BWE
30
P4
SS
V
1
A
SS
V
2
I/O
1
I/O
I/O
I/O
31
I/O
SS
V
0
A
SS
V
I/O
I/OP1
I/O0
NC
(1)
SS
5
A
DD
V
V
13
A
NC
LBO
(2)
10
A
11
A
14
NC
NC
A
NC
ZZ
U
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DDQ
V
DDQ
V
5317 drw 02c
Top View
Pin Configuration 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
ADSP
ADSC
(4)
3
A
9
A
18
17
NC
NC
NC
NC
NC
CS
0
7
A
2
A
DD
V
13
A
A
8
I/O
SS
SS
P1
I/O
NC
V
NC
CE
V
9
I/O
SS
SS
7
I/O
NC
V
V
NC
DDQ
V
SS
SS
6
I/O
DDQ
V
NC
V
V
OE
10
2
SS
5
I/O
G
H
J
NC
I/O
I/O
V
NC
BW
ADV
GW
11
SS
SS
V
4
I/O
NC
V
NC
DDQ
V
DD
DD
V
DD
V
DDQ
V
V
NC
NC
12
SS
SS
3
NC
I/O
I/O
NC
I/O
NC
I/O
V
CLK
NC
V
NC
I/O
K
L
SS
V
13
1
BW
2
I/O
NC
NC
DDQ
V
14
SS
V
SS
V
DDQ
V
M
N
P
R
T
BWE
15
SS
V
1
A
SS
V
1
I/O
I/O
NC
NC
NC
NC
P2
SS
V
0
A
SS
V
0
NC
I/O
NC
(1)
SS
5
DD
V
12
A
A
V
LBO
(2)
10
15
A
14
A
11
A
A
NC
ZZ
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DNU(3)
DDQ
V
DDQ
V
U
5317 drw 02d
,
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M device CS0 will be removed, B2 will be used for address expansion.
6.42
7
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(3)
A
B
C
D
E
F
NC
A7
NC
CE
BW3
BW4
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A2
BW2
BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
CS1
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
(3)
NC
A6
CS0
A9
NC
I/OP3
I/O17
I/O19
I/O21
I/O23
VSS(1)
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A10
NC
I/OP2
I/O14
I/O12
I/O10
I/O8
I/O16
I/O18
I/O20
I/O22
NC
I/O15
I/O13
I/O11
I/O9
NC
G
H
J
(2)
ZZ
I/O24
I/O26
I/O28
I/O30
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
I/O7
I/O5
I/O3
I/O1
NC
I/O6
I/O4
I/O2
I/O0
I/OP1
A17
K
L
M
N
P
(3)
NC
(3)
(4)
(4)
NC
DNU
A1
A0
DNU
A14
A15
(3)
(4)
(4)
R
NC
A4
A3
DNU
DNU
A11
A12
A16
LBO
5317tbl 17a
Pin Configuration 512K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
A8
11
(3)
A
B
C
D
E
F
NC
NC
A7
NC
A10
CE
BW2
NC
CS1
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
ADV
(3)
A6
CS0
A9
NC
BW1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
I/O8
I/O9
I/O10
I/O11
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/OP1
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
G
H
J
NC
VSS(1)
I/O12
I/O13
I/O14
ZZ
(2)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
NC
A18
K
L
M
N
P
I/O
15
V
V
DD
V
SS
V
SS
V
SS
V
DD
V
I/O
0
DDQ
DDQ
(3)
I/OP2
NC
VDDQ
A5
VSS
A2
NC
NC
A1
A0
NC
VSS
A11
A12
VDDQ
A14
NC
A15
A16
(3)
(4)
(4)
NC
DNU
DNU
(3)
(4)
(4)
R
NC
A4
A3
DNU
DNU
A13
A17
LBO
5317 tbl 17b
NOTES:
1. H1 does not have to be directly connected to VSS, as long as the input voltage is < VIL.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.482
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1 )
___
___
___
LBO Input Leakage Current
|ILI|
VDD = Max., VIN = 0V to VDD
VOUT = 0V to VCC
30
5
µA
µA
V
|ILO|
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
IOL = +6mA, VDD = Min.
IOH = -6mA, VDD = Min.
0.4
___
2.0
V
5317
tbl 08
NOTE:
1. The
pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
7.5ns
8ns
8.5ns
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
Com'l
Ind
Com'l
Ind
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
mA
mA
mA
mA
IDD
265
285
210
230
190
210
(2)
ISB1
ISB2
IZZ
CMOS Standby Power Supply Current
Clock Running Power Supply Current
Full Sleep Mode Supply Current
Device Deselected, Outputs Open, VDD = Max.,
50
70
50
70
50
70
(2,3)
VDDQ = Max., VIN > VHD or < VLD, f = 0
Device Deselected, Outputs Open, VDD = Max.,
145
50
165
70
140
50
160
70
135
50
155
70
(2,.3)
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
ZZ > VHD, VDD = Max.
5317
tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
= LOW; f=0 means no input lines are changing.
AC Test Conditions
(VDDQ = 2.5V)
AC Test Load
DDQ
V
/2
50Ω
Input Pulse Levels
0 to 2.5V
2ns
I/O
Z = 50Ω
0
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
(VDDQ/2)
(VDDQ/2)
See Figure 1
5317 drw 03
Figure 1. AC Test Load
6
5
4
3
5317 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5317 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
CE
CS1 ADSP ADSC ADV
GW
BWE BWx OE(2)
Operation
Address
Used
CS0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DOUT
HI-Z
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Read Cycle, Begin Burst
L
L
L
H
L
OUT
D
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
Read Cycle, Begin Burst
L
L
L
L
DOUT
HI-Z
DIN
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Write Cycle, Begin Burst
L
L
L
L
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
L
Next
L
Next
L
H
X
X
X
X
L
Next
L
Next
L
X
L
X
L
DIN
Next
L
H
L
DIN
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
DIN
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DOUT
HI-Z
DIN
H
L
H
L
H
L
H
X
X
X
X
X
L
X
L
DIN
H
L
DIN
X
X
DIN
5317 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2.
is an asynchronous input.
3. ZZ - low for the table.
6.1402
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table (1, 2)
GW
H
H
L
BWE
H
L
BW1
BW2
X
BW3
X
BW4
X
Operation
Read
X
Read
H
H
H
H
Write all Bytes
Write all Bytes
X
L
X
X
X
X
H
H
H
H
H
L
L
L
L
(3)
Write Byte 1
L
L
H
H
H
(3)
Write Byte 2
L
H
L
H
H
(3)
Write Byte 3
L
H
H
L
H
(3)
Write Byte 4
L
H
H
H
L
5317 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. 3 and 4 are not applicable for the IDT71V67902.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5317 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5317 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5317 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
tCY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
tCH
____
____
____
(1)
3
4
4.5
tCL
Output Parameters
____
____
____
tCD
Clock High to Valid Data
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
Output Enable Low to Output Active
2
0
2
0
2
0
(2)
____
____
____
tCL Z
(2)
2
3.5
2
3.5
2
3.5
ns
ns
ns
ns
tCHZ
____
____
____
tOE
3.5
3.5
3.5
____
____
____
(2)
0
0
0
tOLZ
____
____
____
(2)
Output Enable High to Output High-Z
3.5
3.5
3.5
tOHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tSA
tSS
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
Address Status Setup Time
Data In Setup Time
tSD
tSW
tSAV
tSC
Write Setup Time
Address Advance Setup Time
Chip Enable/Select Setup Time
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tHS
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Address Status Hold Time
Data In Hold Time
tHD
tHW
tHAV
tHC
Write Hold Time
Address Advance Hold Time
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
tZZPW
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
(3)
tZZR
ZZ Recovery Time
Configuration Set-up Time
tCFG(4)
ns
5317 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the
input.
is a static input and must not change during normal operation.
6.1422
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle (1,2)
,
6.42
13
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
,
6.1442
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
(1,2,3)
Timing Waveform of Write Cycle No. 1 - GW Controlled
,
6.42
15
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
,
6.1462
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
6.42
17
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW , BW E, BW x
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5317 drw 10
NOTES:
1. ZZ input is LOW,
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, and function identically and are therefore interchangable.
is HIGH and
is Don't Care for this cycle.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5317 drw 11
NOTES:
1. ZZ input is LOW,
and
are HIGH, and
is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
4. For write cycles,
writes are shown, the functionality of
and have different limitations.
and
x together is the same as
.
6.1482
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.2402
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
XX
IDT XXX
S
XX
X
Process/Temp
Range
Device
Type
Power
Speed
Package
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BG
BQ
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
75
80
85
Access Time in Tenths of Nanoseconds
,
71V67702 256K x 36 Flow-Through Burst Synchronous SRAM
71V67902 512K x 18 Flow-Through Burst Synchronous SRAM
5317 drw 12
6.2422
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
04/26/00
CreatedDatasheetfrom71V677and71V679Datasheets
For3.3VI/Ooffering, see 71V67703and71V67903Datasheets
Pg. 4
AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsand
RecommendedOperatingTemperaturetables.
Pg. 7
Replace PinU6with
pininBGApinconfiguration;Addpindescriptionnote inpinout
Pg. 18
Inserted100pinTQFPPackageDiagramOutline
05/24/00
07/12/00
Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correctnote 2onBGA and TQFP pinconfiguration
Pg. 20
Pg. 5,6,8
Pg. 7
Pg. 20
Pg. 9
Correctioninthe119BGAPackageDiagramOutline
RemovenotefromTQFPandBQ165pinout
Add/RemovereferencenotefromBG119pinout
UpdateBG119packagediagramoutlinedimensions
Updated ISB2 levels for tcd = 7.5ns - 8.5ns
RemoveJTAGpins
07/16/01
10/29/01
Pg. 1,2
Pg. 7
Changed U2-U6 pins to DNU
Pg. 8
Pg. 9
Changed P5, P7, R5 & R7 pins to DNU
Raise specs on 7.5ns, 8ns & 8.5ns by 10mA
08/27/02
Pg. 4,9,12, AddedIndustrialinformationtothedatasheet.
22
10/22/02
04/15/03
12/20/03
Pg. 1-23
Pg. 4
Pg. 7
ChangeddatasheetfromAdvancedInformationtoFinalRelease.
Updated165fBGAtablefromTBDto7.
Updated 119BGA pin configurations- I/O signals on P6, P7 (128K x36) and P7, N6, L6, K7,
H6, G7, F6, E7, D6 (256K x 18).
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