IDT71V67803S133BG [IDT]
Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119;
| 型号： | IDT71V67803S133BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119 静态存储器 |
| 文件： | 总23页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K X 36, 512K X 18
IDT71V67603/Z
IDT71V67803/Z
3.3VSynchronousSRAMs
3.3V I/O, Burst Counter
PipelinedOutputs,SingleCycleDeselect
Features
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil
the endofthe write cycle.
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
orderofthesethreeaddressesaredefinedbytheinternalburstcounter
andthe LBO inputpin.
◆
◆
write enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (VDDQ)
◆
◆
◆
◆
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-
pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165
fine pitchballgridarray(fBGA).
Description
The IDT71V67603/7803 are high-speed SRAMs organized as
PinDescriptionSummary
A0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
OE
GW
0
, CS
1
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
5310 tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
FEBRUARY 2009
1
©2007IntegratedDeviceTechnology,Inc.
DSC-5310/07
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
Address Status
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
ADSC
ADSP
ADV
(Cache Controller)
used to load the address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOWinput that is used to
load the address registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
inputis HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW
1
-BW . If BWE is LOW at the
4
BWE
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
Individual Byte
Write Enables
I
I
I
LOW
LOW
N/A
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW
2
controls I/O8-15, I/OP2, etc.
BW
1
-BW
4
Any active byte write causes all outputs to be disabled.
Chip Enable
Synchronous chip enable. CE is used with CS
CE also gates ADSP.
0
and CS1 to enable the IDT71V67603/7803.
CE
CLK
Clock
This is the clock input. All timing references for the device are made with respect to this
input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
I
I
I
HIGH
LOW
LOW
Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to enable the chip.
Synchronous active LOW chip select. CS
1
is used with CE and CS0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Linear Burst Order
LOW
Asynchronous burstorder selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
OE
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
I
N/A
N/A
3.3V core power supply.
V
3.3V I/O Supply.
V
N/A
Ground.
NC
ZZ
No Connect
Sleep Mode
N/A
NC pins are not electrically connected to the device.
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67603/7803 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
5310 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
CLK
2
Burst
Logic
18/19
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
CLR
ADSP
2
CLK EN
A0,A1
A2–A18
A0–A17/18
ADDRESS
REGISTER
36/18
36/18
18/19
GW
Byte 1
Write Register
BWE
Byte 1
Write Driver
BW
1
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
OUTPUT
REGISTER
CE
CS
CS
Q
D
0
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
ZZ
Powerdown
D
Q
Enable
Delay
Register
OE
OUTPUT
BUFFER
OE
,
36/18
I/O
0–I/O31
I/OP1–I/OP4
5301 drw 01
6.42
3
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Commercial
Unit
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
VDD
VDDQ
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
3.3V±5%
5310 tbl 04
NOTE:
1. TA is the "instant on" case temperature.
VTERM
Terminal Voltage with
Respect to GND
RecommendedDCOperating
Conditions
VTERM
Terminal Voltage with
Respect to GND
V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
oC
oC
oC
W
T (7)
A
Operating Temperature
V
DD
DDQ
SS
IH
IH
IL
3.465
3.465
0
V
V
V
V
V
Temperature
Under Bias
-55 to +125
TBIAS
V
V
0
2.0
0
Storage
-55 to +125
TSTG
____
V
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
VDD +0.3
Temperature
____
____
V
2.0
VDDQ +0.3
P
T
Power Dissipation
DC Output Current
2.0
50
V
-0.3(1)
0.8
V
IOUT
mA
5310 tbl 05
5310 tbl 03
NOTES:
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
165fBGACapacitance
100PinTQFPCapacitance
(TA = +25°C, f = 1.0MHz)
(TA = +25°C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
7
7
pF
CI/O
VOUT = 3dV
pF
CI/O
VOUT = 3dV
pF
5310 tbl 07
5310 tbl 07b
119BGACapacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5310 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
70
VDDQ
VDDQ
69
68
67
66
65
64
I/O22
I/O23
I/O9
I/O8
V
DD / NC(1)
V
SS
NC
VDD
NC
V
DD
ZZ(2)
V
SS
I/O24
I/O25
63
62
I/O7
I/O6
61
60
59
58
57
56
55
54
53
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
I/OP1
1
,
52
51
0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5301 drw 02
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
A
NC
NC
10
2
3
4
V
DDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
NC
NC
I/O8
NC
I/OP1
I/O
7
8
7
9
I/O9
72
71
I/O
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
70
69
68
67
66
65
64
V
DDQ
VDDQ
I/O10
I/O11
I/O
I/O
5
4
V
DD / NC(1)
VSS
VDD
NC
NC
V
DD
ZZ(2)
V
SS
I/O12
I/O13
63
62
61
60
59
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
58
57
56
55
0
VSS
VSS
,
54
53
V
DDQ
VDDQ
NC
NC
NC
NC
NC
NC
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5310 drw 03
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
6
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
A
17
15
3
2
9
NC
NC
CS
NC
NC
0
7
A
DD
V
12
A
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
V
19
I/O
12
I/O
DDQ
V
OE
20
21
11
10
I/O
I/O
I/O
I/O
G
H
J
2
3
BW
ADV
GW
BW
22
I/O
23
I/O
SS
V
SS
V
9
I/O
8
I/O
DDQ
DD
DD
V
DD
DDQ
7
V
V
NC
NC
V
V
24
I/O
26
I/O
SS
V
SS
V
6
I/O
K
L
CLK
NC
I/O
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
1
BW
DDQ
28
SS
V
SS
V
3
DDQ
V
M
N
P
R
T
V
I/O
I/O
BWE
29
I/O
30
P4
SS
1
0
SS
2
I/O
1
I/O
I/O
V
V
A
A
V
V
0
I/O
31
SS
SS
P1
I/O
NC
NC
I/O
I/O
(1)
NC
5
DD
V
13
A
V
DD / NC
A
LBO
(2)
,
10
A
11
A
14
A
NC
NC
ZZ
DDQ
V
DNU(3)
DNU(3)
DDQ
V
DNU(3)
U
DNU(3)
DNU(3)
5310 drw 04
Top View
Pin Configuration – 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
18
17
DDQ
V
V
A
A
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
(4)
3
2
9
NC
NC
CS
NC
NC
NC
0
7
DD
V
13
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
NC
V
V
V
NC
V
V
V
V
V
I/O
NC
9
I/O
7
I/O
NC
CE
OE
DDQ
V
6
DDQ
V
NC
I/O
NC
10
I/O
5
I/O
G
H
J
NC
BW
2
ADV
GW
11
I/O
SS
SS
4
I/O
NC
V
NC
DDQ
V
DD
DD
V
DD
DDQ
V
V
NC
V
NC
12
SS
SS
3
NC
I/O
NC
V
CLK
NC
V
NC
I/O
K
L
13
I/O
SS
2
I/O
V
V
V
V
NC
1
BW
DDQ
V
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
NC
M
N
P
R
T
BWE
15
I/O
1
0
1
I/O
NC
A
NC
P2
0
I/O
NC
NC
NC
DDQ
I/O
A
NC
(1)
5
DD
V
12
A
A
V
DD / NC
NC
LBO
(2)
,
10
15
14
A
11
A
A
A
NC
ZZ
DNU(3)
DDQ
V
5310 drw 05
DNU(3)
DNU(3)
U
V
DNU(3)
DNU(3)
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M device CS0 will be removed, B2 will be used for address expansion.
6.42
7
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
(3)
A
B
C
D
E
F
NC
A
7
A
8
NC
CE
BW
3
BW
2
CS
1
BWE
GW
ADSC
OE
ADV
ADSP
(3)
NC
A6
CS
0
CLK
A9
NC
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
10
11
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/OP2
I/O14
I/O12
I/O10
I/O16
I/O18
I/O20
I/O22
NC
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
I/O23
VDDQ
V
V
V
V
V
V
I/O
NC
I/O
I/O
I/O
I/O
NC
9
I/O8
(1)
(2)
V
DD
NC
V
V
V
V
V
NC
ZZ
I/O
I/O
I/O
I/O
I/OP1
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
I/O24
I/O26
I/O28
I/O30
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
13
7
6
K
L
M
N
P
V
V
V
V
V
V
V
5
4
V
V
V
V
V
V
V
3
2
V
V
V
V
V
V
V
1
0
(3)
V
V
NC
NC
NC
V
V
(3)
(4)
(4)
NC
A5
A2
DNU
A1
DNU
A
A
A14
A
17
16
5310 tbl 17a
(3)
(4)
(4)
R
NC
A4
A3
DNU
A0
DNU
A
A12
A15
A
LBO
Pin Configuration – 512K x 18, 165 fBGA
1
2
3
4
5
6
7
BWE
GW
8
9
10
11
(3)
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
A7
NC
A8
A10
CE
BW
2
CS
1
ADSC
OE
ADV
ADSP
(3)
A6
CS
0
NC
CLK
A9
NC
BW
1
NC
V
DDQ
DDQ
DDQ
DDQ
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
11
12
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/OP1
I/O
8
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
I/O
9
V
V
V
V
V
V
V
6
I/O10
V
V
V
V
V
V
V
5
G
H
J
I/O
V
DDQ
V
V
V
V
V
V
4
11
(1)
(2)
V
DD
NC
NC
NC
NC
NC
NC
NC
V
V
V
V
V
NC
ZZ
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
14
13
I/O
I/O
I/O
I/O
NC
3
NC
NC
NC
NC
NC
K
L
M
N
P
V
V
V
V
V
V
V
2
V
V
V
V
V
V
V
1
V
V
V
V
V
V
V
0
(3)
V
V
NC
NC
NC
V
V
(3)
(4)
(4)
NC
A5
A2
DNU
A1
DNU
A
A
A15
A
18
17
5310 tbl 17b
(3)
(4)
(4)
R
NC
A4
A3
DNU
A0
DNU
A
A
A16
A
LBO
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.42
8
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
(1)
___
___
___
ZZ and LBO Input Leakage Current
Output Leakage Current
Output Low Voltage
|ILZZ
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +8mA, VDD = Min.
OH = -8mA, VDD = Min.
30
5
µA
µA
V
|ILO
|
V
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
5310 tbl 08
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
166MHz
150MHz
Com'l
133MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l only
Ind
Ind
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
mA
mA
mA
I
DD
340
50
305
50
325
260
50
280
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
70
175
70
70
170
70
V
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
160
50
155
50
150
50
(2,3)
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
ZZ > VHD, DD = Max.
V
Full Sleep Mode Supply
Current
mA
IZZ
5310 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ/2
AC Test Conditions
AC Test Load
(VDDQ = 3.3V)
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
5310 drw 06
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
Figure 1. AC Test Load
6
5
4
1.5V
See Figure 1
5310 tbl 10
3
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
5310 drw 07
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,3)
Operation
Address
Used
CS0
CLK
I/O
CE
CS
1
ADSP ADSC ADV
GW
BWE
BWx
OE
(2)
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
5310 tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
6.42
10
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
SynchronousWrite Function Truth Table(1, 2)
Operation
GW
H
H
L
BWE
H
L
BW
X
H
X
L
1
BW
X
H
X
L
2
BW
X
H
X
L
3
BW4
Read
X
Read
H
X
L
Write all Bytes
Write all Bytes
Write Byte 1(3)
Write Byte 2(3)
Write Byte 3(3)
Write Byte 4(3)
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
5310 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67803.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
ZZ
I/O Status
Power
OE
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Read
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5310 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5310 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5310 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
166MHz
150MHz
133MHz
Max.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Unit
____
____
____
____
____
____
t
CY C
Clock Cycle Time
6
6.7
2.6
2.6
7.5
3
ns
ns
ns
(1)
Clock High Pulse Width
Clock Low Pulse Width
2.4
2.4
tCH
____
____
____
(1)
3
tCL
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.5
3.8
4.2
ns
ns
ns
____
____
____
tCDC
1.5
0
1.5
0
1.5
0
(2)
CL Z
____
____
____
t
(2)
Clock High to Data High-Z
1.5
3.5
1.5
3.8
1.5
4.2
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
3.5
3.8
4.2
____
____
____
(2)
(2)
Output Enable Low to Output Active
Output Enable High to Output High-Z
0
0
0
t
OLZ
____
____
____
3.5
3.8
4.2
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
t
ZZPW
ZZ Pulse Width
100
100
24
100
100
27
100
100
30
ns
ns
(3)
ZZR
ZZ Recovery Time
Configuration Set-up Time
t
____
____
____
(4)
CFG
ns
t
5310 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42
12
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Pipelined Read Cycle(1,2)
,
6.42
13
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
,
6.42
14
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
,
6.42
15
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
,
6.42
16
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
,
6.42
17
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
0
CS
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5310 drw 14
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5310 drw 15
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
19
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
20
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
21
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
OrderingInformation
X
X
XXX
S
X
XX
Z
Device
Type
Power Speed
Package
Process/Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
G
Restricted hazardous substance device
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine Pitch Ball Grid Array
PF
BG
BQ
166*
150
133
,
Frequency in Megahertz
Blank
Z
First generation or current die step
Current generation die step optional
256K x 36 Pipelined Burst Synchronous SRAM
512K x 18 Pipelined Burst Synchronous SRAM
71V67603
71V67803
5310 drw 13
* Industrial temperature not available on 166MHz devices
6.42
22
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
12/31/99
Createddatasheetfrom71V676and71V678datasheets.
I/Ovoltage andspeedgrade offerings have beensplitintoseparate partnumbers.
Seethefollowingdatasheetsfor:
3.3VI/O, 133–166MHz
2.5VI/O, 133–166MHz
3.3VI/O, 183–200MHz
2.5VI/O, 183–200MHz
71V67603
71V67602
71V67613
71V67612
04/26/00
05/24/00
07/12/00
Pg. 4
AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsandRecommended
OperatingTemperaturetables.
Replace PinU6withTRST pininBGApinconfiguration;Addpindescriptionnote inpinout
Inserted100pinTQFPPackageDiagramOutline
Pg. 7
Pg. 18
Pg. 1,8,4,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 in BGA and TQFP pinouts
Pg. 20
Pg. 5,6
Pg. 7
Correctioninthe119BGAPackageDiagramOutline
RemovenotefromTQFPpinout
Add/RemovereferencenotefromBG119pinout
RemovenotefromBQ165pinout
Pg. 9
Pg. 20
Pg. 9
Pg. 1,2
Pg. 7,8
Pg. 9
UpdateBG119PackageDiagramOutlinedimensions
UpdatedISB2levels forF=133-166MHz
Remove 166MHz and JTAG pins
Updated pins U2-U6 to DNU and P5,P7,R5 & R7 to DNU
Remove 166MHz and raise range by 10mA on 150Mhz and 133MHz
12/18/00
10/29/01
Pg. 12,22 Remove166MHz
10/22/02
11/19/02
Pg.1-22
ChangeddatasheetfromAdvancedtofinalrelease.
Pg. 4,9,12, AddedItemptodatasheet.
22
Pg.1,9,12,22 Added166MHztodatasheet.
04/15 /03 Pg.4
Updated165fBGAtablefromTBDto7.
09/30/04
Pg.7
Updated 119BGA pin configurations-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Pg.22
Pg.22
Added"Restrictedhazardoussubstancedevice"toorderinginformation.
AddedZgenerationdiesteptoorderinginformation.
02/21/07
02/20/09 Pg. 22
Removed "IDT" from orderable part number.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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