IDT71V67803S133PFGI8

256K X 36, 512K X 18

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

IDT71V67603

IDT71V67803

PipelinedOutputs,SingleCycleDeselect

Features

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

theendofthewritecycle.

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

LBO input selects interleaved or linear burst mode

◆

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

◆

3.3V core power supply

◆

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-

pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165

fine pitchballgridarray(fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

PinDescriptionSummary

A⁰-A¹⁸

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CE

CS⁰, CS1

Chip Selects

Output Enable

OE

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

GW

BWE

(1)

BW¹, BW², BW³, BW4

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

DC

ADV

ADSC

ADSP

LBO

ZZ

Asynchronous

Synchronous

N/A

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

N/A

5310 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

SEPTEMBER 2004

1

DSC-5310/06

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁸

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

Address Status

I

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

ADSC

ADSP

ADV

(Cache Controller)

used to load the address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; thatis, there is no address advance.

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs BW¹-BW⁴. If BWE is LOW at the

BWE

rising edge of CLK then

x inputs are passed to the next stage in the circuit. If

BW

is

BWE

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

Individual Byte

Write Enables

I

LOW

N/A

Synchronous byte write enables. BW¹controls I/O^0-7, I/O^P1, BW²controls I/O^8-15, I/O^P2, etc.

Any active byte write causes all outputs to be disabled.

BW¹-BW4

CE

Chip Enable

Synchronous chip enable. CE is used with CS⁰and CS¹to enable the IDT71V67603/7803.

CE also gates ADSP.

CLK

Clock

This is the clock input. All timing references for the device are made with respect to this

input.

CS⁰

CS1

GW

Chip Select 0

Chip Select 1

I

HIGH

LOW

Synchronous active HIGH chip select. CS⁰is used with CE and CS¹to enable the chip.

Synchronous active LOW chip select. CS¹is used with CE and CS⁰to enable the chip.

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

I/O

I

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

LBO

Output Enable

I

LOW

Asynchronous output enable. When OE is LOW the data outputdrivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

OE

V^DD

V^DDQ

V^SS

NC

Power Supply

Ground

N/A

I

N/A

3.3V core power supply.

3.3V I/O Supply.

N/A

Ground.

No Connect

Sleep Mode

N/A

NC pins are not electrically connected to the device.

ZZ

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V67603/7803 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

5310 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

2

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

LBO

ADV

CEN

INTERNAL

ADDRESS

Burst

Sequence

256K x 36/

512K x 18-

BIT

MEMORY

ARRAY

CLK

2

Burst

Logic

18/19

Binary

Counter

ADSC

A0*

A1*

Q0

Q1

CLR

ADSP

2

CLK EN

A0,A1

A2–A18

A0–A17/18

G W

ADDRESS

REGISTER

36/18

18/19

Byte 1

Write Register

BW E

Byte 1

Write Driver

BW 1

BW 2

9

Byte 2

Write Register

Byte 2

Write Driver

Byte 3

Write Register

Byte 3

Write Driver

BW 3

BW 4

9

Byte 4

Write Register

Byte 4

Write Driver

OUTPUT

REGISTER

CE

CS₀

CS1

Q

D

Enable

DATA INPUT

REGISTER

Register

CLK EN

ZZ

Powerdown

D

Q

Enable

Delay

Register

OE

OUTPUT

BUFFER

OE

,

36/18

I/O0–I/O31

I/OP1–I/OP4

5301 drw 01

6.42

3

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Symbol

Rating

Commercial

Unit

Grade

Temperature⁽¹⁾

0°C to +70°C

-40°C to +85°C

V^SS

0V

V^DD

V^DDQ

(2)

V^TERM

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

Commercial

Industrial

3.3V±5%

(3,6)

V^TERM

Terminal Voltage with

Respect to GND

-0.5 to V^DD

-0.5 to V^DD+0.5

-0.5 to V^DDQ+0.5

-0 to +70

V

3.3V±5%

5310 tbl 04

NOTE:

1. TA is the "instant on" case temperature.

(4,6)

V^TERM

Terminal Voltage with

Respect to GND

RecommendedDCOperating

Conditions

(5,6)

V^TERM

Terminal Voltage with

Respect to GND

V

Symbol

V^DD

V^DDQ

V^SS

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min. Typ.

3.135 3.3

Max.

3.465

0

Unit

V

^oC

W

(7)

T^A

Operating Temperature

Temperature

Under Bias

-55 to +125

T^BIAS

V

0

V

Storage

Temperature

-55 to +125

T^STG

____

V^IH

Input High Voltage - Inputs

Input High Voltage -I/O

Input Low Voltage

2.0

V^DD+0.3

V^DDQ+0.3

0.8

V

____

V^IH

P^T

Power Dissipation

DC Output Current

2.0

50

(1)

V^IL

-0.3

V

I^OUT

mA

5310 tbl 05

5310 tbl 03

NOTES:

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed VDDQ during power supply ramp up.

7. TA is the "instant on" case temperature.

165fBGACapacitance

(TA = +25°C, f = 1.0MHz)

100PinTQFPCapacitance

(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

VOUT = 3dV

Max. Unit

Symbol

CIN

5

7

pF

7

pF

CI/O

pF

CI/O

pF

5310 tbl 07

5310 tbl 07b

119BGACapacitance

(TA = +25°C, f = 1.0MHz)

Symbol

C^IN

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

V^IN= 3dV

V^OUT= 3dV

Max. Unit

7

pF

C^I/O

pF

5310 tbl 07a

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

6.42

4

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 36, 100-Pin TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

I/OP3

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

2

3

4

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

I/O22

I/O23

VDDQ

69

68

67

66

I/O9

I/O8

VSS

NC

VDD

ZZ⁽²⁾

I/O7

I/O6

VDDQ

VSS

I/O5

I/O4

I/O3

I/O2

VSS

VDDQ

I/O1

I/O0

I/OP1

VDD / NC⁽¹⁾

VDD

65

64

NC

VSS

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

VDDQ

I/O30

I/O31

I/OP4

63

62

61

60

59

58

57

56

55

54

53

,

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5301 drw 02

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 512K x 18, 100-Pin TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

NC

VDDQ

VSS

NC

I/O8

I/O9

VSS

A10

NC

2

79

78

77

3

4

VDDQ

VSS

NC

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

NC

VDD

ZZ⁽²⁾

I/O3

I/O2

VDDQ

VSS

I/O1

I/O0

NC

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

VDDQ

I/O10

I/O11

VDD / NC⁽¹⁾

VDD

69

68

67

66

65

64

NC

VSS

63

62

I/O12

I/O13

VDDQ

VSS

I/O14

I/O15

I/OP2

NC

VSS

VDDQ

NC

61

60

59

58

57

56

55

54

53

NC

VSS

VDDQ

NC

,

52

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5310 drw 03

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

6

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 36, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

V

A

ADSP

ADSC

(4)

A17

3

2

9

A

NC

CS

NC

0

7

A

DD

V

12

A

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

CE

V

17

I/O

18

I/O

13

I/O

14

I/O

DDQ

V

19

I/O

12

I/O

DDQ

V

OE

20

21

11

10

I/O

G

H

J

2

3

BW

ADV

GW

BW

22

I/O

23

I/O

SS

V

9

I/O

8

I/O

V

DDQ

DD

V

DD

DDQ

V

NC

V

24

26

SS

4

SS

6

7

K

L

I/O

V

CLK

NC

V

I/O

25

I/O

27

I/O

4

I/O

5

I/O

1

BW

DDQ

28

SS

3

DDQ

M

N

P

R

T

V

I/O

V

I/O

V

BWE

29

I/O

30

P4

SS

1

A

2

I/O

1

I/O

0

I/O

31

0

A

P1

I/O

NC

I/O

(1)

NC

5

DD

V

13

A

VDD / NC

A

LBO

(2)

10

A

11

A

14

A

,

NC

ZZ

DNU⁽³⁾

DDQ

V

U

DNU⁽³⁾

DDQ

V

5310 drw 04

Top View

Pin Configuration 512K x 18, 119 BGA

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

(4)

3

2

9

A18

17

NC

CS

NC

0

7

DD

V

13

A

8

SS

P1

I/O

NC

V

NC

V

9

I/O

7

I/O

NC

CE

OE

DDQ

V

6

I/O

DDQ

V

NC

10

I/O

5

I/O

G

H

J

NC

BW2

SS

ADV

GW

11

I/O

SS

4

I/O

NC

V

NC

DDQ

V

DD

V

DD

DDQ

V

NC

V

NC

12

SS

3

NC

I/O

V

CLK

NC

V

NC

I/O

K

L

13

I/O

SS

2

I/O

NC

V

NC

1

BW

DDQ

V

14

I/O

SS

DDQ

V

M

N

P

R

T

V

NC

BWE

15

1

A

1

I/O

NC

P2

0

A

0

I/O

NC

(1)

5

DD

V

12

11

NC

DDQ

A

VDD / NC

14

A

NC

LBO

(2)

,

10

15

A

NC

A

ZZ

DNU⁽³⁾

DDQ

V

5310 drw 05

DNU⁽³⁾

V

DNU⁽³⁾

U

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. T7 can be left unconnected and the device will always remain in active mode.

3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

4. On future 18M device CS₀will be removed, B2 will be used for address expansion.

6.42

7

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Pin Configuration 256K x 36, 165 fBGA

1

2

3

4

5

6

7

8

9

10

11

(3)

A

B

C

D

E

F

NC

A

NC

7

8

CE

BW

CS

1

BWE

GW

ADSC

OE

ADV

ADSP

3

2

(3)

A

6

CS

CLK

A

9

NC

I/O

0

BW

1

4

I/O

NC

I/O

V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

NC

I/O

P3

P2

I/O

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

14

17

16

15

I/O

18

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

13

I/O

12

19

I/O

21

I/O

20

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

10

11

G

H

J

I/O

V

I/O

8

23

22

DDQ

DD

SS

DD

DDQ

9

(1)

(2)

V

DD

NC

I/O

NC

V

DD

V

SS

V

SS

V

SS

V

DD

NC

I/O

ZZ

I/O

25

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

6

24

7

K

L

M

N

P

I/O

V

I/O

4

27

26

DDQ

DD

SS

DD

DDQ

5

I/O

29

I/O

28

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

3

I/O2

I/O

31

I/O

30

V

DDQ

V

DD

V

SS

V

SS

V

SS

V

DD

V

DDQ

I/O

1

0

(3)

I/O

P4

NC

V

DDQ

V

SS

NC

V

SS

V

DDQ

NC

I/O

P1

(3)

(4)

NC

LBO

NC

A

DNU

A

DNU

A

10

A

14

A

17

5

2

1

13

(3)

(4)

R

NC

A

DNU

A

DNU

A

15

A

16

4

3

0

11

12

5310 tbl 17a

Pin Configuration 512K x 18, 165 fBGA

1

2

3

4

5

6

7

BWE

8

9

10

A8

11

(3)

A

B

C

D

E

F

NC

A7

NC

A10

CE

BW2

NC

CS1

CLK

VSS

ADSC

OE

ADV

(3)

A6

CS0

A9

NC

BW1

VSS

GW

VSS

ADSP

VDDQ

NC

I/O8

I/O9

VDDQ

VSS

VDD

VSS

VDD

NC

I/O3

I/O2

I/O1

I/O0

NC

A15

A16

I/OP1

I/O7

I/O⁶

I/O

10

V

DD

V

SS

V

SS

V

SS

V

DD

V

I/O

5

DDQ

G

H

J

I/O

VDDQ

NC

VDD

VSS

A2

VSS

NC

VSS

NC

VDD

VSS

A11

VDDQ

NC

I/O4

11

(1)

(2)

VDD

I/O12

I/O13

I/O14

I/O15

I/OP2

NC

ZZ

VDDQ

A5

VDDQ

A14

NC

A18

K

L

M

N

P

(3)

NC

A1

A0

(3)

(4)

NC

DNU

(3)

(4)

R

NC

A4

A3

DNU

A12

A13

A17

LBO

5310 tbl 17b

NOTES:

1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. H11 can be left unconnected and the device will always remain in active mode.

3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.

4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.

6.42

8

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

V^DD= Max., V^IN= 0V to V^DD

5

µA

(1 )

___

ZZ and LBO Input Leakage Current

Output Leakage Current

Output Low Voltage

|I^LZZ|

|I^LO|

V^OL

V^OH

V^DD= Max., V^IN= 0V to V^DD

V^OUT= 0V to V^DDQ, Device Deselected

I^OL= +8mA, V^DD= Min.

30

5

µA

V

0.4

___

Output High Voltage

I^OH= -8mA, V^DD= Min.

2.4

V

5310 tbl 08

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating

TemperatureandSupplyVoltageRange⁽¹⁾

166MHz

150MHz

Com'l

133MHz

Com'l

Unit

Symbol

IDD

Parameter

Test Conditions

Com'l only

Ind

Operating Power Supply

Current

Device Selected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VIH or < VIL, f = fMAX

mA

340

50

305

50

325

260

50

280

(2)

ISB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = 0^(2,3)

70

175

70

170

70

ISB2

IZZ

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = fMAX

160

50

155

50

150

50

(2,3)

ZZ > VHD, VDD = Max.

Full Sleep Mode Supply

Current

mA

5310 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

VDDQ/2

AC Test Conditions

(VDDQ = 3.3V)

AC Test Load

50Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

,

5310 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

6

5

4

1.5V

See Figure 1

5310 tbl 10

3

∆tCD

(Typical, ns)

2

1

20 30 50

80 100

Capacitance (pF)

200

5310 drw 07

,

Figure 2. Lumped Capacitive Load, Typical Derating

6.42

9

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

SynchronousTruthTable^(1,3)

Operation

Address

CS0

CLK

I/O

CE

CS1 ADSP ADSC ADV

GW BWE BWx

OE

(2)

Used

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

H

L

X

L

X

H

X

H

X

L

X

L

X

L

X

L

X

H

L

X

H

L

X

H

L

X

L

-

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

None

L

None

L

X

L

X

L

None

L

External

H

X

L

Read Cycle, Begin Burst

L

H

L

Read Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

Read Cycle, Begin Burst

L

Read Cycle, Begin Burst

L

H

X

L

Write Cycle, Begin Burst

L

Write Cycle, Begin Burst

L

X

H

X

H

X

L

X

H

X

H

L

DIN

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

L

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

H

L

H

L

H

L

H

X

L

X

L

X

L

DIN

H

L

DIN

X

H

X

H

X

L

X

H

X

H

L

DIN

Current

H

L

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

H

L

H

L

H

L

H

X

L

X

L

DIN

H

L

DIN

X

DIN

5310 tbl 11

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

10

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Synchronous Write Function Truth Table^{(1, 2)}

Operation

GW

H

L

BWE

H

L

BW1

BW2

X

BW3

X

BW4

X

Read

X

Read

H

Write all Bytes

X

L

X

H

L

(3)

Write Byte 1

L

H

(3)

Write Byte 2

L

H

L

H

(3)

Write Byte 3

L

H

L

H

(3)

Write Byte 4

L

H

L

5310 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. BW³and BW4 are not applicable for the IDT71V67803.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

ZZ

I/O Status

Power

OE

Read

L

H

X

L

H

Data Out

High-Z

Active

Write

High-Z – Data In

High-Z

Active

Deselected

Sleep Mode

Standby

Sleep

High-Z

5310 tbl 13

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

0

A1

A0

First Address

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5310 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

0

A0

0

A1

0

A0

1

A1

1

A0

0

A1

1

A0

First Address

1

Second Address

Third Address

0

1

0

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5310 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.42

11

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)

166MHz

150MHz

133MHz

Max.

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Unit

____

t^CYC

Clock Cycle Time

6

6.7

2.6

7.5

3

ns

(1)

Clock High Pulse Width

Clock Low Pulse Width

2.4

t^CH

____

(1)

3

t^CL

Output Parameters

____

t^CD

Clock High to Valid Data

3.5

3.8

4.2

ns

____

t^CDC

Clock High to Data Change

1.5

0

1.5

0

1.5

0

____

(2)

Clock High to Output Active

Clock High to Data High-Z

t^{CL Z}

(2)

1.5

3.5

1.5

3.8

1.5

4.2

ns

t^CHZ

____

t^OE

Output Enable Access Time

Output Enable Low to Output Active

Output Enable High to Output High-Z

3.5

3.8

4.2

____

(2)

0

t^OLZ

____

(2)

3.5

3.8

4.2

t^OHZ

Set Up Times

____

t^SA

t^SS

Address Setup Time

1.5

ns

Address Status Setup Time

Data In Setup Time

t^SD

t^SW

t^SAV

t^SC

Write Setup Time

Address Advance Setup Time

Chip Enable/Select Setup Time

Hold Times

____

t^HA

t^HS

Address Hold Time

0.5

ns

Address Status Hold Time

Data In Hold Time

t^HD

t^HW

t^HAV

t^HC

Write Hold Time

Address Advance Hold Time

Chip Enable/Select Hold Time

Sleep Mode and Configuration Parameters

____

t^ZZPW

ZZ Pulse Width

100

24

100

27

100

30

ns

(3)

ZZ Recovery Time

Configuration Set-up Time

t^ZZR

____

(4)

ns

t^CFG

5310 tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

6.42

12

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Pipelined Read Cycle^(1,2)

,

6.42

13

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles^(1,2,3)

,

6.42

14

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 GW Controlled^(1,2,3)

,

6.42

15

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 Byte Controlled^(1,2,3)

,

6.42

16

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes^(1,2,3)

,

6.42

17

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW, BWE, BWx

CE, CS1

CS0

OE

(Av)

(Aw)

(Ax)

(Ay)

DATAOUT

,

5310 drw 14

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW

CE, CS¹

CS⁰

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATA_IN

,

5310 drw 15

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.42

18

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline

6.42

19

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

119 Ball Grid Array (BGA) Package Diagram Outline

6.42

20

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline

6.42

21

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

OrderingInformation

X

IDT

XXX

S

X

XX

Device

Type

Power

Spe ed

Package

P roce ss/Temperature Range

Commercia l (0°C to +70°C)

Industria l (-40°C to +85°C)

Blank

I

G

Re stricted ha za rdous substa nce device

100-pin Pla stic Thin Quad Flatpack (TQFP)

119 Ball Grid Arra y (BGA)

P F

BG

BQ

165 fine Pitch Ball Grid Array

166*

150

,

Frequency in Megahertz

133

256K x 36 Pipelined Burst Synchronous SRAM

512K x 18 Pipelined Burst Synchronous SRAM

71V67603

71V67803

5310 drw 13

* Industria l tempera ture not a va ilable on 166MHz devices

6.42

22

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

DatasheetDocumentHistory

12/31/99

Createddatasheetfrom71V676and71V678datasheets.

I/Ovoltage andspeedgrade offerings have beensplitintoseparate partnumbers.

Seethefollowingdatasheetsfor:

3.3VI/O, 133–166MHz

2.5VI/O, 133–166MHz

3.3VI/O, 183–200MHz

2.5VI/O, 183–200MHz

71V67603

71V67602

71V67613

71V67612

04/26/00

05/24/00

07/12/00

Pg. 4

AddcapacitanceforBGApackage;InsertclarificationnotetoAbsoluteMaxRatingsandRecommended

OperatingTemperaturetables.

Replace PinU6withTRST pininBGApinconfiguration;Addpindescriptionnote inpinout

Inserted100pinTQFPPackageDiagramOutline

Pg. 7

Pg. 18

Pg. 1,8,4,21 Add new package offering, 13 x 15 fBGA

22

Pg. 5,6,7,8 Correct note 2 in BGA and TQFP pinouts

Pg. 20

Pg. 5,6

Pg. 7

Correctioninthe119BGAPackageDiagramOutline

RemovenotefromTQFPpinout

Add/RemovereferencenotefromBG119pinout

RemovenotefromBQ165pinout

Pg. 9

Pg. 20

Pg. 9

Pg. 1,2

Pg. 7,8

Pg. 9

UpdateBG119PackageDiagramOutlinedimensions

UpdatedISB2levels forF=133-166MHz

Remove 166MHz and JTAG pins

Updated pins U2-U6 to DNU and P5,P7,R5 & R7 to DNU

Remove 166MHz and raise range by 10mA on 150Mhz and 133MHz

12/18/00

10/29/01

Pg. 12,22 Remove166MHz

10/22/02

11/19/02

Pg.1-22

ChangeddatasheetfromAdvancedtofinalrelease.

Pg. 4,9,12, AddedItemptodatasheet.

22

Pg.1,9,12,22 Added166MHztodatasheet.

04/15 /03 Pg.4

Updated165fBGAtablefromTBDto7.

09/30/04

Pg.7

Updated 119BGA pin configurations-reordered I/O signals on P6, P7 (128K x 36)

and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).

Pg.22

Added"Restrictedhazardoussubstancedevice"toorderinginformation.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

23


型号：	IDT71V67803S133PFGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Cache SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟静态存储器内存集成电路
文件：	总23页 (文件大小：983K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V67803S133PFGI8 [IDT]

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