IDT7201LA20DG_技术文档

IDT7200L

IDT7201LA

IDT7202LA

CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9, 1K x 9

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

•

First-In/First-Out dual-port memory

256 x 9 organization (IDT7200)

512 x 9 organization (IDT7201)

1K x 9 organization (IDT7202)

The IDT7200/7201/7202 are dual-port memories that load

and empty data on a first-in/first-out basis. The devices use

Full and Empty flags to prevent data overflow and underflow

andexpansionlogictoallowforunlimitedexpansioncapability

in both word size and depth.

Low power consumption

— Active: 770mW (max.)

—Power-down: 2.75mW (max.)

Ultra high speed—12ns access time

Asynchronous and simultaneous read and write

Fully expandable by both word depth and/or bit width

Pin and functionally compatible with 720X family

Status Flags: Empty, Half-Full, Full

The reads and writes are internally sequential through the

use of ring pointers, with no address information required to

loadandunloaddata. Dataistoggledinandoutofthedevices

through the use of the Write (W) and Read (R) pins.

The devices utilizes a 9-bit wide data array to allow for

control and parity bits at the user’s option. This feature is

especially useful in data communications applications where

it is necessary to use a parity bit for transmission/reception

error checking. It also features a Retransmit (RT) capability

that allows for reset of the read pointer to its initial position

when RT is pulsed low to allow for retransmission from the

beginning of data. A Half-Full Flag is available in the single

device mode and width expansion modes.

The IDT7200/7201/7202 are fabricated using IDT’s high-

speed CMOS technology. They are designed for those

applications requiring asynchronous and simultaneous read/

writes in multiprocessing and rate buffer applications. Military

grade product is manufactured in compliance with the latest

revision of MIL-STD-883, Class B.

•

Auto-retransmit capability

High-performance CEMOS technology

Military product compliant to MIL-STD-883, Class B

Standard Military Drawing #5962-87531, 5962-89666,

5962-89863 and 5962-89536 are listed on this function

Industrial temperature range (-40oC to +85oC) is

available, tested to military electrical specifications

•

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D0–D8)

WRITE

W

CONTROL

WRITE

POINTER

RAM

READ

POINTER

ARRAY

256 x 9

512 x 9

1024 x 9

THREE-

STATE

BUFFERS

RS

DATA OUTPUTS

(Q0–Q8)

READ

R

RESET

LOGIC

CONTROL

FLAG

LOGIC

EF

FF

FL/RT

EXPANSION

LOGIC

XO/HF

XI

2679 drw 01

The IDT logo is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1996 Integrated Device Technology, Inc.

DSC-2679/7

5.03

1

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

W

D8

1

28

VCC

D4

4

3

2

32 31 30

1

2

27

D

2

5

29

28

27

26

25

24

23

22

21

D6

D3

3

26

25

D5

D1

6

D7

D2

4

D6

D0

7

NC

FL RT

D1

5

P28-1, 24

D7

XI

8

J32-1

&

L32-1

/

P28-2,

D0

6

23

FL/RT

RS

EF

D28-1,

FF

9

RS

EF

XI

7

D28-3, 22

Q

0

1

10

11

12

13

E28-2,

SO28-3

FF

8

21

XO/HF

Q0

Q1

Q2

Q3

Q8

GND

9

20

19

18

17

16

15

XO/HF

Q7

NC

Q

7

6

10

11

12

13

14

Q

2

Q6

14 15 16 17 18 19 20

Q5

Q4

R

2679 drw 02b

2679 drw 02a

LCC/PLCC

TOP VIEW

DIP/SOIC/CERPACK

TOP VIEW

NOTE:

1. CERPACK(E28-2)and600-mil-wideDIP(P28-1andD28-1)notavailable 1. LCC (L32-1) not available for 7200.

for 7200.

RECOMMENDED DC OPERATING

CONDITIONS

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Symbol

Rating

Com’l.

Mil.

Unit

Symbol

Parameter

Min.

Typ. Max. Unit

VTERM

Terminal Voltage

with Respect

to GND

–0.5 to +7.0 –0.5 to +7.0

V

CCM

Military Supply

Voltage

4.5

5.0

5.5

V

VCCC

Commercial Supply

Voltage

4.5

5.0

5.5

V

TA

Operating

Temperature

0 to +70

–55 to +125 °C

GND

Supply Voltage

0

V

TBIAS

TSTG

IOUT

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +155 °C

(1)

V

IH

Input High Voltage

Commercial

2.0

—

Storage

Temperature

(1)

IH

Input High Voltage

Mlitary

2.2

—

V

DC Output

Current

50

mA

(2)

IL

Input Low Voltage

Commercial and

Military

0.8

NOTE:

2679 tbl 01

1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliabilty.

NOTE:

2679 tbl 03

1. VIH = 2.6V for XI input (commercial).

VIH = 2.8V for XI input (military).

2. 1.5V undershoots are allowed for 10ns once per cycle.

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

Symbol

CIN

Parameter⁽¹⁾

Condition

VIN = 0V

Max. Unit

Input Capacitance

Output Capacitance

8

pF

COUT

VOUT = 0V

NOTE:

2679 tbl 02

1. This parameter is sampled and not 100% tested.

5.03

2

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

IDT7200L

IDT7201LA

IDT7202LA

IDT7200L

IDT7201LA

IDT7202LA

Military

IDT7200L

IDT7201LA

IDT7202LA

Commercial

tA = 25, 35 ns

Commercial

tA = 12, 15, 20 ns

tA = 20 ns

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

(1)

ILI

Input Leakage Current (Any Input)

Output Leakage Current

–1

–10

2.4

—

1

10

–10

2.4

—

10

–1

–10

2.4

—

1

µA

V

(2)

ILO

10

—

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

125⁽⁴⁾

15

0.4

140⁽⁴⁾

20

0.4

125⁽⁴⁾mA

V

(3)

ICC1

—

(3)

ICC2

Standby Current (R=W=RS=FL/RT=VIH)

—

15

mA

ICC3(L)⁽³⁾Power Down Current (All Input = VCC - 0.2V)

—

0.5

—

0.9

—

0.5

NOTES:

2679 tbl 05

4

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. ICC measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

DC ELECTRICAL CHARACTERISTICS (Continued)

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

IDT7200L

IDT7201LA

IDT7202LA

Military

IDT7200L

IDT7201LA

IDT7202LA

Commercial

tA = 50 ns

IDT7200L

IDT7201LA

IDT7202LA

Military

tA = 30, 40 ns

tA = 50, 65, 80, 120 ns

Symbol

Parameter

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

(1)

ILI

Input Leakage Current (Any Input)

Output Leakage Current

–10

2.4

—

10

–1

–10

2.4

—

50

5

1

10

—

0.4

80

8

–10

2.4

—

70

8

10

—

µA

V

(2)

ILO

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

140⁽⁴⁾

20

0.4

V

(3)

ICC1

—

100 mA

(3)

ICC2

Standby Current (R=W=RS=FL/RT=VIH)

—

15

mA

ICC3(L)⁽³⁾Power Down Current (All Input = VCC - 0.2V)

—

0.9

—

0.5

—

0.9

NOTES:

2679 tbl 05

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. ICC measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.03

3

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS⁽¹⁾

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

Commercial

Com'l & Mil. Com'l

Military

Com'l

7200L12 7200L15

7200L20 7200L25

7200L30

7200L35

7201LA12 7201LA15 7201LA20 7201LA25 7201LA30 7201LA35

7202LA12 7202LA15 7202LA20 7202LA25 7202LA30 7202LA35

Symbol Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tS

Shift Frequency

—

20

—

8

50

—

12

—

12

—

12

17

20

12

14

—

12

14

17

—

12

—

25

—

10

15

5

40

—

15

—

15

—

25

15

—

15

25

—

15

—

30

—

10

20

5

33.3

—

20

—

15

—

30

20

—

20

30

—

20

—

35

—

10

25

5

28.5

—

25

—

18

—

35

25

—

25

35

—

25

—

40

—

10

30

5

25

—

30

—

20

—

40

30

—

30

40

—

30

—

45

—

10

35

5

22.2 MHz

tRC

Read Cycle Time

—

35

—

20

—

45

30

—

30

45

—

35

—

ns

2679 tbl 06

tA

Access Time

tRR

Read Recovery Time

Read Pulse Width⁽²⁾

tRPW

tRLZ

tWLZ

tDV

12

3

Read Pulse Low to Data Bus at Low Z⁽³⁾

Write Pulse High to Data Bus at Low Z^{(3, 4)}

Data Valid from Read Pulse High

Read Pulse High to Data Bus at High Z⁽³⁾

Write Cycle Time

3

5

10

5

tRHZ

tWC

tWPW

tWR

tDS

—

20

12

8

—

25

15

10

11

0

—

30

20

10

12

0

—

35

25

10

15

0

—

40

30

10

18

0

—

45

35

10

18

0

Write Pulse Width⁽²⁾

Write Recovery Time

Data Set-up Time

9

tDH

Data Hold Time

0

tRSC

tRS

Reset Cycle Time

Reset Pulse Width⁽²⁾

Reset Set-up Time⁽³⁾

20

12

8

25

15

10

25

15

10

—

15

—

15

—

15

10

30

20

10

30

20

10

—

20

—

20

—

20

10

35

25

10

35

25

10

—

25

—

25

—

25

10

40

30

10

40

30

10

—

30

—

30

—

30

10

45

35

10

45

35

10

—

35

—

35

—

35

10

tRSS

tRSR

tRTC

tRT

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width⁽²⁾

Retransmit Set-up Time⁽³⁾

Retransmit Recovery Time

Reset to Empty Flag Low

20

12

8

tRTS

tRTR

tEFL

—

12

—

12

—

12

8

tHFH,FFH Reset to Half-Full and Full Flag High

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

Retransmit Low to Flags Valid

Read Low to Empty Flag Low

Read High to Full Flag High

Read Pulse Width after EF High

Write High to Empty Flag High

Write Low to Full Flag Low

Write Low to Half-Full Flag Low

Read High to Half-Full Flag High

Write Pulse Width after FF High

Read/Write to XO Low

Read/Write to XO High

XI Pulse Width⁽²⁾

tXIR

XI Recovery Time

tXIS

XI Set-up Time

8

NOTES:

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum value are not allowed.

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

5.03

4

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS⁽¹⁾(Continued)

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

Military

Com'l & Mil.

Military⁽²⁾

7200 L40

7201LA40

7202LA40

7200L50

7201LA50

7202LA50

7200L65

7201LA65

7202LA65

7200L80

7201LA80

7202LA80

7200L120

7201LA120

7202LA120

Symbol

tS

Parameter

Shift Frequency

Min.

—

Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

20

—

40

—

25

—

50

30

35

—

35

50

—

40

—

65

—

15

50

10

15

5

15

—

50

—

30

—

65

45

—

45

65

—

50

—

80

—

15

65

10

15

5

12.5

—

65

—

30

—

80

60

—

60

80

—

65

—

100

—

10

—

140

—

7

—

MHz

ns

tRC

Read Cycle Time

50

—

tA

Access Time

80

—

120

—

ns

tRR

Read Recovery Time

Read Pulse Width⁽³⁾

Read Pulse Low to Data Bus at Low Z⁽⁴⁾

10

40

5

20

80

10

20

5

20

ns

tRPW

tRLZ

tWLZ

tDV

—

120

10

—

ns

—

ns

Write Pulse High to Data Bus at Low Z^{(4, 5)}10

—

20

—

ns

Data Valid from Read Pulse High

Read Pulse High to Data Bus at High Z⁽⁴⁾

Write Cycle Time

5

—

5

—

ns

tRHZ

tWC

tWPW

tWR

tDS

—

50

40

10

20

0

—

65

50

15

30

5

—

80

65

15

30

10

80

65

15

80

65

15

—

65

—

65

—

65

10

15

—

30

—

35

—

ns

100

80

20

40

10

100

80

20

100

80

20

—

140

120

20

ns

Write Pulse Width⁽³⁾

—

ns

Write Recovery Time

—

ns

Data Set-up Time

—

40

—

ns

tDH

Data Hold Time

—

10

—

ns

tRSC

tRS

Reset Cycle Time

Reset Pulse Width⁽³⁾

Reset Set-up Time⁽⁴⁾

50

40

10

50

40

10

—

40

—

40

—

40

10

65

50

15

65

50

15

—

50

—

50

—

50

10

15

—

140

120

20

—

ns

—

ns

tRSS

tRSR

tRTC

tRT

—

ns

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width⁽³⁾

Retransmit Set-up Time⁽⁴⁾

Retransmit Recovery Time

Reset to Empty Flag Low

—

ns

—

140

120

20

—

ns

—

ns

tRTS

tRTR

tEFL

—

ns

—

ns

100

60

—

140

60

—

ns

tHFH,FFH Reset to Half-Full and Full Flag High

—

ns

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

Retransmit Low to Flags Valid

Read Low to Empty Flag Low

Read High to Full Flag High

Read Pulse Width after EF High

Write High to Empty Flag High

Write Low to Full Flag Low

Write Low to Half-Full Flag Low

Read High to Half-Full Flag High

Write Pulse Width after FF High

Read/Write to XO Low

—

ns

—

ns

—

ns

80

—

120

—

ns

60

100

—

60

140

—

ns

—

ns

—

ns

—

ns

80

—

120

—

ns

80

—

120

—

ns

Read/Write to XO High

XI Pulse Width⁽³⁾

—

ns

80

10

15

120

10

ns

tXIR

XI Recovery Time

—

ns

tXIS

XI Set-up Time

—

15

—

ns

NOTES:

2679 tbl 07

1. Timings referenced as in AC Test Conditions

2. Speed grades 65, 80 and 120 not available in the CERPACK

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

5.03

5

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

5V

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

5ns

1.5V

1.1K

TO

OUTPUT

1.5V

See Figure 1

30pF*

680Ω

2679 tbl 08

2679 drw 03

or equivalent circuit

Figure 1. Output Load

* Includes scope and jig capacitances.

the Data Outputs (Q0 – Q8) will return to a high impedance

condition until the next Read operation. When all data has

been read from the FIFO, the Empty Flag (EF) will go low,

allowing the “final” read cycle but inhibiting further read

operations with the data outputs remaining in a high imped-

ance state. Once a valid write operation has been accom-

plished, the Empty Flag (EF) will go high after tWEF and a valid

Read can then begin. When the FIFO is empty, the internal

readpointerisblockedfromRsoexternalchangesinRwillnot

affect the FIFO when it is empty.

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

)

RS

Reset is accomplished whenever the Reset (RS) input is

taken to a low state. During reset, both internal read and write

pointers are set to the first location. A reset is required after

power up before a write operation can take place. Both the

FIRST LOAD/RETRANSMIT (

/

)

FL RT

Thisisadual-purposeinput. IntheDepthExpansionMode,

this pin is grounded to indicate that it is the first loaded (see

OperatingModes). IntheSingleDeviceMode, thispinactsas

the restransmit input. The Single Device Mode is initiated by

grounding the Expansion In (XI).

The IDT7200/7201A/7202A can be made to retransmit

data when the Retransmit Enable control (RT) input is pulsed

low. A retransmit operation will set the internal read pointer to

the first location and will not affect the write pointer. Read

Enable (R) and Write Enable (W) must be in the high state

during retransmit. This feature is useful when less than 256/

512/1024 writes are performed between resets. The retrans-

mit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), depending on the

relative locations of the read and write pointers.

Read Enable ( ) and Write Enable ( ) inputs must be in

R

W

the high state during the window shown in Figure 2, (i.e.,

tRSS before the rising edge of ) and should not change

RS

until tRSR after the rising edge of

. Half-Full Flag (

RS

)

HF

will be reset to high after Reset ( ).

RS

WRITE ENABLE ( )

W

A write cycle is initiated on the falling edge of this input if the

Full Flag (FF) is not set. Data set-up and hold times must be

adhered to with respect to the rising edge of the Write Enable

(W). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of

the next write operation, the Half-Full Flag (HF) will be set to

low and will remain set until the difference between the write

pointer and read pointer is less than or equal to one half of the

total memory of the device. The Half-Full Flag (HF) is then

reset by the rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go low,

inhibiting further write operations. Upon the completion of a

valid read operation, the Full Flag (FF) will go high after tRFF,

allowing a valid write to begin. When the FIFO is full, the

internal write pointer is blocked from W, so external changes

in W will not affect the FIFO when it is full.

EXPANSION IN ( )

XI

This input is a dual-purpose pin. Expansion In (XI) is

grounded to indicate an operation in the single device mode.

Expansion In (XI) is connected to Expansion Out (XO) of the

previousdeviceintheDepthExpansionorDaisyChainMode.

OUTPUTS:

FULL FLAG (

)

FF

The Full Flag (FF) will go low, inhibiting further write

operation, when the write pointer is one location less than the

read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full-Flag (FF) will go

low after 256 writes for IDT7200, 512 writes for the IDT7201A

and 1024 writes for the IDT7202A.

READ ENABLE ( )

R

A read cycle is initiated on the falling edge of the Read

Enable (R) provided the Empty Flag (EF) is not set. The data

is accessed on a First-In/First-Out basis, independent of any

ongoing write operations. After Read Enable (R) goes high,

5.03

6

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

EMPTY FLAG (

)

EF

pointer and read pointer is less than or equal to one half of the

The Empty Flag (EF) will go low, inhibiting further read total memory of the device. The Half-Full Flag (HF) is then

operations, when the read pointer is equal to the write pointer, reset by using rising edge of the read operation.

indicating that the device is empty.

In the Depth Expansion Mode, Expansion In (XI) is con-

nected to Expansion Out (XO) of the previous device. This

output acts as a signal to the next device in the Daisy Chain

EXPANSION OUT/HALF-FULL FLAG (

/

)

XO HF

This is a dual-purpose output. In the single device mode, by providing a pulse to the next device when the previous

when Expansion In (XI) is grounded, this output acts as an device reaches the last location of memory.

indication of a half-full memory.

After half of the memory is filled and at the falling edge of DATA OUTPUTS (Q0 – Q8)

the next write operation, the Half-Full Flag (HF) will be set low

Data outputs for 9-bit wide data. This data is in a high

and will remain set until the difference between the write impedance condition whenever Read (R) is in a high state.

t RSC

tRS

RS

tRSS

tRSR

W

R

t RSS

t EFL

EF

t HFH, tFFH

HF, FF

2679 drw 04

Figure 2. Reset

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = V^IHaround the rising edge of RS.

t

RC

tRPW

t

RR

t

A

t A

R

t

RLZ

t

DV

t RHZ

Q

0

– Q8

DATA OUT VALID

t

WC

t

WPW

tWR

W

t

DS

tDH

D0 – D8

DATA IN VALID

2679 drw 05

Figure 3. Asynchronous Write and Read Operation

5.03

7

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LAST WRITE

IGNORED

WRITE

FIRST READ

ADDITIONAL

READS

FIRST

WRITE

R

W

tWFF

tRFF

FF

2679 drw 06

Figure 4. Full Flag From Last Write to First Read

LAST READ

IGNORED

READ

FIRST WRITE

ADDITIONAL

WRITES

FIRST

READ

W

R

tREF

t A

tWEF

EF

DATA OUT

VALID

2679 drw 07

Figure 5. Empty Flag From Last Read to First Write

t RTC

t RT

RT

t

RTS

tRTR

W,R

RTF

HF, EF, FF

FLAG VALID

2679 drw 08

Figure 6. Retransmit

5.03

8

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

W

EF

R

t WEF

t RPE

2679 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

R

FF

W

t RFF

t _WPF

2679 drw 10

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse

W

R

t _RHF

HALF-FULL OR LESS

t _WHF

MORE THAN HALF-FULL

2678 drw 11

HF

HALF-FULL OR LESS

Figure 9. Half-Full Flag Timing

WRITE TO

LAST PHYSICAL

LOCATION

READ FROM

LAST PHYSICAL

LOCATION

W

R

t

XOH

t

XOL

t

XOL

t XOH

XO

2679 drw 12

Figure 10. Expansion Out

5.03

9

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t XI

t XIR

XI

t XIS

WRITE TO

FIRST PHYSICAL

LOCATION

W

R

t XIS

READ FROM

FIRST PHYSICAL

LOCATION

2679 drw 13

Figure 11. Expansion In

OPERATING MODES:

USAGE MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e. FF is monitored on the device

where W is used; EF is monitored on the device where R is Width Expansion

used). For additional information, refer to Tech Note 8: Oper- Word width may be increased simply by connecting the

ating FIFOs on Full and Empty Boundary Conditions and corresponding input control signals of multiple devices. Sta-

tusflags(EF, FFandHF)canbedetectedfromanyonedevice.

Figure 13 demonstrates an 18-bit word width by using two

IDT7200/7201A/7202As. Any word width can be attained by

adding additional IDT7200/7201A/7202As (Figure 13).

Tech Note 6: Designing with FIFOs.

Single Device Mode

A single IDT7200/7201A/7202A may be used when the

application requirements are for 256/512/1024 words or less.

The IDT7200/7201A/7202A is in a Single Device Configura-

tion when the Expansion In (XI) control input is grounded (see

Figure 12).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)

canbeachievedbypairingIDT7200/7201A/7202Asasshown

in Figure 16. Both Depth Expansion and Width Expansion

may be used in this mode.

Depth Expansion

TheIDT7200/7201A/7202Acaneasilybeadaptedtoappli-

cations when the requirements are for greater than 256/512/

1024 words. Figure 14 demonstrates Depth Expansion using

three IDT7200/7201A/7202As. Any depth can be attained by

adding additional IDT7200/7201A/7202As. The IDT7200/

7201A/7202A operates in the Depth Expansion mode when

the following conditions are met:

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-

through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.

The data is enabled on the bus in (tWEF + tA) ns after the rising

edge of W, called the first write edge, and it remains on the

bus until the R line is raised from low-to-high, after which the

buswouldgointoathree-statemodeaftertRHZ ns. TheEFline

would have a pulse showing temporary deassertion and then

would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after

reading one word of data from a full FIFO. The R line causes

the FF to be deasserted but the W line being low causes it to

be asserted again in anticipation of a new data word. On the

rising edge of W, the new word is loaded in the FIFO. The W

1. The first device must be designated by grounding the First

Load (FL) control input.

2. All other devices must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(FF) and Empty Flag (EF). This requires the ORing of all

EFsandORingofallFFs(i.e. allmustbesettogeneratethe

correct composite FF or EF). See Figure 14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

Foradditionalinformation,refertoTechNote9: Cascading line must be toggled when FFis not asserted to write new data

FIFOs or FIFO Modules.

in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large

FIFO arrays (see Figure 15).

5.03

10

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(HALF–FULL FLAG)

(HF)

WRITE (W)

READ (R)

9

IDT

DATA OUT (Q)

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

7200/

7201A/

7202A

EMPTY FLAG (EF)

RETRANSMIT (RT)

EXPANSION IN (XI)

2679 drw 14

Figure 12. Block Diagram of Single 256/512/1024 x 9 FIFO

HF

18

9

DATA IN (D)

IDT

WRITE (

FULL FLAG (FF

RESET (RS

W)

READ (

R)

7200/

7201A/

7202A

IDT

)

EMPTY FLAG (EF

)

7200/

7201A/

7202A

)

RETRANSMIT (RT

)

9

XI

18

_OUT(Q)

DATA

2679 drw 15

Figure 13. Block Diagram of 256/512/1024 x 18 FIFO Memory Used in Width Expansion Mode

TABLE I—RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Location Zero

Unchanged

RS

0

RT

X

XI

0

EF

0

FF

1

HF

1

Reset

Location Zero

Increment⁽¹⁾

Retransmit

Read/Write

NOTE:

1

0

X

1

0

Increment⁽¹⁾

X

2679 tbl 09

1. Pointer will increment if flag is High.

TABLE II—RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs

Internal Status

Outputs

Mode

Read Pointer

Location Zero

X

Write Pointer

Location Zero

X

RS

0

FL

0

XI

(1)

EF

FF

1

Reset First Device

Reset All Other Devices

Read/Write

0

X

0

1

X

NOTE:

2679 tbl 10

1. XI is connected to XO of previous device. See Figure 14. RS= Reset Input, FL/RT= First Load/Retransmit, EF= Empty Flag Output, FF= Flag Full Output,

XI = Expansion Input, HF = Half-Full Flag Output

5.03

11

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

XO

IDT

7200/

7201A/

7202A

R

W

FF

9

EF

FL

Q

D

9

VCC

XI

XO

FF

EF

FL

IDT

EMPTY

FULL

7200/

7201A/

7202A

9

XI

XO

FF

EF

IDT

7200/

7201A/

7202A

9

RS

FL

XI

2679 drw 16

Figure 14. Block Diagram of 768 x 9/1536 x 9/3072 x 9 FIFO Memory (Depth Expansion)

Q0–Q8

Q9–Q17

Q(N-8) -QN

• • •

IDT7200/

IDT7201A/

IDT7202A

DEPTH

IDT7201A/

IDT7202A

DEPTH

IDT7201A/

IDT7202A

DEPTH

R, W, RS

D0 –DN

• • •

EXPANSION

BLOCK

EXPANSION

BLOCK

EXPANSION

BLOCK

D0 -D8

D9 -D17

D(N-8)-DN

D9 -DN

D18 -DN

D(N-8)-DN

2679 drw 17

Figure 15. Compound FIFO Expansion

NOTES:

1. For depth expsansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

5.03

12

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

W

A

R_B

EF_B

HF_B

IDT

7ID20T0/

77220011AA/

7202A

FFA

DA 0-8

QB 0-8

SYSTEM A

SYSTEM B

A 0-8

Q

B 0-8

D

IDT

7200/

7201A/

7202A

R

HF

EF

A

W

B

FF

B

2679 drw 18

Figure 16. Bidirectional FIFO Mode

DATAIN

W

t RPE

R

EF

t REF

tA

tWEF

t WLZ

DATAOUT

DATAOUTVALID

2679 drw 19

Figure 17. Read Data Flow-Through Mode

R

W

t WPF

t _RFF

FF

t WFF

DATAIN

t DH

DATAIN

VALID

t _DS

t _A

DATA_OUTVALID

DATAOUT

2679 drw 20

Figure 18. Write Data Flow-Through Mode

5.03

13

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

XXXX

X

XXX

X

Device Type Power Speed Package

Process/

Temperature

Range

Blank Commercial (0°C to + 70°C)

B

Military (–55°C to + 125°C)

Compliant to MIL-STD-883, Class B

Plastic DIP (7201 & 7202 Only)

Plastic THINDIP

P

TP

D

CERDIP (7201 & 7202 Only)

Ceramic THINDIP

TD

J

Plastic Leaded Chip Carrier

SOIC

Leadless Chip Carrier (7201 & 7202 Only)

CERPACK (7201 & 7202 Only)

SO

L

XE

12

15

20

25

30

35

40

50

65

80

120

Commerical Only

Commercial Only

Military Only

Access Time (tA)

Commercial Only

Speed in Nanoseconds

Military Only

Military only--

except XE

package

LA

Low Power*

7200

7201

7202

256 x 9-Bit FIFO

512 x 9-Bit FIFO

1024 x 9-Bit FIFO

2679 drw 21

* "A" to be included for 7201 and 7202 ordering part number.

5.03

14


型号：	IDT7201LA20DG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	暂无描述先进先出芯片
文件：	总14页 (文件大小：156K)
中文：	中文翻译
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IDT7201LA20DG [IDT]

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