IDT7201LA20SO8_技术文档

CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

IDT7200L

IDT7201LA

IDT7202LA

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

•

Industrial temperature range (–40^oC to +85^oC) is available

(plastic packages only)

Green parts available, see ordering information

FEATURES:

• First-In/First-Out dual-port memory

• 256 x 9 organization (IDT7200)

•

• 512 x 9 organization (IDT7201)

• 1,024 x 9 organization (IDT7202)

• Low power consumption

— Active: 440mW (max.)

DESCRIPTION:

TheIDT7200/7201/7202aredual-portmemoriesthatloadandemptydata

onafirst-in/first-outbasis. ThedevicesuseFullandEmptyflagstopreventdata

overflowandunderflowandexpansionlogictoallowforunlimitedexpansion

capability in both word size and depth.

—Power-down: 28mW (max.)

• Ultra high speed—12ns access time

• Asynchronous and simultaneous read and write

• Fully expandable by both word depth and/or bit width

• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9

• Status Flags: Empty, Half-Full, Full

• Auto-retransmit capability

• High-performance CEMOS™ technology

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863

and 5962-89536 are listed on this function

• Dual versions available in the TSSOP package. For more informa-

tion, see IDT7280/7281/7282 data sheet

IDT7280 = 2 x IDT7200

The reads and writes are internally sequential through the use of ring

pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data

istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead

(R) pins.

Thedevicesutilizea9-bitwidedataarraytoallowforcontrolandparitybits

attheuser’soption. Thisfeatureisespeciallyusefulindatacommunications

applicationswhereitisnecessarytouseaparitybitfortransmission/reception

errorchecking. ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset

of the read pointer to its initial position when RT is pulsed LOW to allow for

retransmissionfromthebeginningofdata. AHalf-FullFlagisavailableinthe

singledevicemodeandwidthexpansionmodes.

TheseFIFOsarefabricatedusinghigh-speedCMOStechnology. They

aredesignedforthoseapplicationsrequiringasynchronousandsimultaneous

read/writes in multiprocessing and rate buffer applications. Military grade

productismanufacturedincompliancewithMIL-STD-883,ClassB.

IDT7281 = 2 x IDT7201

IDT7282 = 2 x IDT7202

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D0-D8)

WRITE

CONTROL

W

RAM

ARRAY

256 x 9

WRITE

POINTER

READ

POINTER

512 x 9

1,024 x 9

THREE-

STATE

BUFFERS

RS

DATA OUTPUTS

READ

(Q0-Q8)

RESET

LOGIC

R

CONTROL

FLAG

LOGIC

EF

FF

FL/RT

EXPANSION

2679 drw 01

XO/HF

XI

LOGIC

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.

NOVEMBER 2017

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES

1

DSC-2679/15

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

PIN CONFIGURATIONS

INDEX

W

D8

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

D4

2

4

3

2

32 31 30

1

D3

3

D5

D

2

5

29

28

27

26

25

24

23

22

21

D6

D2

4

D6

D1

6

D7

D1

5

D7

D0

7

NC

XI

8

FL/RT

RS

D0

6

FL/RT

RS

EF

FF

9

XI

7

EF

Q0

10

11

12

13

FF

Q0

Q1

Q2

Q3

Q8

GND

8

Q1

XO/HF

9

XO/HF

Q7

NC

Q7

10

11

12

13

14

Q2

Q6

14 15 16 17 18 19 20

Q5

Q4

R

2679 drw 02b

2679 drw 02a

Reference

Identifier

Order

Code

Reference

Identifier

Order

Code

PackageType

Package Type

LCC⁽¹⁾

PLCC

L32- 1

J32-1

L

J

PLASTIC DIP⁽¹⁾

PLASTIC THIN DIP

CERDIP⁽¹⁾

THIN CERDIP

SOIC

P28-1

P28-2

D28-1

D28-3

SO28-3

P

T P

D

TD

SO

TOP VIEW

NOTE:

1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200.

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Parameter

Min. Typ. Max. Unit

VCC

SupplyVoltage

Commercial/Industrial/Military

SupplyVoltage

InputHighVoltageCom'l/Ind'l

InputHighVoltageMilitary

InputLowVoltage

Commercial/Industrial/Military

OperatingTemperatureCommercial

OperatingTemperatureIndustrial

OperatingTemperatureMilitary

4.5

5.0

5.5

V

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Com’l & Ind'l

Mil.

Unit

GND

0

V

VTERM

TerminalVoltage

withRespect

to GND

–0.5 to +7.0

V

(1)

VIH

2.0

2.2

—

0.8

(1)

VIH

(2)

VIL

TSTG

IOUT

Storage

Temperature

–55 to +125

–50to+50

–65 to +155

–50to+50

°C

TA

0

–40

–55

—

70

85

125

°C

DCOutput

Current

mA

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

NOTES:

1. For RT/RS/XI input, VIH = 2.6V (commercial).

For RT/RS/XI input, VIH = 2.8V (military).

2. 1.5V undershoots are allowed for 10ns once per cycle.

2

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0^oC to +70^oC; Industrial: VCC = 5V ± 10%, TA = –40^oC to +85^oC; Military: VCC = 5V ± 10%, TA = –55^oC to +125^oC)

IDT7200L

IDT7201LA

IDT7200L

IDT7201LA

IDT7202LA

Com'l & Ind'l⁽¹⁾

tA = 12, 15, 20, 25, 35, 50 ns

Military⁽²⁾

tA = 20, 30, 50, 80 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

(3)

ILI

InputLeakageCurrent(AnyInput)

OutputLeakageCurrent

–1

–10

2.4

—

1

10

—

0.4

80

5

–10

2.4

—

10

µA

V

(4)

ILO

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

100

15

V

(5,6,7)

ICC1

ICC2

—

mA

(5,8)

StandbyCurrent(R=W=RS=FL/RT=VIH)

—

NOTES:

1. Industrial temperature range product for the 15ns and 25 ns speed grades are available as a standard device.

2. Military speed grades of 50ns and 80ns are only available for the IDT7201LA.

3. Measurements with 0.4 ≤ VIN ≤ VCC.

4. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

5. Tested with outputs open (IOUT = 0).

6. Tested at f = 20 MHz.

7. Typical ICC1 = 15 + 2*fS + 0.02*CL*fS (in mA) with VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive

load (in pF).

8. All Inputs = VCC - 0.2V or GND + 0.2V.

CAPACITANCE(TA = +25°C, f = 1.0 MHz)

Symbol

CIN

Parameter

Condition

VIN = 0V

Max.

Unit

pF

InputCapacitance

OutputCapacitance

8

COUT

VOUT = 0V

pF

NOTE:

1. Characterized values, not currently tested.

5V

1.1K

TO

OUTPUT

30pF*

AC TEST CONDITIONS

Input Pulse Levels

680Ω

GND to 3.0V

5ns

InputRise/FallTimes

2679 drw 03

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

1.5V

or equivalent circuit

SeeFigure1

Figure 1. Output Load

* Includes scope and jig capacitances.

3

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial

Com'l & Ind'l⁽²⁾

Com'l & Mil.

Com'l & Ind'l⁽²⁾

IDT7200L12

IDT7201LA12

IDT7202LA12

IDT7200L15

IDT7201LA15

IDT7202LA15

IDT7200L20

IDT7201LA20

IDT7202LA20

IDT7200L25

IDT7201LA25

IDT7202LA25

Symbol Parameter

Min.

Max.

50

—

12

—

12

—

12

17

20

12

14

—

12

14

17

—

12

—

Min.

Max.

Min.

Max.

33.3

—

20

—

15

—

30

20

—

20

30

—

20

—

Min.

—

35

—

10

25

3

Max.

Unit

MHz

ns

tS

ShiftFrequency

—

20

—

8

—

40

—

30

—

10

20

3

28.5

—

25

—

18

—

35

25

—

25

35

—

25

—

tRC

ReadCycleTime

25

—

10

15

3

—

15

—

15

—

25

15

—

15

25

—

15

—

tA

AccessTime

tRR

ReadRecoveryTime

tRPW

tRLZ

tWLZ

tDV

ReadPulseWidth⁽³⁾

12

3

Read Pulse Low to Data Bus at Low Z⁽⁴⁾

Write Pulse High to Data Bus at Low Z^(4,5)

DataValidfromReadPulseHigh

Read Pulse High to Data Bus at High Z⁽⁴⁾

WriteCycleTime

5

tRHZ

tWC

tWPW

tWR

tDS

—

20

12

8

—

25

15

10

11

0

—

30

20

10

12

0

—

35

25

10

15

0

WritePulseWidth⁽³⁾

WriteRecoveryTime

DataSet-upTime

9

tDH

DataHoldTime

0

tRSC

tRS

ResetCycleTime

ResetPulseWidth⁽³⁾

20

12

8

25

15

10

25

15

10

—

15

—

15

—

15

10

30

20

10

30

20

10

—

20

—

20

—

20

10

35

25

10

35

25

10

—

25

—

25

—

25

10

tRSS

tRSR

tRTC

tRT

ResetSet-upTime⁽⁴⁾

ResetRecoveryTime

RetransmitCycleTime

RetransmitPulseWidth⁽³⁾

RetransmitSet-upTime⁽⁴⁾

RetransmitRecoveryTime

ResettoEmptyFlagLow

20

12

8

tRTS

tRTR

tEFL

—

12

—

12

—

12

8

tHFH,FFH ResettoHalf-FullandFullFlagHigh

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

RetransmitLowtoFlagsValid

Read Low to Empty Flag Low

Read High to Full Flag High

ReadPulseWidthafterEFHigh

Write High to Empty Flag High

Write Low to Full Flag Low

WriteLowtoHalf-FullFlagLow

ReadHightoHalf-FullFlagHigh

WritePulseWidthafterFFHigh

Read/WritetoXOLow

Read/WritetoXOHigh

XI Pulse Width⁽³⁾

tXIR

XI Recovery Time

tXIS

XISet-upTime

8

NOTES:

1. Timings referenced as in AC Test Conditions.

2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode

4

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾(Continued)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Military

Commercial

Com'l & Mil.⁽²⁾

Military⁽²⁾

IDT7200L30

IDT7201LA30

IDT7202LA30

IDT7200L35

IDT7201LA35

IDT7202LA35

IDT7200L50

IDT7201LA50

IDT7202LA50

IDT7201LA80

Symbol

tS

Parameter

Min.

—

40

—

10

30

3

Max.

Min.

—

45

—

10

35

3

Max.

Min.

—

65

—

15

50

3

Max.

Min.

—

100

—

20

80

3

Max.

Unit

MHz

ns

ShiftFrequency

ReadCycleTime

AccessTime

25

—

30

—

20

—

40

30

—

30

40

—

30

—

22.2

—

35

—

20

—

45

30

—

30

45

—

35

—

15

—

50

—

30

—

65

45

—

45

65

—

50

—

10

—

80

—

30

—

100

60

—

60

100

—

80

—

tRC

tA

tRR

ReadRecoveryTime

ReadPulseWidth⁽³⁾

tRPW

tRLZ

tWLZ

tDV

Read Pulse Low to Data Bus at Low Z⁽⁴⁾

Write Pulse High to Data Bus at Low Z^{(4, 5)}

DataValidfromReadPulseHigh

Read Pulse High to Data Bus at High Z⁽⁴⁾

WriteCycleTime

5

tRHZ

tWC

—

40

30

10

18

0

—

45

35

10

18

0

—

65

50

15

30

5

—

100

80

20

40

10

100

80

20

100

80

20

—

80

—

80

—

80

10

15

tWPW

tWR

WritePulseWidth⁽³⁾

WriteRecoveryTime

tDS

DataSet-upTime

tDH

DataHoldTime

tRSC

tRS

ResetCycleTime

ResetPulseWidth⁽³⁾

ResetSet-upTime⁽⁴⁾

40

30

10

40

30

10

—

30

—

30

—

30

10

45

35

10

45

35

10

—

35

—

35

—

35

10

65

50

15

65

50

15

—

50

—

50

—

50

10

15

tRSS

tRSR

tRTC

tRT

ResetRecoveryTime

RetransmitCycleTime

RetransmitPulseWidth⁽³⁾

RetransmitSet-upTime⁽⁴⁾

RetransmitRecoveryTime

ResettoEmptyFlagLow

ResettoHalf-FullandFullFlagHigh

RetransmitLowtoFlagsValid

Read Low to Empty Flag Low

Read High to Full Flag High

ReadPulseWidthafterEFHigh

Write High to Empty Flag High

Write Low to Full Flag Low

WriteLowtoHalf-FullFlagLow

ReadHightoHalf-FullFlagHigh

WritePulseWidthafterFFHigh

Read/WritetoXOLow

tRTS

tRTR

tEFL

tHFH,FFH

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

tXI

Read/WritetoXOHigh

XI Pulse Width⁽³⁾

tXIR

XI Recovery Time

tXIS

XISet-upTime

NOTES:

1. Timings referenced as in AC Test Conditions

2. Military speed grades of 50ns and 80ns are only available for IDT7201LA.

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

5

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

DeviceMode,thispinactsastheretransmitinput. TheSingleDeviceModeis

initiated by grounding the Expansion In (XI).

SIGNALDESCRIPTIONS

The IDT7200/7201A/7202A can be made to retransmit data when the

RetransmitEnablecontrol(RT)inputispulsedLOW. Aretransmitoperationwill

settheinternalreadpointertothefirstlocationandwillnotaffectthewritepointer.

Read Enable (R) and Write Enable (W) must be in the HIGH state during

retransmit. This feature is useful when less than 256/512/1,024 writes are

performedbetweenresets. Theretransmitfeatureisnotcompatiblewiththe

DepthExpansionModeandwillaffecttheHalf-FullFlag(HF), dependingon

therelativelocationsofthereadandwritepointers.

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (RS)

ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW

state. During reset, both internal read and write pointers are set to the first

location. Aresetisrequiredafterpowerupbeforeawriteoperationcantake

place. Both the Read Enable (R) and Write Enable (W) inputs must be

in the HIGH state during the window shown in Figure 2, (i.e., tRSS

before the rising edge of RS) and should not change until tRSR after

the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after

Reset (RS).

EXPANSION IN (XI)

Thisinputisadual-purposepin. ExpansionIn(XI)isgroundedtoindicate

an operation in the single device mode. Expansion In (XI) is connected to

Expansion Out (XO) of the previous device in the Depth Expansion or Daisy

Chain Mode.

OUTPUTS:

WRITE ENABLE (W)

FULL FLAG (FF)

AwritecycleisinitiatedonthefallingedgeofthisinputiftheFullFlag(FF)

isnotset. Dataset-upandholdtimesmustbeadheredtowithrespecttotherising

edgeoftheWriteEnable(W). DataisstoredintheRAMarraysequentiallyand

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of the next write

operation,theHalf-FullFlag(HF)willbesettoLOWandwillremainsetuntilthe

differencebetweenthewritepointerandreadpointerislessthanorequalto

onehalfofthetotalmemoryofthedevice. TheHalf-FullFlag(HF)isthenreset

by the rising edge of the read operation.

Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther

write operations. Upon the completion of a valid read operation, the Full

Flag(FF)willgoHIGHaftertRFF,allowingavalidwritetobegin. WhentheFIFO

isfull,theinternalwritepointerisblockedfromW,soexternalchangesinWwill

notaffecttheFIFOwhenitisfull.

TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe

write pointer is one location less than the read pointer, indicating that the

device is full. If the read pointer is not moved after Reset (RS), the Full-Flag

(FF)willgoLOWafter256writesforIDT7200,512writesfortheIDT7201Aand

1,024 writes for the IDT7202A.

EMPTY FLAG (EF)

TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when

the read pointer is equal to the write pointer, indicating that the device is

empty.

EXPANSION OUT/HALF-FULL FLAG (XO/HF)

This is a dual-purpose output. In the single device mode, when

Expansion In (XI) is grounded, this output acts as an indication of a half-full

memory.

After half of the memory is filled and at the falling edge of the next write

operation,theHalf-FullFlag(HF)willbesetLOWandwillremainsetuntilthe

difference between the write pointer and read pointer is less than or equal

to one half of the total memory of the device. The Half-Full Flag (HF) is then

reset by using rising edge of the read operation.

IntheDepthExpansionMode,ExpansionIn(XI)isconnectedtoExpansion

Out(XO)ofthepreviousdevice.Thisoutputactsasasignaltothenextdevice

intheDaisyChainbyprovidingapulsetothenextdevicewhentheprevious

devicereachesthelastlocationofmemory.

READ ENABLE (R)

AreadcycleisinitiatedonthefallingedgeoftheReadEnable(R)provided

theEmptyFlag(EF)isnotset. ThedataisaccessedonaFirst-In/First-Outbasis,

independent of any ongoing write operations. After Read Enable (R) goes

HIGH,theDataOutputs(Q0–Q8)willreturntoahighimpedanceconditionuntil

thenextReadoperation. WhenalldatahasbeenreadfromtheFIFO,theEmpty

Flag(EF)willgoLOW,allowingthe“final”readcyclebutinhibitingfurtherread

operationswiththedataoutputsremaininginahighimpedancestate. Oncea

validwriteoperationhasbeenaccomplished,theEmptyFlag(EF)willgoHIGH

aftertWEFandavalidReadcanthenbegin. WhentheFIFOisempty,theinternal

readpointerisblockedfromRsoexternalchangesinRwillnotaffecttheFIFO

whenitisempty.

DATA OUTPUTS (Q0 – Q8)

Dataoutputsfor9-bitwidedata. Thisdataisinahighimpedancecondition

whenever Read (R) is in a HIGH state.

FIRST LOAD/RETRANSMIT (FL/RT)

This is a dual-purpose input. In the Depth Expansion Mode, this pin is

groundedtoindicatethatitisthefirstloaded(seeOperatingModes). IntheSingle

6

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

tRSC

tRS

RS

W

tRSR

tRSS

R

tEFL

EF

tHFH , tFFH

HF, FF

2679 drw 04

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = V^IHaround the rising edge of RS.

Figure 2. Reset

tRC

tRPW

tRR

tA

R

tDV

tRHZ

tRLZ

Q0-Q8

DATA OUT VALID

tWC

tWPW

tWR

W

tDS

tDH

D0-D8

DATA IN VALID

2679 drw 05

Figure 3. Asynchronous Write and Read Operation

FIRST

WRITE

LAST WRITE

IGNORED

WRITE

FIRST READ

ADDITIONAL

READS

R

W

t

WFF

t

RFF

2679 drw 06

FF

Figure 4. Full Flag From Last Write to First Read

7

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

LAST READ

IGNORED

READ

FIRST WRITE

ADDITIONAL

WRITES

FIRST READ

W

R

EF

tWEF

t

REF

tA

DATA OUT

VALID

2679 drw 07

Figure 5. Empty Flag From Last Read to First Write

tRTC

tRT

RT

W,R

tRTS

tRTF

tRTR

HF, EF, FF

FLAG VALID

2679 drw 08

Figure 6. Retransmit

W

EF

R

t

WEF

tRPE

2679 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

R

FF

W

t

RFF

tWPF

2679 drw 10

Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse

8

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

W

R

tRHF

tWHF

HALF-FULL OR LESS

MORE THAN HALF-FULL

HF

2679 drw 11

Figure 9. Half-Full Flag Timing

WRITE TO

LAST PHYSICAL

LOCATION

READ FROM

LAST PHYSICAL

LOCATION

W

R

tXOL

tXOH

tXOL

2679 drw 12

XO

Figure 10. Expansion Out

tXIR

tXI

XI

tXIS

WRITE TO

FIRST PHYSICAL

LOCATION

W

R

tXIS

READ FROM

FIRST PHYSICAL

LOCATION

2679 drw 13

Figure 11. Expansion In

depthcanbeattainedbyaddingadditionalIDT7200/7201A/7202As. These

FIFOsoperateintheDepthExpansionmodewhenthefollowingconditions

are met:

OPERATINGMODES:

Care must be taken to assure that the appropriate flag is monitored by

eachsystem(i.e.FFismonitoredonthedevicewhereWisused;EFismonitored

onthedevicewhereRisused).Foradditionalinformation,refertoTechNote

8: OperatingFIFOsonFullandEmptyBoundaryConditions andTechNote

1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(FL)control

input.

2. All other devices must have FLin the HIGH state.

3. TheExpansionOut(XO)pinofeachdevicemustbetiedtotheExpansion

In (XI) pin of the next device. See Figure 14.

4. ExternallogicisneededtogenerateacompositeFullFlag(FF)andEmpty

Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e.

allmustbesettogeneratethecorrectcompositeFForEF). SeeFigure

14.

6: Designing with FIFOs.

SINGLE DEVICE MODE

A single IDT7200/7201A/7202A may be used when the application

requirements are for 256/512/1,024 words or less. These devices are in a

Single Device Configuration when the Expansion In (XI) control input is

grounded (see Figure 12).

5. TheRetransmit(RT)functionandHalf-FullFlag(HF)arenotavailablein

theDepthExpansionMode.

DEPTH EXPANSION

The IDT7200/7201A/7202A can easily be adapted to applications when

the requirements are for greater than 256/512/1,024 words. Figure 14

demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any

For additional information, refer to Tech Note 9: Cascading FIFOs or

FIFO Modules.

9

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

theFIFOpermitsareadingofasinglewordafterwritingonewordofdatainto

anemptyFIFO. Thedataisenabledonthebusin(tWEF +tA)nsaftertherising

edgeofW,calledthefirstwriteedge,anditremainsonthebusuntiltheRline

israisedfromLOW-to-HIGH, afterwhichthebuswouldgointoathree-state

mode after tRHZ ns. The EF line would have a pulse showing temporary

deassertionandthenwouldbeasserted.

In the write flow-through mode (Figure 18), the FIFO permits the writing

of a single word of data immediately after reading one word of data from a

fullFIFO. TheRlinecausestheFFtobedeassertedbuttheWlinebeingLOW

causesittobeassertedagaininanticipationofanewdataword. Ontherising

edge of W, the new word is loaded in the FIFO. The W line must be toggled

whenFFisnotassertedtowritenewdataintheFIFOandtoincrementthewrite

pointer.

USAGEMODES:

WIDTH EXPANSION

Word width may be increased simply by connecting the corresponding

inputcontrolsignalsofmultipledevices. Statusflags(EF,FFandHF)canbe

detectedfromanyonedevice. Figure13demonstratesan18-bitwordwidth

by using two IDT7200/7201A/7202As. Any word width can be attained by

adding additional IDT7200/7201A/7202As (Figure 13).

BIDIRECTIONAL OPERATION

Applications which require data buffering between two systems (each

system capable of Read and Write operations) can be achieved by pairing

IDT7200/7201A/7202AsasshowninFigure16.BothDepthExpansionand

Width Expansion may be used in this mode.

COMPOUND EXPANSION

Thetwoexpansiontechniquesdescribedabovecanbeappliedtogether

in a straightforward manner to achieve large FIFO arrays (see Figure 15).

DATA FLOW-THROUGH

Two types of flow-through modes are permitted, a read flow-through

and write flow-through mode. For the read flow-through mode (Figure 17),

(HALF-FULL FLAG)

WRITE (W)

(HF)

READ (R)

9

IDT

DATA OUT (Q)

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

7200/

7201A/

7202A

EMPTY FLAG (EF)

RETRANSMIT (RT)

EXPANSION IN (XI)

2679 drw 14

Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO

HF

18

9

IN

DATA (D)

IDT

WRITE (W)

FULL FLAG (FF)

RESET (RS)

READ (R)

7200/

7201A/

7202A

IDT

EMPTY FLAG (EF)

7200/

7201A/

7202A

RETRANSMIT (RT)

9

XI

18

DATA OUT (Q)

2679 drw 15

Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode

10

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

TABLE 1 — RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs

InternalStatus

Write Pointer

Outputs

Mode

RS

RT

XI

Read Pointer

EF

FF

HF

Reset

0

1

X

0

1

0

LocationZero

Increment⁽¹⁾

LocationZero

Unchanged

Increment⁽¹⁾

0

X

1

X

1

X

Retransmit

Read/Write

NOTE:

1. Pointer will increment if flag is HIGH.

TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs

InternalStatus

Write Pointer

Outputs

Mode

RS

FL

XI

Read Pointer

EF

FF

ResetFirstDevice

Reset All Other Devices

Read/Write

0

1

0

1

X

(1)

LocationZero

X

LocationZero

X

0

X

1

X

NOTE:

1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

XI = Expansion Input, HF = Half-Full Flag Output

XO

R

W

FF

EF

FL

IDT

7200/

7201A/

7202A

9

Q

V

D

CC

XI

XO

FF

EF

FL

IDT

EMPTY

FULL

7200/

7201A/

7202A

9

XI

XO

FF

EF

IDT

7200/

7201A/

7202A

9

RS

FL

XI

2678 drw16

Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)

11

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

Q

0-

Q

8

Q

9-

Q

17

Q

(N-8)-Q

n

Q9-

Q

Q0-

Q

8

Q(N-8)-Q

n

IDT7200/

IDT7201A/

IDT7202A

DEPTH

IDT7201A/

IDT7202A

DEPTH

IDT7201A/

IDT7202A

DEPTH

R, W, RS

EXPANSION

BLOCK

EXPANSION

BLOCK

EXPANSION

BLOCK

D0-D8

D9-D17

D(N-8)-DN

D0-DN

2679 drw 17

D9-DN

D18-DN

D(N-8)-DN

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

Figure 15. Compound FIFO Expansion

W

A

RB

EF

HF

IDT

B

7200/

7201A

7201A/

B

FFA

7202A

DA 0-8

QB 0-8

SYSTEM A

SYSTEM B

QA 0-8

DB 0-8

IDT

7200/

7201A/

7202A

R

A

W

B

HFA

FF

B

2679 drw 18

EFA

Figure 16. Bidirectional FIFO Mode

12

IDT7201L/7201LA/7202LACMOSASYNCHRONOUSFIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL,INDUSTRIALANDMILITARY

TEMPERATURERANGES

IN

DATA

W

R

tRPE

EF

t

REF

tWEF

tWLZ

tA

DATA OUT

OUT

DATA

VALID

2679 drw 19

Figure 17. Read Data Flow-Through Mode

R

tWPF

W

t

RFF

FF

tDH

t

WFF

IN

DATA

VALID

IN

DATA

tDS

tA

OUT

DATA

OUT

DATA

VALID

2679 drw 20

Figure 18. Write Data Flow-Through Mode

13

ORDERING INFORMATION

X

XXXX

X

XXX

X

Device Type Power Speed Package

Process/

Temperature

Range

Blank

8

Tube or Tray

Tape and Reel

Blank

I⁽¹⁾

B

Commercial (0^oC to +70^oC)

Industrial (-40^oC to +85^oC)

Military (-55^oC to +125^oC)

Compliant to MIL-STD-883, Class B

G⁽³⁾

Green

P ⁽⁴⁾

TP

D

TD

J

Plastic DIP

Plastic Thin DIP

CERDIP

Thin CERDIP

Plastic Leaded Chip Carrier

SOIC

P28-1

P28-2

D28-1

D28-3

J32-1

SO28-3

L32-1

(7201 & 7202 Only)

PLCC

LCC

SO

L

Leadless Chip Carrier

(7201 & 7202 Only)

12

15

20

25

30

35

50

80

Commercial Only

Commercial and Industrial

Commercial and Military

Commercial and Industrial

Military Only

Commercial Only

Commercial and (Military only for 7201)

Military only for 7201

Access Time (t

Speed in Nanoseconds

A)

LA⁽²⁾

Low Power

7200

7201

7202

7280

7281

7282

256 x 9-Bit FIFO

512 x 9-Bit FIFO

1,024 x 9-Bit FIFO

256 x 9-Bit DUAL FIFO

512 x 9-Bit DUAL FIFO

1,024 x 9-Bit DUAL FIFO

See 7280/7281/7282

data sheet for details

2679 drw 21

NOTES:

1. Industrial temperature range product is available for the 15ns and 25ns as a standard product.

2. "A" to be included for IDT7201 and IDT7202 ordering part number.

3. Green parts are available. For specific speeds and packages contact your local sales office.

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

4. For "P", Plastic Dip, when ordering green package, the suffix is "PDG".

DATASHEETDOCUMENTHISTORY

05/02/2001

04/03/2006

10/22/2008

06/29/2012

11/27/2017

pgs. 1, 2, 3, 4, 5 and 14.

pgs. 1 and 14.

pg. 1.

pgs. 1 and 14.

ProductDiscontinuationNotice-PDN#SP-17-02

Last time buy expires June 15, 2018.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

14


型号：	IDT7201LA20SO8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO, 512X9, 20ns, Asynchronous, CMOS, PDSO28, SOIC-28 时钟先进先出芯片光电二极管内存集成电路
文件：	总14页 (文件大小：110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7201LA20SO8 [IDT]

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