IDT7206L25TDB_技术文档

CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9,

8192 x 9 and 16384 x 9

IDT7203

IDT7204

IDT7205

IDT7206

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• First-In/First-Out Dual-Port memory

• 2048 x 9 organization (IDT7203)

• 4096 x 9 organization (IDT7204)

• 8192 x 9 organization (IDT7205)

• 16384 x 9 organization (IDT7206)

• High-speed: 12ns access time

The IDT7203/7204/7205/7206 are dual-port memory buff-

ers with internal pointers that load and empty data on a first-

in/first-out basis. The device uses Full and Empty flags to

prevent data overflow and underflow and expansion logic to

allow for unlimited expansion capability in both word size and

depth.

• Low power consumption

— Active: 770mW (max.)

Data is toggled in and out of the device through the use of

the Write (W) and Read (R) pins.

— Power-down: 44mW (max.)

The devices 9-bit width provides a bit for a control or parity

at the user’s option. It also features a Retransmit (RT) capa-

bilitythatallowsthereadpointertoberesettoitsinitialposition

when RT is pulsed LOW. A Half-Full Flag is available in the

single device and width expansion modes.

The IDT7203/7204/7205/7206 are fabricated using IDT’s

high-speed CMOS technology. They are designed for appli-

cationsrequiringasynchronousandsimultaneousread/writes

in multiprocessing, rate buffering, and other applications.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

• Asynchronous and simultaneous read and write

• Fully expandable in both word depth and width

• Pin and functionally compatible with IDT720X family

• Status Flags: Empty, Half-Full, Full

• Retransmit capability

• High-performance CMOS technology

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing for #5962-88669 (IDT7203),

5962-89567 (IDT7203), and 5962-89568 (IDT7204) are

listed on this function

• Industrial temperature range (-40^oC to +85^oC) is avail-

able, tested to military electrical specifications

.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D0 –D8)

WRITE

CONTROL

W

RAM ARRAY

WRITE

POINTER

READ

POINTER

2048 x 9

4096 x 9

8192 x 9

16384 x 9

THREE-

STATE

BUFFERS

RS

DATA OUTPUTS

(Q0 –Q8)

READ

CONTROL

RESET

LOGIC

R

FLAG

LOGIC

EF

FF

FL/RT

EXPANSION

LOGIC

XO/HF

XI

2661 drw 01

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1996 Integrated Device Technology, Inc.

DSC-2661/9

5.04

1

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

1

2

3

4

5

6

7

28

27

W

Vcc

D

8

D

4

26

25

24

23

22

21

20

19

18

17

16

15

D

3

2

5

6

5

29

28

27

26

25

24

23

22

21

D

2

D

6

7

NC

D

6

7

1

0

P28-1

P28-2

D28-1

D28-3

SO28-3

D

XI

FF

1

0

7

FL/RT

RS

EF

J32-1

&

L32-1

8

9

XI

FF

FL/RT

RS

EF

XO/HF

Q

8

9

10

11

12

13

Q

NC

0

1

Q

0

XO/HF

10

11

12

13

14

Q

R

7

6

5

4

Q

1

2

3

7

6

Q

2

Q₈

GND

2661 drw 02b

2661 drw 02a

PLCC/LCC

TOP VIEW

DIP

TOP VIEW

NOTES:

1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/

7205.

2. The small outline package SO28-3 is only available for the 7204.

3. Consult factory for CERPACK pinout.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Rating

Commercial

Military

Unit

Symbol

Parameter

Min.

Typ.

Max.

Unit

VTERM

Terminal

Voltage with

Respect to

GND

–0.5 to + 7.0

–0.5 to +7.0

V

VCCM

Military Supply

Voltage

4.5

5.0

5.5

V

VCCC

GND

Commercial Supply

Voltage

4.5

5.0

5.5

V

TA

Operating

Temperature

0 to +70

–55 to +125

–65 to +135

–65 to +155

50

° C

Supply Voltage

0

V

TBIAS

TSTG

IOUT

Temperature –55 to +125

Under Bias

(1)

VIH

Input High Voltage

Commercial

2.0

—

Storage

Temperature

–55 to + 125

° C

(1)

VIH

Input High Voltage

Military

2.2

—

V

DC Output

Current

50

mA

(1)

VIL

Input Low Voltage

Commercial and

Military

0.8

NOTE:

2661 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

onlyandfunctionaloperationofthedeviceattheseoranyotherconditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

NOTE:

2661 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

5.04

2

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

IDT7203/7204

Commercial

IDT7203/7204

Military⁽¹⁾

tA = 12, 15, 20, 25, 35, 50 ns

tA = 20, 30, 40, 50, 65, 80, 120 ns

Symbol

Parameter

Min.

–1

Typ.

—

Max.

1

Min.

–1

Typ.

—

Max.

1

Unit

µA

V

(2)

ILI

Input Leakage Current (Any Input)

Output Leakage Current

(3)

ILO

–10

2.4

—

10

–10

2.4

—

10

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

120⁽⁵⁾

12

—

0.4

150⁽⁵⁾

25

V

(4)

ICC1

—

mA

(4)

ICC2

Standby Current (R=W=RS=FL/RT=VIH)

—

ICC3(L)⁽⁴⁾Power Down Current (All Input = VCC - 0.2V)

ICC3(S)⁽⁴⁾Power Down Current (All Input = VCC - 0.2V)

NOTES:

—

2

—

4

—

8

—

12

2661 tbl 03

1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. ICC measurements are made with outputs open (only capacitive loading).

5. Tested at f = 20MHz.

DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)

IDT7205/7206

Commercial

IDT7205/7206

Military

tA = 15, 20, 25, 35, 50 ns

tA = 20, 30, 50 ns

Symbol

Parameter

Min.

–1

Typ.

—

Max.

1

Min.

–1

Typ.

—

Max.

1

Unit

µA

V

(1)

ILI

Input Leakage Current (Any Input)

Output Leakage Current

(2)

ILO

–10

2.4

—

10

–10

2.4

—

10

VOH

VOL

Output Logic “1” Voltage IOH = –2mA

Output Logic “0” Voltage IOL = 8mA

Active Power Supply Current

—

0.4

120⁽⁴⁾

12

—

0.4

150⁽⁴⁾

V

(3)

ICC1

—

mA

(3)

ICC2

Standby Current (R=W=RS=FL/RT=VIH)

—

25

ICC3(L)⁽³⁾Power Down Current (All Input = VCC - 0.2V)

—

8

—

12

mA

NOTES:

2661 tbl 04

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. ICC measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.04

3

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS⁽¹⁾

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Commercial Com'l & Mil. Com'l Military

Com'l

7203S/L12 7203S/L15 7203S/L20 7203S/L25 7203S/L30 7203S/L35

7204S/L12 7204S/L15 7204S/L20 7204S/L25 7204S/L30 7204S/L35

7205L15

7206L15

7205L20

7206L20

7205L25

7206L25

7205L30

7206L30

7205L35

7206L35

Symbol Parameters

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fS

Shift Frequency

—

20

—

8

50

—

12

—

25

—

10

15

40

—

15

—

30

—

10

20

33.3

—

35

—

10

25

28.5

—

40

—

10

30

25

—

30

—

45

—

10

35

22.2 MHz

tRC

tA

Read Cycle Time

Access Time

—

35

—

ns

20

—

25

—

tRR

tRPW

Read Recovery Time

Read Pulse Width⁽²⁾

12

—

tRLZ

tWLZ

tDV

Read LOW to Data Bus LOW⁽³⁾

Write HIGH to Data Bus Low-Z^{(3, 4)}

Data Valid from Read HIGH

Read HIGH to Data Bus High-Z⁽³⁾

Write Cycle Time

3

—

12

—

5

—

15

—

5

—

15

—

5

—

18

—

5

—

20

—

5

—

20

—

ns

5

10

5

tRHZ

tWC

tWPW

tWR

tDS

—

20

12

8

—

25

15

10

11

0

—

30

20

10

12

0

—

35

25

10

15

0

—

40

30

10

18

0

—

45

35

10

18

0

Write Pulse Width⁽²⁾

Write Recovery Time

Data Set-up Time

9

tDH

Data Hold Time

0

tRSC

tRS

Reset Cycle Time

Reset Pulse Width⁽²⁾

20

12

25

15

30

20

35

25

40

30

45

35

tRSS

tRTR

tRTC

Reset Set-up Time⁽³⁾

12

8

—

12

17

20

12

14

—

12

14

17

—

12

—

15

10

25

15

10

—

15

—

15

—

15

10

—

25

15

—

15

25

—

15

—

20

10

30

20

10

—

20

—

20

—

20

10

—

30

20

—

20

30

—

20

—

25

10

35

25

10

—

25

—

25

—

25

10

—

35

25

—

25

35

—

25

—

30

10

40

30

10

—

30

—

30

—

30

10

—

40

30

—

30

40

—

30

—

35

10

45

35

10

—

35

—

35

—

35

10

15

—

45

30

—

30

45

—

35

—

ns

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width⁽²⁾

Retransmit Set-up Time⁽³⁾

Retransmit Recovery Time

Reset to EF LOW

20

12

8

tRT

tRTS

tRSR

tEFL

—

12

—

12

—

12

8

tHFH, tFFH Reset to HF and FF HIGH

tRTF

tREF

tRFF

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

tXOH

Retransmit LOW to Flags Valid

Read LOW to EF LOW

Read HIGH to FF HIGH

Read Pulse Width after EF HIGH

Write HIGH to EF HIGH

Write LOW to FF LOW

Write LOW to HF Flag LOW

Read HIGH to HF Flag HIGH

Write Pulse Width after FF HIGH

Read/Write LOW to XO LOW

Read/Write HIGH to XO HIGH

XI Pulse Width⁽²⁾

tXI

ns

tXIR

XI Recovery Time

tXIS

XI Set-up Time

8

ns

NOTES:

2661 tbl 05

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum are not allowed.

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

5.04

4

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS⁽¹⁾(Continued)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Military

Com'l & Mil.

Military⁽²⁾

7203S/L40

7204S/L40

7203S/L50

7204S/L50

7205L50

7203S/L65 7203S/L80 7203S/L120

7204S/L65 7204S/L80 7204S/L120

7206L50

Symbol

fS

Parameters

Shift Frequency

Min.

—

Max. Min.

Max. Min. Max. Min. Max. Min. Max.

Unit

MHz

ns

20

—

40

—

65

—

15

50

15

—

50

—

80

—

15

65

12.5

—

100

—

10

—

80

—

140

—

7

—

tRC

Read Cycle Time

Access Time

50

—

tA

65

—

120

—

ns

tRR

Read Recovery Time

Read Pulse Width⁽³⁾

10

40

20

ns

tRPW

—

80

120

—

ns

tRLZ

tWLZ

tDV

Read LOW to Data Bus LOW⁽⁴⁾

Write HIGH to Data Bus Low-Z^{(4, 5)}

Data Valid from Read HIGH

Read HIGH to Data Bus High-Z⁽⁴⁾

Write Cycle Time

5

—

25

—

10

15

5

—

30

—

10

15

5

—

30

—

10

20

5

—

30

—

10

20

—

35

—

ns

10

5

tRHZ

tWC

tWPW

tWR

tDS

—

50

40

10

20

0

—

65

50

15

30

5

—

80

65

15

30

10

80

65

—

100

80

20

40

10

100

80

140

120

20

Write Pulse Width⁽³⁾

Write Recovery Time

Data Set-up Time

40

tDH

Data Hold Time

10

tRSC

tRS

Reset Cycle Time

Reset Pulse Width⁽³⁾

50

40

65

50

140

120

tRSS

tRSR

tRTC

Reset Set-up Time⁽⁴⁾

40

10

50

40

10

—

40

—

40

—

40

10

15

—

50

35

—

35

50

—

40

—

50

15

65

50

15

—

50

—

50

—

50

10

15

—

65

45

—

45

65

—

50

—

65

15

80

65

15

—

65

—

65

—

65

10

15

—

80

60

—

60

80

—

65

—

80

20

100

80

20

—

80

—

80

—

80

10

15

—

120

20

—

ns

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width⁽³⁾

Retransmit Set-up Time⁽⁴⁾

Retransmit Recovery Time

Reset to EF LOW

—

140

120

20

—

ns

tRT

—

ns

tRTS

tRSR

tEFL

—

ns

—

ns

100

60

—

140

60

ns

tHFH, tFFH

tRTF

Reset to HF and FF HIGH

Retransmit LOW to Flags Valid

Read LOW to EF Flag LOW

Read HIGH to FF HIGH

Read Pulse Width after EF HIGH

Write HIGH to EF HIGH

Write LOW to FF LOW

Write LOW to HF LOW

Read HIGH to HF HIGH

Write Pulse Width after FF HIGH

Read/Write LOW to XO LOW

Read/Write HIGH to XO HIGH

XI Pulse Width⁽³⁾

—

ns

—

ns

tREF

—

ns

tRFF

—

60

ns

tRPE

tWEF

tWFF

tWHF

tRHF

tWPF

tXOL

120

—

ns

60

100

—

60

ns

—

60

ns

—

140

—

ns

—

ns

120

—

ns

80

—

120

—

ns

tXOH

tXI

—

ns

120

10

ns

tXIR

XI Recovery Time

—

ns

tXIS

XI Set-up Time

—

15

—

ns

NOTES:

2661 tbl 06

1. Timings referenced as in AC Test Conditions.

2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.

3. Pulse widths less than minimum are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

5.04

5

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

5V

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

5ns

1.5V

1.1KΩ

See Figure 1

D.U.T.

2661 tbl 07

30pF*

680Ω

CAPACITANCE⁽¹⁾(TA = +25°C, f = 1.0 MHz)

2661 drw 03

Symbol

Parameter

Condition

VIN = 0V

Max. Unit

(1)

CIN

Input Capacitance

Output Capacitance

10

pF

OR EQUIVALENT CIRCUIT

(1,2)

COUT

VOUT = 0V

pF

Figure 1. Output Load

NOTES:

2661 tbl 08

1. This parameter is sampled and not 100% tested.

2. With output deselected.

*Includes jig and scope capacitances.

READ ENABLE ( ) — A read cycle is initiated on the falling

R

SIGNAL DESCRIPTIONS

Inputs:

edgeoftheReadEnable(R),providedtheEmptyFlag(EF)isnot

set. The data is accessed on a First-In/First-Out basis, inde-

pendentofanyongoingwriteoperations. AfterReadEnable(R)

goes HIGH, the Data Outputs (Q0 through Q8) will return to a

high-impedance condition until the next Read operation. When

all the data has been read from the FIFO, the Empty Flag (EF)

will go LOW, allowing the “final” read cycle but inhibiting further

read operations, with the data outputs remaining in a high-

impedancestate. Onceavalidwriteoperationhasbeenaccom-

plished, the Empty Flag (EF) will go HIGH after tWEF and a valid

Readcanthenbegin. WhentheFIFOisempty,theinternalread

pointer is blocked from Rso external changes will not affect the

FIFO when it is empty.

DATA IN (D0–D8) — Data inputs for 9-bit wide data.

Controls:

RESET ( ) — Reset is accomplished whenever the Reset

RS

(RS) input is taken to a LOW state. During reset, both internal

read and write pointers are set to the first location. A reset is

required after power-up before a write operation can take place.

Both the Read Enable ( ) and Write Enable ( ) inputs must

R

W

be in the HIGH state during the window shown in Figure 2

(i.e. tRSS before the rising edge of ) and should not

RS

change until tRSR after the rising edge of

FIRST LOAD/RETRANSMIT (

/

) — This is a dual-

FL RT

.

RS

purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first device loaded (see

Operating Modes). The Single Device Mode is initiated by

grounding the Expansion In (XI).

WRITEENABLE( )—Awritecycleisinitiatedonthefalling

W

edge of this input if the Full Flag (FF) is not set. Data set-up and

hold times must be adhered-to, with respect to the rising edge

of the Write Enable (W). Data is stored in the RAM array

sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW,

and will remain set until the difference between the write pointer

and read pointer is less-than or equal to one-half of the total

memory of the device. The Half-Full Flag (HF) is reset by the

rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW on

thefallingedgeofthelastwritesignal,whichinhibitsfurtherwrite

operations. Upon the completion of a valid read operation, the

Full Flag (FF) will go HIGH after tRFF, allowing a new valid write

to begin. When the FIFO is full, the internal write pointer is

blockedfromW,soexternalchangesinWwillnotaffecttheFIFO

when it is full.

The IDT7203/7204/7205/7206 can be made to retransmit

data when the Retransmit Enable Control (RT) input is pulsed

LOW. A retransmit operation will set the internal read pointer to

the first location and will not affect the write pointer. The status

of the Flags will change depending on the relative locations of

the read and write pointers. Read Enable (R) and Write Enable

(W) must be in the HIGH state during retransmit. This feature is

useful when less than 2048/4096/8192/16384 writes are per-

formed between resets. The retransmit feature is not compat-

ible with the Depth Expansion Mode.

EXPANSION IN ( ) — This input is a dual-purpose pin.

XI

Expansion In (XI) is grounded to indicate an operation in the

single device mode. Expansion In (XI) is connected to Expan-

sion Out (XO) of the previous device in the Depth Expansion or

Daisy-Chain Mode.

5.04

6

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

and will remain set until the difference between the write pointer

and read pointer is less than or equal to one half of the total

memory of the device. The Half-Full Flag (HF) is then reset by

the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con-

nected to Expansion Out (XO) of the previous device. This

output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device

reaches the last location of memory. There will be an XO pulse

whentheWritepointerreachesthelastlocationofmemory, and

an additional XO pulse when the Read pointer reaches the last

location of memory.

Outputs:

FULLFLAG( )—TheFullFlag(FF)willgoLOW,inhibiting

FF

further write operations, when the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go

LOW after 2048/4096/8192/16384 writes.

EMPTY FLAG ( ) — The Empty Flag (EF) will go LOW,

inhibitingfurtherreadoperations,whenthereadpointerisequal

to the write pointer, indicating that the device is empty.

EF

EXPANSION OUT/HALF-FULL FLAG(

/

) — This is a

XO HF

dual-purpose output. In the single device mode, when Expan-

sionIn(XI)isgrounded,thisoutputactsasanindicationofahalf-

full memory.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW

DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-

bit wide data. These outputs are in a high-impedance condition

whenever Read (R) is in a HIGH state.

t

RSC

t

RS

W

t

RSS

tRSR

t

RSS

R

t

EFL

EF

t

HFH

, tFFH

HF, FF

2661 drw 04

NOTE:

1. W and R = VIH around the rising edge of RS.

Figure 2. Reset

t

RC

tRPW

t

RR

t

A

t

A

R

t

DV

tRHZ

t

RLZ

DATAOUT VALID

Q0–Q8

t_WC

t

WPW

tWR

W

t_DS

t _DH

DATAIN

VALID

D0–D8

2661 drw 05

Figure 3. Asynchronous Write and Read Operation

5.04

7

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IGNORED

WRITE

LAST WRITE

FIRST READ

R

W

t_WFF

tRFF

FF

2661 drw 06

Figure 4. Full FlagTiming From Last Write to First Read

IGNORED

READ

LAST READ

FIRST WRITE

W

R

t_REF

tWEF

EF

t_A

VALID

DATAOUT

2661 drw 07

Figure 5. Empty Flag Timing From Last Read to First Write

t RTC

t RT

RT

t

RTS

tRTR

W,R

RTF

HF, EF, FF

FLAG VALID

2661 drw 08

NOTE:

1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.

Figure 6. Retransmit

5.04

8

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

W

EF

R

t _WEF

t _RPE

2661 drw 09

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.

R

FF

W

t_RFF

t_WPF

2661 drw 10

Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.

W

t

RHF

R

t

WHF

HF

HALF-FULL OR LESS

MORE THAN HALF-FULL

HALF-FULL OR LESS

2661 drw 11

Figure 9. Half-Full Flag Timing

WRITE TO

LAST PHYSICAL

LOCATION

W

R

READ FROM

LAST PHYSICAL

LOCATION

t_XOL

t_XOH

t_XOL

t_XOH

XO

2661 drw 12

Figure 10. Expansion Out

5.04

9

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t _XI

t_XIR

XI

t_XIS

WRITE TO

FIRST PHYSICAL

LOCATION

W

R

t

XIS

READ FROM

FIRST PHYSICAL

LOCATION

2661 drw 11

Figure 11. Expansion In

OPERATING MODES:

USAGE MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e. FF is monitored on the device Width Expansion

where W is used; EF is monitored on the device where R is

Word width may be increased simply by connecting the

used). For additional information, refer to Tech Note 8: Oper- corresponding input control signals of multiple devices. Sta-

ating FIFOs on Full and Empty Boundary Conditions and tusflags(EF, FFandHF)canbedetectedfromanyonedevice.

Figure 13 demonstrates an 18-bit word width by using two

IDT7203/7204/7205/7206s. Any word width can be attained

by adding additional IDT7203/7204/7205/7206s (Figure 13).

Tech Note 6: Designing with FIFOs.

Single Device Mode

A single IDT7203/7204/7205/7206 may be used when the

applicationrequirementsarefor 2048/4096/8192/16384 words

or less. The IDT7203/7204/7205/7206 is in a Single Device

Configuration when the Expansion In (XI) control input is

grounded (see Figure 12).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)

can be achieved by pairing IDT7203/7204/7205/7206s as

shown in Figure 16. Both Depth Expansion and Width Expan-

sion may be used in this mode.

Depth Expansion

The IDT7203/7204/7205/7206 can easily be adapted to

applicationswhentherequirementsareforgreaterthan2048/

4096/8192/16384 words. Figure 14 demonstrates Depth Ex-

pansion using three IDT7203/7204/7205/7206s. Any depth

can be attained by adding additional IDT7203/7204/7205/

7206s. The IDT7203/7204/7205/7206 operates in the Depth

Expansion mode when the following conditions are met:

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-

through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.

The data is enabled on the bus in (tWEF + tA) ns after the rising

edgeofW, calledthefirstwriteedge, anditremainsonthebus

until the R line is raised from LOW-to-HIGH, after which the

buswouldgointoathree-statemodeaftertRHZ ns. TheEFline

would have a pulse showing temporary deassertion and then

would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after

reading one word of data from a full FIFO. The R line causes

the FFto be deasserted but the Wline being LOW causes it to

be asserted again in anticipation of a new data word. On the

rising edge of W, the new word is loaded in the FIFO. The W

line must be toggled when FFis not asserted to write new data

1. The first device must be designated by grounding the First

Load (FL) control input.

2. All other devices must have FL in the HIGH state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(FF) and Empty Flag (EF). This requires the ORing of all

EFsandORingofallFFs(i.e. allmustbesettogeneratethe

correct composite FF or EF). See Figure 14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

Foradditionalinformation,refertoTechNote9: Cascading in the FIFO and to increment the write pointer.

FIFOs or FIFO Modules.

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large

FIFO arrays (see Figure 15).

5.04

10

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(HALF–FULL FLAG)

(HF)

WRITE (W)

READ (R)

9

IDT

7203/

7204/

7205/

7206

DATA OUT (Q)

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

EMPTY FLAG (EF)

RETRANSMIT (RT)

EXPANSION IN (XI)

2661 drw 14

Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode

HF

18

9

DATA IN (D)

WRITE (W)

IDT

READ (R)

IDT

7203/

7204/

7205/

7206

FULL FLAG (FF)

RESET (RS)

7203/

7204/

7205/

7206

EMPTY FLAG (EF)

RETRANSMIT (RT)

9

XI

18

_DATAOUT(Q)

2661 drw 15

NOTE:

1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode

5.04

11

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES

TABLE I – RESET AND RETRANSMIT

SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Location Zero

Increment⁽¹⁾

Write Pointer

Location Zero

Unchanged

RS

0

RT

X

XI

0

EF

0

FF

1

HF

1

Reset

Retransmit

1

0

X

Read/Write

1

0

Increment⁽¹⁾

X

NOTE:

2661 tbl 09

1. Pointer will Increment if flag is HIGH.

TABLE II – RESET AND FIRST LOAD

DEPTH EXPANSION/COMPOUND EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Location Zero

X

RS

0

FL

0

XI

EF

0

FF

Reset First Device

Reset all Other Devices

(1)

Location Zero

X

1

X

0

1

0

Read/Write

1

X

NOTES:

2661 tbl 10

1. XI is connected to XO of previous device. See Figure 14.

2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

XO

R

W

D

IDT

FF

9

EF

FL

7203/

7204/

7205/

7206

Q

9

VCC

XI

XO

FF

EF

FL

IDT

EMPTY

FULL

7203/

7204/

7205/

7206

9

XI

XO

FF

EF

IDT

7203/

7204/

7205/

7206

9

RS

FL

XI

2661 drw 16

Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)

5.04

12

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Q0–Q8

Q9 –Q17

Q(N-8) -QN

• • •

Q9 –Q17

IDT7203/

IDT7204/

IDT7205/

IDT7206

DEPTH

EXPANSION

BLOCK

IDT7203/

IDT7204/

IDT7205/

IDT7206

IDT7203/

IDT7204/

IDT7205/

IDT7206

DEPTH

EXPANSION

BLOCK

R, W, RS

DEPTH

• • •

EXPANSION

BLOCK

D0 -D8

D9 -D17

D(N-8)-DN

D0 –DN

D9 -DN

D18 -DN

D(N-8)-DN

2661 drw 17

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

Figure 15. Compound FIFO Expansion

WA

R_B

EF_B

HF_B

IDT

7203/

IDT

7204/

7201A

7205/

FFA

7206

DA 0-8

QB 0-8

SYSTEM A

SYSTEM B

A 0-8

Q

B 0-8

D

IDT

7203/

7204/

7205/

7206

RA

HFA

EFA

WB

FFB

2661 drw 18

Figure 16. Bidirectional FIFO Operation

DATAIN

W

R

t_RPE

EF

t_WEF

t_REF

t _A

t_WLZ

DATA_OUT

DATA VALIDOUT

2661 drw 19

Figure 17. Read Data Flow-Through Mode

5.04

13

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

R

W

t _WPF

t _RFF

FF

t _WFF

t _DH

DATA IN

t_DS

VALID

DATA IN

t

A

DATA OUT

DATA OUT VALID

2661 drw 20

Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

IDT

XXXX

X

XX

X

DeviceType Power

Speed

Package

Process/

Temperature

Range

Blank

B

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

Plastic DIP

P

Plastic THINDIP

TP

D

Ceramic DIP

Ceramic THINDIP (all except 7206)

Plastic Leaded Chip Carrier

Leadless Chip Carrier (Military only)

Small Outline IC (7204 only)

TD

J

L

SO

12

15

20

25

30

35

40

50

65

80

120

Commercial 7203/04 Only

Commercial Only

Military Only

Commercial Only

Military 7203/04 Only

Access Time (tA)

Speed in ns

Military 7203/04DB Only

Standard Power (7203/7204 only)

Low Power

S

L

7203 2048 x 9 FIFO

7204 4096 x 9 FIFO

7205 8192 x 9 FIFO

7206 16384 x 9 FIFO

2661 drw 21

5.04

14


型号：	IDT7206L25TDB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 CMOS异步FIFO 2048× 9 ， 4096 ×9 ， 8192 ×9和16384 ×9 先进先出芯片
文件：	总14页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7206L25TDB [IDT]

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