IDT72125L25SO8_技术文档

IDT72125

CMOS PARALLEL-TO-SERIALFIFO

1,024 x 16

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Theabilitytobufferwidewordwidths(x16)maketheseFIFOsidealforlaser

printers,FAXmachines,localareanetworks(LANs),videostorageanddisk/

tapecontrollerapplications.

Expansioninwidthanddepthcanbeachievedusingmultiplechips. IDT’s

uniqueserialexpansionlogicmakesthispossibleusingaminimumofpins.

Theuniqueserialoutputportisdrivenbyonedatapin(SO)andoneclock

pin(SOCP). TheLeastSignificantorMostSignificantBitcanbereadfirstby

programmingtheDIRpinafterareset.

MonitoringtheFIFOiseasedbytheavailabilityoffourstatusflags:Empty,

Full,Half-FullandAlmost-Empty/Almost-Full. TheFullandEmptyflagsprevent

anyFIFOdataoverfloworunderflowconditions. TheHalf-FullFlagisavailable

inbothsingleandexpansionmodeconfigurations.TheAlmost-Empty/Almost-

Full Flag is available only in a single device mode.

FEATURES:

• 25ns parallel port access time, 35ns cycle time

• 50MHz serial shift frequency

• Wide x16 organization offering easy expansion

• Low power consumption (50mA typical)

• Least/Most Significant Bit first read selected by asserting the

FL/DIR pin

• Four memory status flags: Empty, Full, Half-Full, and Almost-

Empty/Almost-Full

• Dual-Port zero fall-through architecture

• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC

• Green parts available, see ordering information

TheIDT72125isfabricatedusingsubmicronCMOStechnology.

DESCRIPTION:

The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial

FIFO.ThisFIFOfeaturesa16-bitparallelinputportandaserialoutputportwith

1,024worddepths, respectively.

FUNCTIONAL BLOCK DIAGRAM

D0

-15

W

RS

16

RESET

LOGIC

RAM

ARRAY

WRITE

POINTER

READ

POINTER

1,024 x 16

FF

RSIX

EXPANSION

LOGIC

FLAG

LOGIC

EF

HF

AEF

RSOX

FL/DIR

SERIAL OUTPUT

LOGIC

2665 drw01

SOCP

SO

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

COMMERCIALTEMPERATURERANGE

NOVEMBER 2017

1

©

DSC-2665/2

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

PINCONFIGURATION

28

27

26

25

24

23

22

21

20

19

18

17

16

15

W

1

Vcc

D

0

1

2

3

4

5

6

7

2

D

15

14

13

12

11

10

9

3

D

4

5

6

7

8

9

8

RS

SO

SOCP

RSOX/AEF

FL/DIR

EF

FF

10

11

12

13

14

HF

RSIX

GND

2665 drw 02

PLASTIC THIN DIP (P28, order code: TP)

SOIC (SO28, order code: SO)

TOP VIEW

PINDESCRIPTIONS

Symbol

Name

I/O

Description

D0–D15

Inputs

Reset

I

Datainputsfor16-bitwidedata.

RS

W

I

When RSis set low, internal READ and WRITE pointers are set to the first location of the RAM array.

FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up.

W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset.

Write

I

A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold

times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array

sequentially and independently of any ongoing read operation.

SOCP

SerialOutputClock

FirstLoad/Direction

I

A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both

DepthandSerialWordWidthExpansionmodes, alloftheSOCPpinsaretiedtogether.

FL/DIR

This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL)

function is programmed only during Reset (RS) and a LOW on FLindicates the first device to be loaded

with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift

directionafterResetandtellsthedevicewhethertoreadouttheLeastSignificantorMostSignificantbitfirst.

RSIX

SO

Read Serial In

Expansion

I

In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX

is connected to RSOX (expansion out) of the previous device.

SerialOutput

O

Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the

Directionpinprogramming. DuringExpansiontheSOpinsaretiedtogether.

FF

EF

Full Flag

O

When FFgoes LOW, the device is full and further WRITE operations are inhibited. When FFis HIGH,

thedeviceisnotfull.

EmptyFlag

Half-FullFlag

When EFgoes LOW, the device is empty and further READ operations are inhibited. When EFis HIGH,

thedeviceisnotempty.

HF

O

WhenHFisLOW, thedeviceismorethanhalf-full. WhenHFisHIGH, thedeviceisemptytohalf-full.

RSOX/AEF

Read Serial

This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEFoutput pin.

When AEFis LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEFis HIGH, the device

is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX connected to RSIX of the next device) a

pulseissentfromRSOXtoRSIXtocoordinatethewidth, depthordaisychainexpansion.

OutExpansion

Almost-Empty,

Almost-FullFlag

VCC

GND

Power Supply

Ground

Single power supply of 5V.

Single ground of 0V.

2

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

STATUSFLAGS

Number of Words in FIFO

IDT72125

0

FF

H

L

AEF

L

HF

EF

L

H

L

1–127

L

H

128–512

513–896

897–1023

1024

H

L

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

RECOMMENDEDDCOPERATING

CONDITIONS

Symbol

Description

Max

Unit

VTERM Terminal Voltage with

Respect to GND

–0.5 to +7.0

V

Symbol

Parameter

Min. Typ. Max. Unit

VCC SupplyVoltage

GND SupplyVoltage

4.5

0

5.0 5.5

V

TSTG

IOUT

Storage Temperature

DC Output Current

–55 to +125

–50 to +50

°C

0

mA

VIH

InputHIGHVoltage

2

—

V

NOTE:

VIL⁽¹⁾InputLOWVoltage

—

0

0.8

+70

V

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

TA

OperatingTemperature

°C

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0^οC to +70^οC)

IDT72125

Commercial

Symbol

ILI ⁽¹⁾

ILO⁽²⁾

Parameter

Input Leakage Current (Any Input)

OutputLeakageCurrent

OutputLogic"1"VoltageIOUT=–2mA⁽³⁾

OutputLogic"0"VoltageIOUT=8mA⁽⁴⁾

Active Power Supply Current

Min.

–1

Typ.

—

50

4

Max.

Unit

1

10

—

µA

V

–10

2.4

—

VOH

VOL

0.4

100

8

V

ICC1⁽⁵⁾

ICC2^(5,6,7)

—

mA

StandbyCurrent

—

(W = RS = FL/DIR = VIH; SOCP = VIL)

Power Down Current

ICC3^(5,6,7)

—

1

6

mA

NOTES:

1. Measurements with 0.4V ≤ VIN ≤ VCC.

2. SOCP = VIL, 0.4 ≤ VOUT ≤ VCC.

3. For SO, IOUT = -4mA.

4. For SO, IOUT = 16mA.

5. Tested with outputs open (IOUT = 0).

6. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs - VCC - 0.2.

7. Measurements are made after reset.

3

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

ACELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0^οC to +70^οC)

Commercial

IDT72125L25

Max.

Symbol Parameter

Figure

—

Min.

—

Unit

MHz

tS

ParallelShiftFrequency

SerialShiftFrequency

28.5

50

tSOCP

—

PARALLEL INPUT TIMINGS

tWC

tWPW

tWR

tDS

WriteCycleTime

2

35

25

10

12

0

—

35

—

ns

WritePulseWidth

WriteRecoveryTime

DataSet-upTime

2

tDH

DataHoldTime

2

tWEF

tWFF

tWF

Write High to EFHIGH

WriteLowtoFFLOW

WriteLowtoTransitioning HF, AEF

WritePulseWidthAfterFFHIGH

5, 6

4, 7

8

—

25

tWPF

7

SERIAL OUTPUT TIMINGS

tSOCP

tSOCW

tSOPD

SerialClockCycleTime

3

20

8

—

14

35

—

ns

SerialClockWidthHIGH/LOW

SOCPRisingEdgetoSOValidData

3

—

3

(1)

tSOHZ

SOCP Rising Edge to SO at High-Z

3

(1)

tSOLZ

SOCP Rising Edge to SO at Low-Z

SOCP Rising Edge to EFLOW

3

tSOCEF

tSOCFF

tSOCF

tREFSO

5, 6

4, 7

8

—

35

SOCP Rising Edge to FF HIGH

SOCP Rising Edge to Transitioning HF, AEF

SOCP Delay After EF HIGH

6

RESET TIMINGS

tRSC

tRS

ResetCycleTime

1

35

25

10

—

ns

Reset PulseWidth

ResetSet-upTime

Reset Recovery Time

tRSS

tRSR

EXPANSION MODE TIMINGS

tFLS

FL Set-up Time to RS Rising Edge

9

7

0

—

15

—

ns

tFLH

FL Hold Time to RS Rising Edge

tDIRS

tDIRH

tSOXD1

tSOXD2

tSIXS

DIR Set-up Time to SOCP Rising Edge

DIR Hold Time from SOCP Rising Edge

SOCP Rising Edge to RSOX Rising Edge

SOCP Rising Edge to RSOX Falling Edge

RSIX Set-up Time to SOCP Rising Edge

RSIXPulseWidth

10

5

—

5

tSIXPW

10

NOTE:

1. Values guaranteed by design.

4

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

5V

ACTESTCONDITIONS

InputPulseLevels

GND to 3.0V

5ns

InputRise/FallTimes

1.1KΩ

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

1.5V

TO

OUTPUT

1.5V

See Figure A

30pF^*

680Ω

CAPACITANCE(TA = +25°C, f = 1.0 MHz)

2665 drw 03

Symbol

CIN

Parameter⁽¹⁾

Condition

VIN = 0V

Max.

10

Unit

pF

or equivalent circuit

InputCapacitance

OutputCapacitance

Figure A. Output Load

COUT

VOUT = 0V

12

pF

* Includes scope and jig capacitances.

NOTE:

1. Characterized values, not currently tested.

FUNCTIONALDESCRIPTION

PARALLELDATAINPUT

SERIALDATAOUTPUT

Thedevicemustberesetbeforebeginningoperationsothatallflagsare

settotheirinitialstate.InwidthordepthexpansiontheFirstLoadpin(FL)must

beprogrammedtoindicatethefirstdevice.

TheserialdataisoutputontheSOpin.Thedataisclockedoutontherising

edgeofSOCPprovidingtheEmptyFlag(EF)isnotasserted.IftheEmptyFlag

isassertedthenthenextdatawordisinhibitedfrommovingtotheoutputregister

and being clocked out by SOCP.

TheserialwordisshiftedoutLeastSignificantBitorMostSignificantBitfirst,

dependingontheFL/DIRlevelduringoperation.ALOWonDIRwillcausethe

Least Significant Bit to be read out first. A HIGH on DIR will cause the Most

SignificantBittobereadoutfirst.

ThedataiswrittenintotheFIFOinparallelthroughtheD0–D15inputdata

lines. AwritecycleisinitiatedonthefallingedgeoftheWrite(W)signalprovided

theFullFlag(FF)isnotasserted. IftheWsignalchangesfromHIGH-to-LOW

andtheFullFlag(FF)isalreadyset,thewritelineisinternallyinhibitedinternally

fromincrementingthewritepointerandnowriteoperationoccurs.

Dataset-upandholdtimesmustbemetwithrespecttotherisingedgeofWrite.

OntherisingedgeofW,thewritepointerisincremented. Writeoperationscan

occursimultaneouslyorasynchronouslywithreadoperations.

tRSC

tRS

RS

tRSS

tRSR

W

tRSC

FLAG

STABLE

AEF , EF

tRSC

FLAG

STABLE

HF , FF

SOCP

tRSS

tRSR

NOTE 2

tFLS

tFLH

FL/DIR

2665 drw 04

NOTES:

1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.

2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.

Figure 1. Reset

5

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

tWC

tWPW

tWR

W

tDS

tDH

D0-15

2665 drw05

Figure 2. Write Operation

1/tSOCP

0

1

n-1

SOCP

t

SOCW

t

SOCW

SO

(First Device in Width Expansion Mode)

SOHZ

t

t_SOLZ

(Single Device Mode or Second

Device in Width Expansion Mode)

SOPD

t

SO

NOTE:

2665 drw06

1. In Single Device Mode, SO will not tri-state except after reset.

Figure 3. Read Operation

IGNORED

LAST WRITE

FIRST READ

ADDITIONAL READS FIRST WRITE

WRITE

0

1

n-1

0

1

n-1

SOCP

W

tSOCFF

tWFF

FF

2665 drw07

Figure 4. Full Flag from Last Write to First Read

ADDITIONAL

WRITES

FIRST READ

LAST READ

NO READ

FIRST WRITE

W

0

1

n-1

0

1

n-1

NOTE 1

SOCP

EF

tSOCFF

tSOCEF

tSOPD

VALID

SO

NOTE:

1. SOCP should not be clocked until EF goes HIGH.

2665 drw08

Figure 5. Empty Flag from Last Read to First Write

6

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

DATA IN

W

tWEF

tSOCEF

EF

tREFSO

0

1

n-1

NOTE 1

SOCP

tSOPD

tSOLZ

NOTE 2

SO

2665 drw09

2665 drw10

2665 drw11

NOTES:

1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.

Figure 6. Empty Boundary Condition Timing

0

1

n-1

SOCP

FF

tSOCFF

tWFF

tWPF

W

tDS

tDH

DATA IN VALID

DATA IN

SO

t

SOPD

NOTE 1

DATA OUT VALID

NOTE:

1. Single Device Mode will not tri-state but will retain the last valid data.

Figure 7. Full Boundary Condition Timing

W

HF

HALF-FULL (1/2)

HALF-FULL

HALF-FULL + 1

t

SOCF

tWF

SOCP

AEF

t

SOCF

tWF

7/8 FULL

ALMOST-FULL (7/8 FULL + 1)

1/8 FULL

ALMOST-EMPTY

(1/8 FULL-1)

ALMOST-EMPTY

(1/8 FULL-1)

AEF

Figure 8. Half-Full, Almost-Full and Almost-Empty Timings

7

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

RS

15

0

SOCP

tDIRS

tFLS

tFLH

tDIRH

FL/DIR

tSOXD1

tSOXD2

RSOX

t

SIXS

tRSIXPW

RSIX

2665 drw12

Figure 9. Serial Read Expansion

WIDTH EXPANSION MODE

OPERATINGCONFIGURATIONS

In the cascaded case, word widths of more than 16 bits can be achieved

by using more than one device. By tying the RSOX and RSIX pins together,

as shown in Figure 11, and programming which is the Least Significant Device,

a cascaded serial word is achieved. The Least Significant Device is pro-

grammed by a LOW on the FL/DIR pin during reset. All other devices should

be programmed HIGH on the FL/DIR pin at reset.

SINGLE DEVICE MODE

Thedevicemustberesetbeforebeginningoperationsothatallflagsare

set to location zero. In the standalone case, the RSIX line is tied HIGH and

indicatessingledeviceoperationtothedevice.TheRSOX/AEFpindefaultsto

AEFandoutputstheAlmost-EmptyandAlmost-FullFlag.

PARALLEL DATA IN

D0-15

VCC

RSIX

RSOX/AEF

ALMOST-EMPTY/FULL FLAG

SERIAL OUTPUT CLOCK

SOCP

SO

SERIAL DATA OUT

2665 drw13

Figure 10. Single Device Configuration

TABLE 1 — RESET AND FIRST LOAD TRUTH TABLE-

SINGLEDEVICECONFIGURATION

Inputs

InternalStatus

Read Pointer

Outputs

Mode

RS

0

FL

X

DIR

X

Write Pointer

LocationZero

Increment⁽¹⁾

AEF, EF

FF

1

HF

1

Reset

Read/Write

LocationZero

Increment⁽¹⁾

0

1

X

0,1

X

NOTE:

1. Pointer will increment if appropriate flag is HIGH

TheSerialDataOutput(SO)ofeachdeviceintheserialwordmustbetied

together. Since the SO pin is three stated, only the device which is currently

shiftingoutisenabledanddrivingthe1-bitbus.NOTE:Afterreset,thelevelon

theFL/DIRpindecidesiftheLeastSignificantorMostSignificantBitisreadfirst

outofeachdevice.

The three flag outputs, Empty (EF), Half-Full (HF) and Full (FF), should

be taken from the Most Significant Device (in the example, FIFO #2). The

Almost-Empty/Almost-Full flag is not available. The RSOX pin is used for

expansion.

8

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

SERIAL OUTPUT CLOCK

PARALLEL DATA IN

LOW AT RESET

HIGH AT RESET

D

0-15

D16-31

SOCP

FIFO #1

RSOX

FL/DIR

SOCP

FIFO #2

RSOX

FL/DIR

EF

HF

FF

EF

HF

FF

EMPTY FLAG

HALF-FULL FLAG

FULL FLAG

W

RSIX

SO

RSIX

SO

SERIAL DATA OUT

2665 drw14

Figure 11. Width Expansion for 32-bit Parallel Data In

OPERATINGCONFIGURATIONS

SINGLE DEVICE MODE

3. ExternallogicisneededtogeneratecompositeEmpty,Half-FullandFull

TheIDT72125caneasilybeadaptedtoapplicationsrequiringgreaterthan

1,024words. Figure12demonstratesDepthExpansionusingthreeIDT72125s 4. TheAlmost-EmptyandAlmost-FullFlagisnotavailableduetousingthe

Flags. This requires the ORing of all EF, HF and FF Flags.

and an 74FCT138 Address Decoder. Any depth can be attained by adding

additional devices. The Address Decoder is necessary to determine which

RSOX pin for expansion.

FIFOisbeingwritten. AwordofdatamustbewrittensequentiallyintoeachFIFO COMPOUND EXPANSION (DAISY CHAIN) MODE

sothatthedatawillbereadinthecorrectsequence. These devicesoperate TheseFIFOscanbeexpandedinbothdepthandwidthasFigure13indicates:

intheDepthExpansionModewhenthefollowingconditionsaremet:

1. TheRSOX-to-RSIXexpansionsignalsarewrapped aroundsequentially.

1. ThefirstdevicemustbeprogrammedbyholdingFLLOWatReset.Allother 2. The write (W) signal is expanded in width.

devices must be programmed by holding FLHIGH at reset.

3. FlagsignalsareonlytakenfromtheMostSignificantDevices.

2. TheReadSerialOutExpansionpin(RSOX)ofeachdevicemustbetied 4. TheLeastSignificantDeviceinthearraymustbeprogrammedwithaLOW

totheReadSerialInExpansionpin(RSIX)ofthenextdevice(seeFigure

12).

on FL/DIR during reset.

LOW AT RESET

PARALLEL DATA IN

D

0-15

FL/DIR

RSIX

FIFO #1

EF

HF

EMPTY

FLAG

W

FF

SOCP

RSOX

SO

00

01

10

ADDRESS

DECODER

74FCT138

HIGH AT RESET

D0-15

FL/DIR

RSIX

EF

HALF-FULL

FLAG

W

HF

FF

FIFO #2

SERIAL OUTPUT CLOCK

SOCP

RSOX

SO

HIGH AT RESET

D0-15

FL/DIR

RSIX

EF

W

HF

FF

FIFO #3

RSOX

FULL

FLAG

SOCP

SO

SERIAL DATA OUT

2665 drw15

Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125

9

IDT72125PARALLEL-TO-SERIALCMOSFIFO

1,024 x 16

COMMERCIAL TEMPERATURE RANGE

TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE-

WIDTH/DEPTHCOMPOUNDEXPANSIONMODE

Inputs

InternalStatus

Outputs

Mode

RS

0

FL

0

DIR

X

Read Pointer

Write Pointer

LocationZero

X

EF

HF, FF

Reset-FirstDevice

Reset All Other Devices

Read/Write

LocationZero

X

0

X

1

X

0

1

X

1

X

0,1

NOTE:

1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half-Full Flag Output, FF = Full Flag Output.

ADDRESS

DECODER

74FCT138

PARALLEL DATA IN

00 01 10

SERIAL OUTPUT CLOCK

LOW ON RESET

HIGH ON RESET

SOCP

FIFO #1

RSOX

FL/DIR

EF

HF

FF

SOCP

FL/DIR

FIFO #2

RSOX

EF

HF

FF

EMPTY

FLAG

D

0-15

D

16-31

W

RSIX

SO

RSIX

SO

SOCP

FL/DIR

EF

HF

FF

SOCP

FL/DIR

EF

HF

FF

D0-15

D16-31

HALF-FULL

FLAG

FIFO #3

RSOX

FIFO #4

RSOX

W

SOCP

FL/DIR

EF

HF

FF

SOCP

FL/DIR

EF

HF

FF

D0-15

D16-31

FIFO #5

RSOX

FIFO #6

RSOX

FULL

FLAG

W

SERIAL DATA OUT

2665 drw16

Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125

10

ORDERINGINFORMATION

XXXXX

X

XX

X

DeviceType

Package

Power

Speed

Process/

Temperature

Range

Tube or Tray

Tape and Reel

BLANK

8

BLANK

G⁽¹⁾

Commercial (0^OC to +70^OC)

Green

TP

SO

Plastic Thin DIP (300mil, P28)

Small Outline IC (Gull Wing, SOIC, SO28)

Parallel Access Time

(t ) in Nanoseconds

(50 MHz serial shift rate)

Low Power

25

A

L

72125

1,024 x 16-Bit Parallel-to-Serial FIFO

2665 drw17

NOTE:

1. Green parts are available. For specific speeds and packages contact your local sales office.

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

DATASHEETDOCUMENTHISTORY

02/10/2016

11/27/2017

pgs. 1-11.

ProductDiscontinuationNotice-PDN#SP-17-02

Last time buy expires June 15, 2018.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

11


型号：	IDT72125L25SO8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO, 1KX16, 25ns, Synchronous, CMOS, PDSO28, SOIC-28 时钟先进先出芯片光电二极管内存集成电路
文件：	总11页 (文件大小：101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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