IDT72125L25TP [IDT]
CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16; 的CMOS并行到串行的FIFO 256× 16 512× 16 1024×16
| 型号： | IDT72125L25TP |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 文件： | 总12页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72105
IDT72115
IDT72125
CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1024 x 16
Integrated Device Technology, Inc.
FEATURES:
• 25ns parallel port access time, 35ns cycle time
• 45MHz serial output shift rate
• Wide x16 organization offering easy expansion
• Low power consumption (50mA typical)
• Least/Most Significant Bit first read selected by asserting
the FL/DIR pin
• Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, low-
power,dedicated, parallel-to-serial FIFOs. These FIFOs
possessa16-bitparallelinputportandaserialoutputportwith
256, 512 and 1K word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller
applications.
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
Expansion in width and depth can be achieved using
multiple chips. IDT’s unique serial expansion logic makes this
possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/Almost-
Full. TheFullandEmptyflagspreventanyFIFOdataoverflow
orunderflowconditions. TheHalf-FullFlagisavailableinboth
singleandexpansionmodeconfigurations.TheAlmost-Empty/
Almost-Full Flag is available only in a single device mode.
The IDT72105/15/25 are fabricated using IDT’s leading
edge, submicron CMOS technology. Military grade product is
manufactured in compliance with the latest revision of Mil-
STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
D0–15
W
RS
16
RESET
LOGIC
RAM
WRITE
POINTER
ARRAY
256 x 16
512 x 16
1024 x 16
READ
POINTER
FF
RSIX
EXPANSION
LOGIC
FLAG
LOGIC
EF
HF
AEF
RSOX
FL/DIR
SERIAL OUTPUT
LOGIC
2665 drw 01
SOCP
SO
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1996 Integrated Device Technology, Inc.
DSC-2665/6
5.35
1
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W
D0
D1
D2
D3
D4
D5
D6
D7
EF
FF
HF
Vcc
D15
D14
D13
D12
D11
D10
D9
D8
RS
SO
SOCP
RSOX/AEF
FL/DIR
2
3
4
5
6
P28-2
SO28-3
7
8
9
10
11
12
13
RSIX
GND
14
2665 drw 02a
DIP/SOIC
TOP VIEW
PIN DESCRIPTIONS
Symbol
–D15
Name
Inputs
I/O
Description
D
0
I
Data inputs for 16-bit wide data.
Reset
Write
I
When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM
array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE
RS
after power-up.
W must be high during the RS cycle. Also the First Load pin (FL) is programmed
only during Reset.
I
A write cycle is initiated on the falling edge of WRITE if the Full Flag(FF) is not set. Data set-up
and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the
RAM array sequentially and independently of any ongoing read operation.
W
SOCP
FL/DIR
Serial Output
Clock
I
I
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
First Load/
Direction
This is a dual purpose input used in the width and depth expansion configurations. The First
Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first
device to be loaded with a byte of data. All other devices should be programmed HIGH. The
Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the
Least Significant or Most Significant bit first.
RSIX
SO
FF
Read Serial In
Expansion
I
In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain
expansion, RSIX is connected to RSOX (expansion out) of the previous device.
Serial Output
O
O
O
O
O
Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending
on the Direction pin programming. During Expansion the SO pins are tied together.
Full Flag
When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is
HIGH, the device is not full.
Empty Flag
Half-Full Flag
When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is
HIGH, the device is not empty.
EF
When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to
half-full.
HF
RSOX/AEF Read Serial
Out Expansion
Almost-Empty,
Almost-Full
This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF
output pin. When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When
AEF is HIGH, the device is 1/8-full up to 7/8-full. In the Expansion configuration (RSOX
connected to RSIX of the next device) a pulse is sent from RSOX to RSIX to coordinate the
width, depth or daisy chain expansion.
Flag
V
CC
Power Supply
Ground
Single power supply of 5V.
Single ground of 0V.
GND
2665 tbl 01
5.35
2
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
STATUS FLAGS
Number of Words in FIFO
IDT72105
0
IDT72115
0
IDT72125
0
FF
H
H
H
H
H
L
AEF
L
HF
H
H
H
L
EF
L
1–31
1–63
1–127
L
H
H
H
H
H
32–128
129–224
225–255
256
64–256
257–448
449–511
512
128–512
513–896
897–1023
1024
H
H
L
L
L
L
2665 tbl 02
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min. Typ. Max. Unit
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to + 7.0
V
VCC
4.5
0
5.0
0
5.5
0
V
GND
VIH
V
V
T
T
T
A
Operating
Temperature
0 to +70
–55 to +125
–55 to + 125
50
°
°
°
C
C
C
2.0
—
—
—
—
0.8
BIAS
STG
Temperature
Under Bias
(1)
VIL
V
NOTE:
2665 tbl 04
Storage
Temperature
1. 1.5V undershoots are allowed for 10ns once per cycle.
I
OUT
DC Output
Current
mA
NOTE:
2665 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial VCC = 5.0V ± 10%, TA = 0°C to +70°C)
IDT72105/IDT72115/ IDT72125
Commercial
Symbol
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Min.
–1
Typ.
—
Max.
1
Unit
(1)
I
I
IL
µ
A
A
(2)
OL
–10
2.4
—
—
10
—
µ
(5)
V
OH
OL
Output Logic "1" Voltage IOUT = –2mA
—
V
(6)
V
Output Logic "0" Voltage IOUT = 8mA
Power Supply Current
—
0.4
100
8
V
(3)
(3)
I
CC1
CC2
—
50
4
mA
mA
I
Average Standby Current
—
(W = RS = FL/DIR = VIH)(SOCP = VIL
Power Down Current
)
(3,4,7)
ICC3
—
1
6
mA
NOTES:
2665 tbl 05
1. Measurements with 0.4V ≤ VIN ≤ VCC.
2. SOCP = VIL, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open.
4. RS = FL/DIR = W = VCC - 0.2V; SOCP = 0.2V; all other inputs ≥ VCC - 0.2 or ≤ 0.2V.
5. For SO, IOUT = -4mA.
6. For SO, IOUT = 16mA.
7. Measurements are made after reset.
5.35
3
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)
COM'L
72105L25
72115L25
72125L25
72105L50
72115L50
72125L50
Symbol
tS
tSOCP
Parameter
Parallel Shift Frequency
Serial Shift Frequency
Figure
—
Min.
—
Max.
28.5
50
Min.
—
Max.
15
Unit
MHz
MHz
—
—
—
40
PARALLEL INPUT TIMINGS
tWC
Write Cycle Time
2
2
35
25
10
12
0
—
—
—
—
—
35
35
35
—
65
50
15
15
2
—
—
—
—
—
45
45
45
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWPW
tWR
Write Pulse Width
Write Recovery Time
Data Set-up Time
2
tDS
2
tDH
Data Hold Time
2
tWEF
tWFF
tWF
Write High to EF HIGH
Write Low to FF LOW
Write Low to Transitioning HF, AEF
Write Pulse Width After FF HIGH
5, 6
4, 7
8
—
—
—
25
—
—
—
50
tWPF
7
SERIAL OUTPUT TIMINGS
tSOCP
tSOCW
tSOPD
tSOHZ
tSOLZ
Serial Clock Cycle Time
3
3
20
8
—
—
14
14
14
35
35
35
25
10
—
3
—
—
15
15
15
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
Serial Clock Width HIGH/LOW
SOCP Rising Edge to SO Valid Data
SOCP Rising Edge to SO at High-Z(1)
SOCP Rising Edge to SO at Low-Z(1)
SOCP Rising Edge to EF LOW
3
—
3
3
3
3
3
tSOCEF
tSOCFF
tSOCF
5, 6
4, 7
8
—
—
—
—
—
—
SOCP Rising Edge to FF HIGH
SOCP Rising Edge to Transitioning
HF, AEF
tREFSO
SOCP Delay After EF HIGH
6
35
—
65
—
ns
RESET TIMINGS
tRSC
tRS
Reset Cycle Time
1
1
1
1
35
25
25
10
—
—
—
—
65
50
50
15
—
—
—
—
ns
ns
ns
ns
Reset Pulse Width
Reset Set-up Time
Reset Recovery Time
tRSS
tRSR
EXPANSION MODE TIMINGS
tFLS
tFLH
tDIRS
FL Set-up Time to RS Rising Edge
9
9
9
7
0
—
—
—
8
2
—
—
—
ns
ns
ns
FL Hold Time to RS Rising Edge
DIR Set-up Time to SOCP Rising
Edge
10
12
tDIRH
DIR Hold Time from SOCP Rising
Edge
9
9
9
9
9
5
—
—
5
—
15
15
—
—
5
—
17
17
—
—
ns
ns
ns
ns
tSOXD1
tSOXD2
tSIXS
SOCP Rising Edge to RSOX Rising
Edge
—
—
8
SOCP Rising Edge to RSOX Falling
Edge
RSIX Set-up Time to SOCP Rising
Edge
tSIXPW
RSIX Pulse Width
10
15
ns
NOTE:
1. Values guaranteed by design.
2665 tbl 06
5.35
4
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
5V
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.1K
Ω
1.5V
TO
OUTPUT
PIN
1.5V
See Figure A
30pF*
2665 tbl 07
680Ω
CAPACITANCE (TA = +25°C, f = 1.0MHz)
2665 drw 03
Symbol
CIN
Parameter(1)
Conditions
VIN = 0V
Max. Unit
Input Capacitance
10
12
pF
pF
or equivalent circuit
COUT
Output
Capacitance
VOUT = 0V
Figure A. Output Load
NOTE:
2665 tbl 08
*Includes jig and scope capacitances.
1. This parameter is sampled and not 100% tested.
rising edge of Write. On the rising edge of W, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (FL) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the D0–
15 input data lines. A write cycle is initiated on the falling edge
of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the Wsignal changes from HIGH-to-LOW and the
Full Flag (FF) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
isnotasserted.IftheEmptyFlagisassertedthenthenextdata
word is inhibited from moving to the output register and being
clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the FL/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
Data set-up and hold times must be met with respect to the
tRSC
tRS
RS
W
tRSS
tRSR
tRSC
FLAG
AEF, EF
HF, FF
SOCP
FL/DIR
STABLE
tRSC
FLAG
STABLE
t
RSS
tRSR
NOTE 2
tFLS
tFLH
2665 drw 04
NOTES:
1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.
2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 1. Reset
5.35
5
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
t WC
t WPW
t WR
W
D0–15
2665 drw 05
t DS
t DH
Figure 2. Write Operation
1/t SOCP
0
1
n–1
SOCP
t SOCW
t SOCW
SO
(First Device in Width Expansion Mode)
t SOHZ
SO
(Single Device Mode or Second
Device in Width Expansion Mode)
t SOLZ
t SOPD
NOTE:
1. In Single Device Mode, SO will not tri-state except after reset.
2665 drw 06
Figure 3. Read Operation
IGNORED
WRITE
FIRST READ
ADDITIONAL READS FIRST WRITE
LAST WRITE
0
0
1
n–1
1
n–1
SOCP
W
t SOCFF
t WFF
FF
2665 drw 07
Figure 4. Full Flag from Last Write to First Read
ADDITIONAL
LAST READ
NO READ
FIRST WRITE
WRITES
FIRST READ
W
SOCP
EF
0
1
n–1
0
1
n–1
NOTE 1
t SOCEF
t SOCFF
t SOPD
VALID
VALID
VALID
SO
2665 drw 08
NOTE:
1. SOCP should not be clocked until EF goes HIGH.
Figure 5. Empty Flag from Last Read to First Write
5.35
6
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
DATA IN
W
t WEF
t SOCEF
EF
0
1
n–1
t
REFSO
NOTE 1
SOCP
NOTE 2
t
SOLZ
SO
t SOPD
2665 drw 09
NOTE:
1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
Figure 6. Empty Boundary Condition Timing
0
1
n–1
SOCP
FF
t SOCFF
t WFF
t WPF
W
t DS
t DH
DATA IN
SO
DATA IN VALID
t SOPD
NOTE 1
NOTE 1
DATA OUT VALID
2665 drw 10
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
Figure 7. Full Boundary Condition Timing
W
HF
HALF-FULL (1/2)
HALF-FULL
HALF-FULL + 1
t WF
t SOCF
SOCP
AEF
t WF
t SOCF
7/8 FULL
7/8 FULL
ALMOST-FULL (7/8 FULL + 1)
1/8 FULL
ALMOST-EMPTY
(1/8 FULL – 1)
ALMOST-EMPTY
(1/8 FULL – 1)
AEF
2665 drw 11
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
5.35
7
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
RS
15
0
SOCP
t FLS
t FLH
t DIRS
t DIRH
FL/DIR
RSOX
RSIX
t SOXD1
t SOXD2
t SIXS
t RSIXPW
2665 drw 12
Figure 9. Serial Read Expansion
Width Expansion Mode
OPERATING CONFIGURATIONS
In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the
RSOX and RSIX pins together, as shown in Figure 11, and
programming which is the Least Significant Device, a cas-
caded serial word is achieved. The Least Significant Device
is programmed by a LOW on the FL/DIR pin during reset. All
other devices should be programmed HIGH on theFL/DIR pin
at reset.
Single Device Mode
The device must be reset before beginning operation so
that all flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single device opera-
tion to the device. The RSOX/AEF pin defaults to AEF and
outputs the Almost-Empty and Almost-Full Flag.
PARALLEL DATA IN
D0–15
Vcc
RSIX
RSOX/AEF
SO
ALMOST-EMPTY/FULL FLAG
SERIAL DATA OUT
2665 drw 13
SERIAL OUTPUT CLOCK
SOCP
Figure 10. Single Device Configuration
5.35
8
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
Outputs
Inputs
Internal Status
RS
0
FL
X
FF
1
HF
1
Mode
DIR
X
Read Pointer Write Pointer
Location Zero Location Zero
,
AEF EF
Reset
0
Read/Write
1
X
0,1
Increment(1)
Increment(1)
X
X
X
NOTE:
2665 tbl 09
1. Pointer will increment if appropriate flag is HIGH.
Table 1. Reset and First Load Truth Table–Single Device Configuration
The Serial Data Output (SO) of each device in the serial Bit is read first out of each device.
word must be tied together. Since the SO pin is three stated,
The three flag outputs, Empty (EF), Half-Full (HF) and
only the device which is currently shifting out is enabled and Full (FF), should be taken from the Most Significant Device (in
driving the 1-bit bus. NOTE: After reset, the level on the the example, FIFO #2). The Almost-Empty/Almost-Full flag is
FL/DIR pin decides if the Least Significant or Most Significant not available. The RSOX pin is used for expansion.
SERIAL OUTPUT CLOCK
PARALLEL DATA IN
LOW AT RESET
HIGH AT RESET
D0–15
W
D16–31
SOCP
FIFO #1
RSOX
FL/DIR
SO
SOCP
FIFO #2
RSOX
FL/DIR
SO
EF
HF
FF
EF
HF
FF
EMPTY FLAG
HALF-FULL FLAG
FULL FLAG
W
RSIX
RSIX
SERIAL DATA OUT
2665 drw 14
Figure 11. Width Expansion for 32-bit Parallel Data In
Depth Expansion (Daisy Chain) Mode
The IDT72105/15/25 can easily be adapted to applications
requiring greater than 1024 words. Figure 12 demonstrates
3. External logic is needed to generate composite Empty,
Half-Full and Full Flags. This requires the OR-ing of all EF,
HF and FF Flags.
Depth Expansion using three IDT72105/15/25s and an 4. The Almost-Empty and Almost-Full Flag is not available
IDT74FCT138 Address Decoder. Any depth can be attained
by adding additional devices. The Address Decoder is neces-
sary to determine which FIFO is being written. A word of data
must be written sequentially into each FIFO so that the data
will be read in the correct sequence. The IDT72105/15/25
operates in the Depth Expansion Mode when the following
conditions are met:
due to using the RSOX pin for expansion.
Compound Expansion (Daisy Chain) Mode
The IDT72105/15/25 can be expanded in both depth and
width as Figure 13 indicates:
1. The RSOX-to-RSIX expansion signals are wrapped
around sequentially.
2. The write (W) signal is expanded in width.
3. Flag signals are only taken from the Most Significant
Devices.
1. The first device must be programmed by holding FL LOW
atReset.Allotherdevicesmustbeprogrammedbyholding
FL HIGH at reset.
2. TheReadSerialOutExpansionpin(RSOX)ofeachdevice
must be tied to the Read Serial In Expansion pin (RSIX) of
the next device (see Figure 12).
4. The Least Significant Device in the array must be
programmed with a LOW on FL/DIR during reset.
5.35
9
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
LOW AT RESET
FL/DIR
PARALLEL DATA IN
D0–15
RSIX
FIFO #1
EF
EMPTY
FLAG
W
HF
FF
SOCP
RSOX
SO
00
01
10
ADDRESS
DECODER
74FCT138
HIGH AT RESET
D0–15
FL/DIR
EF
RSIX
HALF-FULL
FLAG
W
FIFO #2
HF
FF
SERIAL OUTPUT CLOCK
SOCP
RSOX
SO
HIGH AT RESET
D0–15
FL/DIR
EF
RSIX
W
HF
FF
FIFO #3
RSOX
FULL
FLAG
SOCP
SO
SERIAL DATA OUT
2665 drw 15
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
Inputs
Internal Status
Outputs
RS
FL
EF
Mode
Reset-First Device
Reset All Other Devices
Read/Write
DIR
X
Read Pointer
Write Pointer
Location Zero
Location Zero
X
,
HF FF
0
0
1
0
1
Location Zero
Location Zero
X
0
0
1
1
X
X
0,1
X
X
NOTE:
2665 tbl 10
1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.
Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode
5.35
10
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGE
ADDRESS
DECODER
74FCT138
PARALLEL DATAIN
00 01 10
SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET
SOCP
FL/DIR
FIFO #1
RSOX
EF
HF
FF
SOCP
FL/DIR
FIFO #2
RSOX
EF
HF
FF
EMPTY
FLAG
D0–15
W
D16–31
W
RSIX
SO
SO
SO
RSIX
SO
SO
SO
SOCP
FL/DIR
SOCP
EF
HF
FF
FL/DIR
EF
HF
FF
D0–15
W
D16–31
W
HALF-FULL
FLAG
FIFO #3
RSOX
FIFO #4
RSOX
RSIX
RSIX
SOCP
FL/DIR
EF
HF
FF
SOCP
FL/DIR
EF
HF
FF
D0–15
W
D16–31
W
FIFO #5
RSOX
FIFO #6
RSOX
FULL
FLAG
RSIX
RSIX
SERIAL DATA
OUT
2665 drw 16
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
5.35
11
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
X
X
XXXXX
X
X
Package
Device
Type
Power
Speed
Process/
Temperature
Range
Commercial (0°C to +70°C)
BLANK
TP
SO
Plastic THINDIP (300mil)
Small Outline (Gull Wing)
Commercial only
Parallel Access
Time (tA) in ns
25
50
(50 MHz serial shift rate)
(40MHz serial shift rate)
L
Low Power
72105
72115
72125
256 x 16-Bit Parallel-to-Serial FIFO
512 x 16-Bit Parallel-to-Serial FIFO
1024 x 16-Bit Parallel-to-Serial FIFO
2665 drw 17
5.35
12
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