IDT7216L45CB [IDT]
16 x 16 PARALLEL CMOS MULTIPLIERS; 16 ×16并行CMOS乘
| 型号： | IDT7216L45CB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 16 x 16 PARALLEL CMOS MULTIPLIERS |
| 文件： | 总13页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7216L
IDT7217L
16 x 16 PARALLEL
CMOS MULTIPLIERS
Integrated Device Technology, Inc.
FEATURES:
• 16 x 16 parallel multiplier with double precision product
• 16ns clocked multiply time
• Low power consumption: 120mA
• Produced with advanced submicron CMOS high perfor-
mance technology
• IDT7216L is pin- and function compatible with TRW
MPY016H/K and AMD Am29516
• IDT7217L requires a single clock with register enables
making it pin- and function compatible with AMD
Am29517
• Configured for easy array expansion
• User-controlled option for transparent output register
mode
DESCRIPTION:
The IDT7216/IDT7217 are high-speed, low-power
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications. Utilization of a modified Booths
algorithm and IDT’s high-performance, submicron CMOS
technology,hasachievedspeedscomparabletobipolar(20ns
max.), at 1/10 the power consumption.
The IDT7216/IDT7217 are ideal for applications requiring
high-speed multiplication such as fast Fourier transform
analysis, digital filtering, graphic display systems, speech
synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are
inadequate.
All input registers, as well as LSP and MSP output regis-
ters, use the same positive edge-triggered D-type flip-flop. In
the IDT7216, there are independent clocks (CLKX, CLKY,
CLKM, CLKL) associated with each of these registers. The
IDT7217hasonlyasingleclockinput(CLK)andthreeregister
enables. ENX and ENY control the two input registers, while
ENP controls the entire product.
• Round control for rounding the MSP
• Input and output directly TTL-compatible
• Three-state output
• Available in Top Braze, DIP, PLCC, Flatpack and Pin
Grid Array
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86873 is listed on this
function for IDT7216 and Standard Military Drawing
#5962-87686 is listed for this function for IDT7217.
• Speeds available: Commercial: L16/20/25/35/45/55/65
TheIDT7216/IDT7217offeradditionalflexibilitywiththeFA
control and MSPSEL functions. The FA control formats the
output for two’s complement by shifting the MSP up one bit
and then repeating the sign bit in the MSB of the LSP. The
Military:
L20/25/30/40/55/65/75
FUNCTIONAL BLOCK DIAGRAMS
IDT7216
IDT7217
XM X15-0
16
RND
YM Y15-0/P15-0
16
XM X15-0
RND
YM Y15-0/P15-0
16
16
XREGISTER
REGISTER
YREGISTER
XREGISTER
REGISTER
YREGISTER
CLKY
CLKX
CLK
ENX
OEL
OEL
ENY
MULTIPLIER
MULTIPLIER
ARRAY
ARRAY
FA
FT
FORMAT ADJUST
FA
FT
FORMAT ADJUST
MSP
REGISTER REGISTER
16 16
LSP
MSP
REGISTER REGISTER
16 16
LSP
CLKM
CLKL
ENP
MULTIPLEXER
MULTIPLEXER
MSPSEL
OEP
MSPSEL
OEP
16
16
PRODUCT
PRODUCT
2580 drw 01
2580 drw 02
MSPOUT (P31 - P16)
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
MSPOUT (P31 - P16)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc.
11.3
DSC-2023/6
1
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Cont’d.)
The IDT7216/IDT7217 multipliers are manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.
MSPSEL low selects the MSP to be available at the product
output port, while a high selects the LSP to be available.
Keeping this pin low will ensure compatibility with the TRW
MPY016H.
PIN CONFIGURATIONS
IDT7216
IDT7217
X4
X3
X2
X1
X0
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
X5
X4
X3
X2
X1
X0
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
X5
2
X6
2
X6
3
X7
3
X7
4
X8
4
X8
5
X9
5
X9
X10
X11
X12
X13
X14
X15
CLKX
RND
XM
X10
X11
X12
X13
OEL
6
OEL
CLK
ENY
6
CLKL
7
7
CLKY
8
8
P0, Y0
P1, Y1
P2, Y2
P3, Y3
P4, Y4
9
9
P0, Y0
P1, Y1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X14
P2, Y2
P3, Y3
P4, Y4
X15
ENX
RND
P5, Y5
P5, Y5
XM
P6, Y6
P6, Y6
YM
YM
C64-2
C64-2
P7, Y7
VCC
VCC
GND
GND
P7, Y7
VCC
P8, Y8
P8, Y8
VCC
P9, Y9
P9, Y9
GND
GND
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P14, Y14
P15, Y15
MSPSEL
FT
FA
OEP
CLKM
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
MSPSEL
FT
FA
OEP
ENP
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P0, P16
P0, P16
P1, P17
P1, P17
39
38
37
36
35
34
33
39
38
37
36
35
34
33
P2, P18
P3, P19
P2, P18
P3, P19
P4, P20
P5, P21
P6, P22
P7, P23
P4, P20
P5, P21
P6, P22
P7, P23
2580 drw 03
2580 drw 04
64-PIN DIP
TOP VIEW
64-PIN DIP
TOP VIEW
11.3
2
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
IDT7216/IDT7217
11
10
09
08
07
06
05
04
03
02
01
NC
X12
X10
X8
X13
X14
X15 RND YM
VCC GND FT OEP
CLKM
or
ENP*
CLKX
or
ENX*
MSP-
SEL
X11
X9
X7
X5
X3
X1
XM
VCC GND
FA
NC
P30,
P14
P31,
P15
P28,
P12
P29,
P13
P26,
P10
P27,
P11
X6
P24,
P8
P25,
P9
X4
G68-2
P22,
P6
P23,
P7
X2
P20,
P4
P21,
P5
OEL X0
CLKY CLKL
P18,
P2
P19,
P3
or
or
CLK*
ENY*
Y0,
P0
Y2,
P2
Y4,
P4
Y6,
P6
Y8,
P8
Y10,
P10
Y12, Y14,
P12 P14
P16,
P0
P17,
P1
NC
Y1,
P1
Y3,
P3
Y5,
P5
Y7,
P7
Y9,
P9
Y11,
P11
Y13, Y15,
NC
K
P13
P15
Pin 1
Designator
A
B
C
D
E
F
G
H
J
L
*Pin designation for IDT7217
2580 drw 05
PGA
TOP VIEW
11.3
3
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
IDT7216
IDT7217
64636261 605958575655 545352515049
64636261605958575655 545352 515049
X12
X11
X10
P15, P31
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
P6, P22
P5, P21
P4, P20
P3, P19
P2, P18
P1, P17
P0, P16
X12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
P15, P31
47 X11
46 X10
45 X9
P14, P30
P13, P29
P12, P28
P11, P27
P10, P26
P9, P25
P8, P24
P7, P23
45 X9
44
X8
44
X8
43
X7
43
X7
42 X6
41 X5
40 X4
39 X3
38 X2
42 X6
41 X5
40 X4
39 X3
38 X2
F64-1
F64-1
P6, P22
P5, P21
37
36 X0
35
37
36 X0
35
X1
X1
P4, P20
P3, P19
P2, P18
OEL
OEL
34 CLKL
34 CLK
P1, P17
P0, P16
33
33
CLKY
ENY
17181920 212223242526 272829303132
17181920212223242526 272829 303132
2580 drw 06
2580 drw 07
64-LEAD FLATPACK
TOP VIEW
64-LEAD FLATPACK
TOP VIEW
IDT7216
IDT7217
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
60 59 58 5756 5554 535251 50 4948 47 46 45 44
X
13 61
14 62
15 63
43
42
41
40
39
38
NC
X13 61
X14 62
X15 63
43
42
NC
X
P
P
P
P
P
P
P
P
P
0
, Y
, Y
, Y
, Y
, Y
, Y
, Y
, Y
, Y
0
1
2
3
4
5
6
7
P0, Y0
X
1
2
3
4
5
6
7
41 P1, Y1
40 P2, Y2
39 P3, Y3
CLKX 64
RND 65
64
ENX
RND65
XM 66
X
Y
M 66
38
P4, Y4
67
M
37
36
35
34
67
VCC68
YM
37 P5, Y5
V
VCCCC 68
36
35
34
P6, Y6
P7, Y7
P8, Y8
1
J68-1
VCC
GND
GND 3
1
2
J68-1
GND
GND
2
3
4
5
6
33 P8
9
, Y8
9
33 P9, Y9
32
P10, Y10
P11, Y11
P12, Y12
P13, Y13
P , Y
MSPSEL
FT
32
4
P10, Y10
MSPSEL
31
30
29
FT 5
FA 6
7
31 P11, Y11
FA
30
29
P12, Y12
P13, Y13
7
8
OEP
OEP
CLKM
27 P1145, Y1154
28
8
28 P14, Y14
27 P15, Y15
ENP
NC
9
NC 9
10 1112 13 14 1516 17 1819 20 212223 24 25 26
10 1112 13 14 1516 171819 20 2122 23 24 25 26
2580 drw 09
2580 drw 08
PLCC
PLCC
TOP VIEW
TOP VIEW
11.3
4
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
X0 - X15
I/O
I
Description
Data Inputs
Y0 - Y15/
P0 - P15
P16 - P31
I/O
Y0 - Y15 are data inputs
P0 - P15 are LSP register output, enabled when OEL = 0
Data Output (LSP or MSP)
O
I
OEL
Output enable control for LSP (least significant product). When low enables P0 - P15. When high P0 - P15
tristated.
OEP
I
I
I
Output enable control for MSP (most significant product). When low enables P16 - P31. When high P16 -
P31 tristated.
XM, YM
RND
Mode control for each data word. Low designates unsigned data input and high designates two's
complement.
"Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This
signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When
RND = 1 and FA = 0, 1 is added to the 2-16 bit (P14). The RND input is registered. It is clocked on the
rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217.
Rounding always occurs in the positive direction which may introduce a systematic bias.
When low, MSP is output on P16 - P31 lines. When high, LSP is output on P16 - P31.
MSPSEL
FA
I
I
Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product
is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's
complement applications (see multiplier input / output formats).
FT
I
I
I
I
I
I
I
I
Flow through control. When high, both MSP and LSP registers are by-passed.
CLK
7217 X, Y, RND, LSP and MSP register clock input.
7216 X register clock input. Also clocks RND register.
7216 Y register clock input. Also clocks RND register.
7216 LSP register clock input.
CLKX
CLKY
CLKL
CLKM
ENX
7216 MSP register clock input.
7217 X register clock enable. Also enables RND register clock.
7217 Y register clock enable. Also enables RND register clock.
ENY
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
CIN
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
Max. Unit
10
12
pF
pF
VCC
Power Supply
Voltage
–0.5 to +7.0 –0.5 to +7.0
V
COUT
VOUT = 0V
VTERM
Terminal Voltage
with Respect to
GND
VCC + 0.5
0 to +70
VCC + 0.5
V
NOTE:
2580 tbl 04
1. This parameter is measured at characterization and not tested.
TA
Operating
Temperature
Temperature
Under Bias
Storage
–55 to +125 °C
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
DC Output
Current
IOUT
50
50
mA
NOTE:
2580 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
11.3
5
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Min. Typ.(1) Max.
Military
Min. Typ.(1) Max.
Symbol
VIH
Parameter
Input High Voltage
Test Conditions(1)
Unit
V
Guaranteed Logic High Level
Guaranteed Logic Low Level
VCC = Max., VIN = 0 to VCC
2.0
—
—
—
—
—
—
—
—
0.8
10
10
2.0
—
—
—
—
—
—
—
—
0.8
10
10
VIL
Input Low Voltage
V
|ILI|
Input Leakage Current
Output Leakage Current
µA
µA
|ILO|
VCC = Max., OE = 2.0V
VOUT = 0 to VCC
ICC
Operating Power Supply Current
VCC = Max., Outputs Disabled
f = 10MHz(2)
—
40
80
—
40
100
mA
ICCQ1
ICCQ2
Quiescent Power Supply Current
Quiescent Power Supply Current
VIN ≥ VIH, VIN ≤ VIL
—
—
—
20
4
40
20
4
—
—
—
20
4
50
25
6
mA
mA
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
ICC/f(2,3) Increase in Power Supply
Current
VCC = Max., Outputs Disabled
—
—
mA/
MHz
V
VOH
Output HIGH Voltage
Output LOW Voltage
VCC = Min., IOH = –2.0mA
VCC = Min., IOL = 8mA
VCC = Max., VO = GND
2.4
—
—
—
—
—
2.4
—
—
—
—
—
(4)
VOL
0.4
0.4
V
IOS
Output Short Circuit Current
-20
-120
-20
-120
mA
NOTES:
2580 tbl 03
1. Typical implies VCC = 5V and TA = +25°C.
2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
ICC = 80+ 4(f –10)mA; for the military range, ICC = 100 + 6(f –10). f = operating frequency in MHz, f = 1/tMUC for IDT7216 and f = 1/tMC for IDT7217.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. IOL = 4mA for tMC >65ns.
11.3
6
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C)
7216L16(5)
7217L16
7216L20
7217L20
7216L25
7217L25
7216L35
7217L35
Symbol
tMUC
tMC
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, Y, RND Set-up Time
Min.
Max. Min.
Max. Min.
Max. Min.
Max. Unit
2
2
25
16
—
—
—
—
15
15
15
15
15
—
—
—
2
2
30
20
—
—
—
—
18
18
18
18
18
—
—
—
2
2
38
25
—
—
—
—
20
20
20
20
20
—
—
—
2
2
55
35
—
—
—
—
25
25
25
25
22
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS
10
1
11
1
12
2
12
3
tH
X, Y, RND Hold Time
tPWH
tPWL
tPDSEL
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P(4)
7
9
10
10
2
10
10
2
7
9
2
2
tPDP
tPDY
tENA
tDIS
tS
2
2
2
2
Output Clock to Y(4)
2
2
2
2
3-State Enable Time
3-State Disable Time(2)
—
—
9
—
—
10
0
—
—
10
2
—
—
10
3
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
tH
tHCL
0
0
Clock Low Hold Time CLKXY
0
0
0
Relative to CLKML (IDT7216 only)(1,3)
7216L45
7217L45
7216L55
7217L55
7216L65
7217L65
Symbol
tMUC
tMC
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, Y, RND Set-up Time
Min.
Max.
Min.
Max.
Min.
Max. Unit
2
2
65
45
—
—
—
—
25
25
25
25
22
—
—
—
2
2
75
55
—
—
—
—
25
30
30
30
25
—
—
—
2
2
85
65
—
—
—
—
30
30
30
35
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS
15
3
20
3
20
3
tH
X, Y, RND Hold Time
tPWH
tPWL
tPDSEL
Clock Pulse Width High
15
15
2
15
20
2
15
20
2
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P(4)
Output Clock to Y(4)
tPDP
tPDY
tENA
tDIS
tS
2
2
2
2
2
2
3-State Enable Time
3-State Disable Time(2)
—
—
10
3
—
—
10
3
—
—
10
3
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only)(1,3)
tH
tHCL
0
0
0
NOTES:
2580 tbl 06
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and PLCC packages only.
11.3
7
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C)
7216L20(5)
7217L20
7216L25
7217L25
7216L30
7217L30
7216L40
7217L40
Symbol
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, Y, RND Set-up Time
Min.
2
Max. Min.
Max. Min.
Max. Min.
Max. Unit
tMUC
tMC
tS
30
30
—
—
—
—
18
18
18
18
20
—
—
—
2
2
38
25
—
—
—
—
20
20
20
20
22
—
—
—
2
2
43
30
—
—
—
—
20
20
20
20
22
—
—
—
2
2
60
40
—
—
—
—
25
25
25
25
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
11
1
12
2
12
2
15
3
tH
X, Y, RND Hold Time
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
Clock Pulse Width High
Clock Pulse Width Low
MSPSEL to Product Out(4)
Output Clock to P(4)
9
10
10
2
10
10
2
15
15
2
9
2
2
2
2
2
Output Clock to Y(4)
2
2
2
2
3-State Enable Time
3-State Disable Time(2)
—
—
10
0
—
—
10
2
—
—
10
2
—
—
12
3
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
tH
tHCL
Clock Low Hold Time CLKXY Relative to
CLKML (IDT7216 only)(1,3)
0
0
0
0
7216L55
7217L55
7216L65
7217L65
7216L75
7217L75
Symbol
Parameter
Unclocked Multiply Time(4)
Clocked Multiply Time(4)
X, Y, RND Set-up Time
Min.
Max.
Min.
2
Max.
85
65
—
Min.
2
Max. Unit
tMUC
tMC
tS
2
2
75
55
—
—
—
—
30
30
30
25
25
—
—
—
95
75
—
—
—
—
35
35
35
40
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
20
3
25
3
25
3
tH
X, Y, RND Hold Time
—
tPWH
tPWL
tPDSEL
tPDP
tPDY
tENA
tDIS
tS
Clock Pulse Width High
15
15
2
15
15
2
—
15
15
2
Clock Pulse Width Low
—
MSPSEL to Product Out(4)
Output Clock to P(4)
Output Clock to Y(4)
35
30
30
35
25
—
2
2
2
2
2
2
3-State Enable Time
3-State Disable Time(2)
—
—
15
3
—
—
15
3
—
—
15
3
Clock Enable Set-up Time (IDT7217 only)
Clock Enable Hold Time (IDT7217 only)
tH
—
tHCL
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only)(1,3)
0
0
—
0
NOTES:
2580 tbl 07
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and Flatpack packages only.
11.3
8
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tPWH
tHCL
CLKX
CLKY
tS
tH
tPWL
INPUT X1, Y1,
RND
tMC
CLKM
CLKL
tPDY
OUTPUT Y
CLKM
CLKL
tPDSEL
tPDP
MSPSEL
OUTPUT P
tMUC
2580 drw 13
Figure 4. IDT7216 Timing Diagram
tPWH
tH
CLK
tS
tS
tPWL
ENX
ENY
tH
X1, Y1,
RND
tS
tH
ENP
tMC
tPDY
OUTPUT Y
tPDSEL
tPDP
MSPSEL
OUTPUT P
tMUC
Figure 5. IDT7217 Timing Diagram
2580 drw 14
11.3
9
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11.3
10
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11.3
11
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11.3
12
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
VCC
7.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
500Ω
500Ω
1.5V
VOUT
VIN
Pulse
Generator
See Figure 1
D.U.T.
2580 tbl 08
50pF
C L
SWITCH POSITION
RT
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests
Open
Figure 12. AC Test Load Circuit
DEFINITIONS:
2580 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
VCC
ESD
PROTECTION
IOH
IIH
OUTPUTS
INPUTS
R
IIL
IOL
Figure 13. Input Interface Circuit
Figure 14. Output Interface Circuit
ORDERING INFORMATION
IDT
XXXX
X
X
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
C
J
F
G
Topbraze DIP
Plastic Leaded Chip Carrier
Flatpack
Pin Grid Array
16
20
25
35
45
55
65
20
25
30
40
55
65
75
Commercial (tMC)
Military (tMC)
L
Low Power
7216
7217
16 x 16 Multiplier
2580 drw 22
11.3
13
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