IDT72245LB10J8 [IDT]
FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | IDT72245LB10J8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 4KX18, 6.5ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68 先进先出芯片 |
| 文件： | 总16页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72205LB, IDT72215LB,
IDT72225LB, IDT72235LB,
IDT72245LB
writecontrols.TheseFIFOsareapplicableforawidevarietyofdatabuffering
needs, such as optical disk controllers, Local Area Networks (LANs), and
interprocessorcommunication.
FEATURES:
• 256 x 18-bit organization array (IDT72205LB)
• 512 x 18-bit organization array (IDT72215LB)
• 1,024 x 18-bit organization array (IDT72225LB)
• 2,048 x 18-bit organization array (IDT72235LB)
• 4,096 x 18-bit organization array (IDT72245LB)
• 10 ns read/write cycle time
TheseFIFOshave18-bitinputandoutputports.Theinputportiscontrolled
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).
Thereadclockcanbetiedtothewriteclockforsingleclockoperationorthe
twoclockscanrunasynchronousofoneanotherfordual-clockoperation. An
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof
theoutput.
Thesynchronous FIFOs havetwofixedflags,Empty (EF)andFull(FF),
andtwoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF).The
offsetloadingoftheprogrammableflagsiscontrolledbyasimplestatemachine,
andisinitiatedbyassertingtheLoadpin(LD). AHalf-Fullflag(HF)isavailable
when the FIFO is used in a single device configuration.
ThesedevicesaredepthexpandableusingaDaisy-Chaintechnique.The
XI andXO pins are usedtoexpandthe FIFOs. Indepthexpansionconfigu-
ration, FirstLoad(FL)is groundedonthe firstdevice andsettoHIGHforall
other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated
usingIDT’shigh-speedsubmicronCMOStechnology.
• Empy and Full flags signal FIFO status
• Easy expandable in depth and width
• Asynchronous or coincident read and write clocks
• Programmable Almost-Empty and Almost-Full flags with
default settings
• Half-Full flag capability
• Dual-Port zero fall-through time architecture
• Output enable puts output data bus in high-impedence state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LBare very high
speed,low-powerFirst-In,First-Out(FIFO)memorieswithclockedreadand
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
INPUT REGISTER
OFFSET REGISTER
FLAG
WRITE CONTROL
LOGIC
•
•
LOGIC
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
)
READ POINTER
WRITE POINTER
•
•
READ CONTROL
LOGIC
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
2766 drw 01
RCLK
Q0-Q17
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
OCTOBER 2006
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2766/1
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN CONFIGURATIONS
9 8 7 6 5 4 3 2
6867666564636261
60
V
Q
Q
GND
Q
Q
CC
D
D
D
D
D
14
13
12
11
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
14
13
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
12
11
D
9
VCC
VCC
Q
Q
GND
Q
10
9
D
GND
8
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
8
Q
7
VCC
Q
Q
GND
Q
6
5
4
2728 2930 3132 3334 3536 3738 3940 4142 43
2766 drw 02
PLCC (J68-1, order code: J)
TOP VIEW
PIN 1
61
50
64
63
62
60
59
58
57
56
55
54
53
52
51
49
D
D
D
D
D
D
15
14
13
12
11
10
48
47
46
45
44
43
42
41
40
39
38
37
36
Q
Q
GND
14
13
1
2
3
4
5
6
7
8
Q
Q
12
11
V
CC
D
D
9
8
7
6
5
4
3
2
1
Q
Q
10
9
D
D
D
D
D
D
D
GND
9
Q8
Q7
Q6
Q5
10
11
12
13
14
15
16
GND
35
34
33
Q4
D
0
VCC
2766 drw 03
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
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OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
Name
I/O
Description
D0–D17 DataInputs
I
I
Datainputs fora18-bitbus.
RS
Reset
WhenRSissetLOW,internalreadandwritepointersaresettothefirstlocationoftheRAMarray,FFandPAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I
I
WhenWENisLOW,dataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLK,iftheFIFOisnotfull.
WEN
WriteEnable
WhenWEN is LOWandLDis HIGH, data is writtenintothe FIFOoneveryLOW-to-HIGHtransitionof
WCLK.WhenWENisHIGH,theFIFOholdsthepreviousdata.DatawillnotbewrittenintotheFIFOiftheFF
isLOW.
RCLK
ReadClock
I
I
WhenRENisLOW,dataisreadfromtheFIFOonaLOW-to-HIGHtransitionofRCLK,iftheFIFOisnotempty.
REN
ReadEnable
WhenRENis LOW, andLDis HIGH,datais readfromtheFIFOoneveryLOW-to-HIGHtransitionofRCLK.
WhenRENis HIGH,theoutputregisterholds theprevious data.DatawillnotbereadfromtheFIFOiftheEF
isLOW.
OE
LD
OutputEnable
Load
I
I
WhenOEisLOW,thedataoutputbusisactive.IfOEisHIGH,theoutputdatabuswillbeinahigh-impedance
state.
WhenLDisLOW,dataontheinputsD0–D11iswrittentotheoffsetanddepthregistersontheLOW-to-HIGH
transitionoftheWCLK,whenWENisLOW.WhenLD isLOW,dataontheoutputsQ0–Q11isreadfromthe
offsetanddepthregistersontheLOW-to-HIGHtransitionoftheRCLK, whenRENisLOW.
FL
FirstLoad
I
I
Inthesingledeviceorwidthexpansionconfiguration,FLisgrounded.Inthedepthexpansionconfiguration,FL
is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXI
RXI
FF
WriteExpansion
ReadExpansion
Full Flag
Inthesingledeviceorwidthexpansionconfiguration,WXIisgrounded.Inthedepthexpansionconfiguration,
WXIis connectedtoWXO(WriteExpansionOut)ofthepreviousdevice.
I
Inthesingledeviceorwidthexpansionconfiguration,RXIisgrounded.Inthedepthexpansionconfiguration,
RXI is connected to RXO (Read Expansion Out) of the previous device.
O
O
O
WhenFFisLOW,theFIFOisfullandfurtherdatawritesintotheinputareinhibited.WhenFFisHIGH,theFIFO
is notfull.FF is synchronizedtoWCLK.
EF
EmptyFlag
WhenEFisLOW,theFIFOisemptyandfurtherdatareadsfromtheoutputareinhibited.WhenEFisHIGH,the
FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
Almost-EmptyFlag
WhenPAEisLOW,theFIFOisalmostemptybasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetis 31fromemptyforIDT72205LB,63fromemptyforIDT72215LB,and127fromemptyfor
IDT72225LB/72235LB/72245LB.
PAF
Programmable
Almost-FullFlag
O
O
WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffsetat
resetis 31fromfullforIDT72205, 63fromfullforIDT72215LB, and127fromfullforIDT72225LB/72235LB/
72245LB.
WXO/HF WriteExpansion
Inthesingledeviceorwidthexpansionconfiguration,thedeviceismorethanhalffullwhenHFisLOW.Inthe
depthexpansionconfiguration,apulseissentfromWXOtoWXIofthenextdevicewhenthelastlocationinthe
FIFOiswritten.
Out/Half-FullFlag
RXO
ReadExpansion
Out
O
O
Inthe depthexpansionconfiguration, a pulse is sentfromRXO toRXI ofthe nextdevice whenthe last
locationinthe FIFOis read.
Q0–Q17 DataOutputs
Dataoutputsforan18-bitbus.
VCC
Power
+5V power supply pins.
GND
Ground
Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP.
3
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTERM
TerminalVoltage
–0.5to+7.0
V
VCC
SupplyVoltage
4.5
5.0
5.5
V
with respect to GND
Commercial/Industrial
TSTG
Storage
Temperature
–55to+125
–50to+50
°C
GND
VIH
SupplyVoltage
0
0
0
V
V
InputHighVoltage
2.0
—
—
IOUT
DCOutputCurrent
mA
Commercial/Industrial
NOTES:
(1)
VIL
InputLowVoltage
Commercial/Industrial
—
0
—
—
⎯
0.8
70
85
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
OperatingTemperature
Commercial
°C
°C
TA
OperatingTemperature
Industrial
-40
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%V, TA = -40°C to +85°C)
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
(1)
Commercial and Industrial
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
1
Unit
(2)
ILI
InputLeakageCurrent(anyinput)
OutputLeakageCurrent
µA
µA
V
(3)
ILO
–10
2.4
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
—
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
—
—
60
5
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial Temperature Range Product for the 15ns and the 25ns speed grades are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. For the IDT72205/72215/72225 the typical ICC1 = 1.81 + 1.12*fS + 0.02*CL*fS (in mA);
for the IDT72235/72245 the typical ICC1 = 2.85 + 1.30*fS + 0.02*CL*fS (in mA)
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
4
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Commercial
Commercial & Industrial(1)
IDT72205LB10
IDT72215LB10
IDT72225LB10
IDT72235LB10
IDT72245LB10
IDT72205LB15
IDT72205LB25
IDT72215LB25
IDT72225LB25
IDT72235LB25
IDT72245LB25
IDT72215LB15
IDT72225LB15
IDT72235LB15
IDT72245LB15
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
Max.
40
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
20
—
8
—
tA
DataAccessTime
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
2
15
—
—
—
—
—
—
—
—
—
—
25
—
12
12
15
15
26
26
26
15
—
—
—
—
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
25
10
10
6
6
DataSet-upTime
4
tDH
DataHoldTime
0
1
1
tENS
tENH
tRS
EnableSet-upTime
EnableHoldTime
ResetPulseWidth(2)
ResetSet-upTime
ResetRecoveryTime
ResettoFlagandOutputTime
3
4
6
0
1
1
10
8
15
10
10
—
0
25
15
15
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
8
—
0
(3)
OutputEnabletoOutputinLow-Z
OutputEnabletoOutputValid
—
6
3
3
3
(3)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
OutputEnabletoOutputinHigh-Z
Write Clock to Full Flag
3
6
3
8
3
—
—
—
—
—
—
3
6.5
6.5
17
—
—
—
—
—
—
6.5
5
10
10
24
24
24
10
—
—
—
—
—
—
—
—
—
—
10
10
10
10
Read Clock to Empty Flag
ClocktoAsynchronousProgrammableAlmost-FullFlag
Clockto Programmable Almost-EmptyFlag
ClocktoHalf-FullFlag
17
17
tXO
Clock to Expansion Out
6.5
—
—
—
—
tXI
ExpansionInPulse Width
tXIS
ExpansionInSet-UpTime
3.5
5
tSKEW1
Skew time between Read Clock & Write Clock forFull Flag
Skew time between Read Clock & Write Clock for Empty Flag
6
(2)
tSKEW2
5
6
NOTES:
1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
30pF*
680Ω
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
3ns
1.5V
1.5V
SeeFigure1
2766 drw 04
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
Figure 1. Output Load
* Includes jig and scope capacitances.
5
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OUTPUTENABLE(OE)
SIGNALDESCRIPTIONS:
WhenOutputEnable (OE)is enabled(LOW), the paralleloutputbuffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
INPUTS:
DATA IN (D0 - D17)
Datainputsfor18-bitwidedata.
LOAD (LD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
taintwo12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs.
WhentheLoad(LD)pinissetLOWandWENissetLOW,dataontheinputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transitionofthe Write Clock(WCLK). WhentheLD pinand(WEN)are held
LOWthendataiswrittenintotheFullOffsetregisteronthesecondLOW-to-HIGH
transitionof(WCLK).Thethirdtransitionofthewriteclock(WCLK)againwrites
totheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,
andWENisLOW,thenextoffsetregisterinsequenceiswritten.
CONTROLS:
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
Duringreset,bothinternalreadandwritepointersaresettothefirstlocation.
Aresetisrequiredafterpower-upbeforeawriteoperationcantakeplace.The
FullFlag(FF),Half-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)
will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable
Almost-EmptyFlag(PAE)willberesettoLOWaftertRSF. Duringreset,theoutput
registerisinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
LD
WEN
WCLK
Selection
Writingtooffsetregisters:
EmptyOffset
0
0
The Write andReadClocks canbe asynchronous orcoincident.
FullOffset
WRITE ENABLE (WEN)
0
1
1
0
1
NoOperation
WhentheWENinput isLOWandLDinputisHIGH,datamaybeloadedinto
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
notfull. DataisstoredintheRAMarraysequentiallyandindependentlyofany
ongoingreadoperation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.
Uponthecompletionofavalidreadcycle,FFwillgoHIGHallowingawriteto
occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored
whenthe FIFOis full.
WriteIntoFIFO
NoOperation
1
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK),whenOutputEnable(OE) is setLOW.
The Write andReadClocks canbe asynchronous orcoincident.
17
17
0
11
11
EMPTY OFFSET REGISTER
READ ENABLE (REN)
WhenReadEnableisLOWandLDinputisHIGH,dataisloadedfromthe
RAM array into the output register on the rising edge of every RCLK cycle if
thedeviceisnotempty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
0
FULL OFFSET REGISTER
Every word accessed at Qn, including the first word written to an empty
FIFO,mustberequestedusingREN. Whenthelastwordhasbeenreadfrom
theFIFO,theEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
goHIGHallowinga readtooccur. The EFflagis updatedonthe risingedge
ofRCLK.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
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OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EMPTY FLAG/ (EF)
Whenthe LD pinis LOWandWEN is HIGH, the WCLKinputis disabled;
thenasignalatthisinputcanneitherincrementthewriteoffsetregisterpointer,
nor execute a write.
Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe
LD pinis setLOWandRENis setLOW;then,datacanbereadontheLOW-
to-HIGH transition of the read clock (RCLK). The act of reading the control
registersemploysadedicatedreadoffsetregisterpointer.(Thereadandwrite
pointersoperateindependently).
WhentheFIFOisempty,EFwillgoLOW,inhibitingfurtherreadoperations.
When EF is HIGH, the FIFOis notempty.
TheEFisupdatedontheLOW-to-HIGHtransitionofthereadclock(RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW when FIFO
reachestheAlmost-Fullcondition. IfnoreadsareperformedafterReset(RS),
thePAFwillgoLOWafter(256-m)writesfortheIDT72205LB,(512-m)writes
fortheIDT72215LB,(1,024-m)writesfortheIDT72225LB,(2,048–m)writes
fortheIDT72235LBand(4,096–m)writesfortheIDT72245LB. Theoffset“m”
isdefinedintheFULLoffsetregister.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FL)
IfthereisnoFulloffsetspecified,thePAFwillbeLOWwhenthedeviceis
31awayfromcompletelyfullforIDT72205LB,63awayfromcompletelyfullfor
IDT72215LB,and127awayfromcompletelyfullforIDT72225LB/72235LB/
72245LB.
FLisgroundedtoindicateoperationintheSingleDeviceorWidthExpansion
mode.IntheDepthExpansionconfiguration,FLisgroundedtoindicateitisthe
firstdeviceloadedandissettoHIGHforallotherdevicesintheDaisyChain.
(SeeOperatingConfigurationsforfurtherdetails.)
ThePAFisassertedLOWontheLOW-to-HIGHtransitionofthewriteclock
(WCLK).PAFisresettoHIGHontheLOW-to-HIGHtransitionofthereadclock
(RCLK). Thus PAF is asynchronous.
WRITE EXPANSION INPUT (WXI)
Thisisadualpurposepin. WXIisgroundedtoindicateoperationintheSingle
DeviceorWidthExpansionmode.WXIisconnectedtoWriteExpansionOut
(WXO) of the previous device in the Daisy Chain Depth Expansion mode.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-EmptyFlag(PAE)willgoLOWwhentheread
pointeris"n+1"locationslessthanthewritepointer.Theoffset"n"isdefinedin
theEMPTYoffsetregister.
IfthereisnoEmptyoffsetspecified,theProgrammableAlmost-EmptyFlag
(PAE) will be LOW when the device is 31 away from completely empty for
IDT72205LB,63awayfromcompletelyemptyforIDT72215LB,and127away
fromcompletelyemptyforIDT72225LB/72235LB/72245LB.
ThePAEisassertedLOWontheLOW-to-HIGHtransitionofthereadclock
(RCLK).PAEisresettoHIGHontheLOW-to-HIGHtransitionofthewriteclock
(WCLK). Thus PAE is asynchronous.
READ EXPANSION INPUT (RXI)
Thisisadualpurposepin.RXIisgroundedtoindicateoperationintheSingle
DeviceorWidthExpansionmode.RXI isconnectedtoReadExpansionOut
(RXO) of the previous device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG(FF)
WhentheFIFOis full,FF willgoLOW,inhibitingfurtherwriteoperations.
WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformedafterareset,
FFwillgoLOWafterDwritestotheFIFO. D=256writesfortheIDT72205LB,
512fortheIDT72215LB,1,024fortheIDT72225LB,2,048fortheIDT72235LB
and 4,096 for the IDT72245LB.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
Thisisadual-purposeoutput.IntheSingleDeviceandWidthExpansion
mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are
grounded,thisoutputactsasanindicationofahalf-fullmemory.
TheFFisupdatedontheLOW-to-HIGHtransitionofthewriteclock(WCLK).
TABLE 1 — STATUS FLAGS
Number of Words in FIFO
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FF PAF HF PAE EF
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
(n + 1) to 128
129 to (256-(m+1))
(256-m)(2) to255
256
(n + 1) to 256
257 to (512-(m+1))
(n + 1) to 512
513 to (1,024-(m+1))
(1,024-m)(2) to1,023
1,024
(n + 1) to 1,024
1,025 to (2,048-(m+1))
(2,048-m)(2) to2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m)(2) to4,095
4,096
H
H
H
H
(2)
(512-m) to511
512
L
NOTES:
1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127)
2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)
7
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext READ EXPANSION OUT (RXO)
writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference
In the Daisy Chain Depth Expansion configuration, Read Expansion In
betweenthewritepointerandreadpointeris less thanorequaltoonehalfof (RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This
thetotalmemoryofthedevice.TheHalf-FullFlag(HF)is thenresettoHIGH outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is whenthepreviousdevicereadsfromthelastlocationofmemory.
asynchronous.
IntheDaisyChainDepthExpansion mode,WXIisconnectedtoWXOof DATAOUTPUTS(Q0-Q17)
thepreviousdevice. ThisoutputactsasasignaltothenextdeviceintheDaisy
Chainbyprovidingapulsewhenthepreviousdevicewritestothelastlocation
ofmemory.
Q0-Q17aredataoutputs for18-bitwidedata.
tRS
t
RSR
tRSS
t
RSF
t
t
RSF
RSF
,
,
(1)
= 1
Q0 - Q17
2766 drw 06
= 0
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing(2)
8
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
tCLKL
WCLK
tDH
tDS
D0 - D17
DATA IN VALID
t
ENH
t
ENS
NO OPERATION
t
WFF
t
WFF
(1)
t
SKEW1
RCLK
2766 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
t
CLK
t
CLKH
tCLKL
RCLK
t
ENS
tENH
NO OPERATION
REF
t
t
REF
t
A
Q0
- Q17
VALID DATA
tOLZ
tOHZ
t
OE
(1)
t
SKEW2
WCLK
2766 drw 08
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
9
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tDS
D0 (first valid write)
D0
- D17
D1
D2
D3
D4
t
ENS
(1)
tFRL
t
SKEW2
RCLK
tREF
tENS
tA
tA
Q0 - Q17
D0
D1
tOLZ
t OE
2766 drw 09
NOTES:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
NO WRITE
(1)
NO WRITE
(1)
WCLK
SKEW1
SKEW1
t
t
DS
DS
t
t
DATA
D0 - D17
WRITE
DATA WRITE
WFF
WFF
WFF
t
t
t
RCLK
ENS
t
ENS
ENH
t
t
ENH
t
LOW
A
A
t
t
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2766 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 8. Full Flag Timing
10
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tDS
tDS
DATA WRITE 1
DATA WRITE 2
D0 - D17
tENS
tENS
tENH
tENH
(1)
(1)
tFRL
tFRL
tSKEW2
tSKEW2
RCLK
tREF
tREF
tREF
LOW
tA
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
2766 drw 11
NOTE:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
tCLK
tCLKH
tCLKL
WCLK
t
ENS
ENS
tENH
LD
t
WEN
tDS
tDH
PAE OFFSET
D0–D15
2766 drw 12
D0–D11
PAE OFFSET
PAF OFFSET
Figure 10. Write Programmable Registers
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
tENS
tA
PAE OFFSET
UNKNOWN
PAE OFFSET
PAF OFFSET
Q0–Q15
2766 drw 13
Figure 11. Read Programmable Registers
11
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
tPAE
n + 1 words in FIFO
n words in FIFO
tPAE
RCLK
tENS
2766 drw 14
NOTE:
1. n = PAE offset. Number of data words written into FIFO already = n.
Figure 12. Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
(1)
tENH
tENS
tPAF
D – m words
D – m + 1 words in FIFO memory (1)
(2)
D – m + 1 words
in FIFO memory
in FIFO memory(1)
tPAF
RCLK
tENS
NOTES:
2766 drw 15
1. m = PAF offset. D = maximum FIFO Depth. Number od data words written into FIFO memory = 256 - m + 1 for the IDT72205LB, 512 - m + 1 for the IDT72215LB,
1,024 - m + 1 for the IDT72225LB, 2,048 - m + 1 for the IDT72235LB and 4,096 - m + 1 for the IDT72245LB.
2. 256 - m words for the IDT72205LB, 512 - m words for the IDT72215LB, 1,024 - m words for the IDT72225LB, 2,048 - m words for the IDT72235LB and 4,096 - m words for
the IDT72245LB.
Figure 13. Programmable Almost-Full Flag Timing
tCLKH
tCLKL
WCLK
tENH
tENS
tHF
D/2 + 1 words in
FIFO memory(2)
D/2 words in FIFO memory(1)
D/2 words in
FIFO memory(1)
tHF
RCLK
tENS
2766 drw 16
NOTES:
1. D = maximum FIFO Depth = 256 words for the IDT72205LB, 512 words for the IDT72215LB, 1,024 words for the IDT72225LB, 2,048 words for the IDT72235LB and 4,096 words
for the IDT72245LB.
Figure 14. Half-Full Flag Timing
12
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLKH
WCLK
Note 1
t
XO
t
XO
tENS
2766 drw 17
NOTE:
1. Write to Last Physical Location.
Figure 15. Write Expansion Out Timing
t
CLKH
RCLK
Note 1
t
XO
t
XO
t
ENS
2766 drw 18
NOTE:
1. Read from Last Physical Location.
Figure 16. Read Expansion Out Timing
t
XI
t
XIS
WCLK
2766 drw 19
Figure 17. Write Expansion In Timing
t
XI
t
XIS
RCLK
2766 drw 20
Figure 18. Read Expansion In Timing
13
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
orless. TheseFIFOsareinasingleDeviceConfigurationwhentheFirstLoad
(FL), Write ExpansionIn(WXI)andReadExpansionIn(RXI) controlinputs
are grounded (Figure 19).
OPERATINGCONFIGURATIONS
SINGLE DEVICE CONFIGURATION
AsingleIDT72205LB/72215LB/72225LB/72235LB/72245LBmaybeused
whentheapplicationrequirementsarefor256/512/1,024/2,048/4,096words
RESET (
)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE
LOAD
)
READ ENABLE
)
)
OUTPUT ENABLE
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
DATA IN (D
0
- D17
)
DATA OUT (Q
0
- Q17
)
FULL FLAG (
)
EMPTY FLAG
)
PROGRAMMABLE (
HALF-FULL FLAG (
)
PROGRAMMABLE
)
)
2766 drw 21
READ EXPANSION IN
WRITE EXPANSION IN (
)
FIRST LOAD (
)
)
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
composite flags by ANDing the Empty Flags of every FIFO, and separately
ANDingallFullFlags.Figure20demonstrates a36-wordwidthbyusingtwo
IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Any word width can
beattainedbyaddingadditionalIDT72205LB/72215LB/72225LB/72235LB/
72245LBs.PleaseseetheApplicationNoteAN-83.
Word width may be increased simply by connecting together the control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEmptyFlagandFullFlag. Becauseofvariationsinskew
betweenRCLKandWCLK,itispossibleforflagassertionanddeassertionto
vary by one cycle between FIFOs. To avoid problems the user must create
RESET
)
RESET
)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE
LOAD
READ ENABLE
OUTPUT ENABLE
PROGRAMMABLE
)
)
)
)
)
72205LB
72215LB
72225LB
72235LB
72245LB
PROGRAMMABLE
HALF FULL FLAG
)
72205LB
72215LB
72225LB
72235LB
72245LB
)
EMPTY FLAG (
)
18
DATA OUT (Q)
36
FULL FLAG (
)
18
FIRST LOAD
WRITE EXPANSION IN (
READ EXPANSION IN
)
2766 drw 22
)
)
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
14
OCTOBER2,2006
IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DEPTH EXPANSION CONFIGURATION —
(WITH PROGRAMMABLE FLAGS)
3. TheWriteExpansionOut(WXO)pinofeachdevicemustbetiedto
the Write Expansion In (WXI) pin of the next device. See Figure 21.
4.The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 21.
5.All Load (LD) pins are tied together.
6.The Half-Full Flag (HF) is not available in this Depth Expansion
Configuration.
7.EF, FF, PAE, and PAF are created with composite flags by ORing
togethereveryrespectiveflags formonitoring.ThecompositePAE
and PAF flags are not precise.
Thesedevicescaneasilybeadaptedtoapplicationsrequiringmorethan256/
512/1,024/2,048/4,096wordsofbuffering. Figure21 showsDepthExpansion
usingthreeIDT72205LB/72215LB/72225LB/72235LB/72245LBs. Maximum
depthis limitedonlybysignalloading. Followthesesteps:
1. The first device must be designated by grounding the First Load (FL)
control input.
2. Allotherdevices musthave FL inthe HIGHstate.
WCLK
RCLK
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
Dn
Qn
Vcc
WCLK
RCLK
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
Dn
DATA OUT
DATA IN
Qn
Vcc
WRITE CLOCK
WRITE ENABLE
RESET
WCLK
Dn
READ CLOCK
RCLK
Qn
READ ENABLE
OUTPUT ENABLE
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
LOAD
FIRST LOAD (
)
2766 drw 23
Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
15
OCTOBER2,2006
ORDERING INFORMATION
XXXXX
Device Type Power
X
XX
Speed
X
X
X
IDT
Package
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
J
PF
TF
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
10
15
25
Commercial Only
Commercial & Industrial
Commercial & Industrial
Clock Cycle Time (tCLK
)
Speed in Nanoseconds
Low Power
LB
72205
72215
72225
72235
72245
256 x 18 Synchronous FIFO
512 x 18 Synchronous FIFO
1,024 x 18 Synchronous FIFO
2,048 x 18 Synchronous FIFO
4,096 x 18 Synchronous FIFO
2766 drw24
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
10/02/2006
pgs. 1 and 16.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1533
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
16
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