IDT72245LB10PF [IDT]
CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18; CMOS SyncFIFOO 256 ×18 ， 512 ×18 ， 1024× 18 ， 2048× 18和4096 ×18
| 型号： | IDT72245LB10PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| 文件： | 总16页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18 and 4,096 x 18
Integrated Device Technology, Inc.
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
FEATURES:
• 256 x 18-bit organization array (IDT72205LB)
• 512 x 18-bit organization array (IDT72215LB)
• 1,024 x 18-bit organization array (IDT72225LB)
• 2,048 x 18-bit organization array (IDT72235LB)
• 4,096 x 18-bit organization array (IDT72245LB)
• 10 ns read/write cycle time
• Empty and Full flags signal FIFO status
• Easily expandable in depth and width
• Asynchronous or coincident read and write clocks
• Programmable Almost-Empty and Almost-Full flags with
default settings
These FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and an input
enable pin (WEN). Data is read into the synchronous FIFO on
everyclockwhenWEN isasserted.Theoutputportiscontrolled
byanotherclockpin(RCLK)andanotherenablepin(REN).The
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual-clock operation. An Output Enable pin (OE) is
provided on the read port for three-state control of the output.
ThesynchronousFIFOshavetwofixedflags,Empty(EF)and
Full (FF), and two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF). The offset loading of the programmable
flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (LD). A Half-Full flag (HF) is available
when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain
technique. The XI and XO pins are used to expand the FIFOs.
In depth expansion configuration, FL is grounded on the first
deviceandsettoHIGHforallotherdevicesintheDaisyChain.
TheIDT72205LB/72215LB/72225LB/72235LB/72245LBis
fabricated using IDT’s high-speed submicron CMOS technol-
ogy.
• Half-Full flag capability
• Dual-Port zero fall-through time architecture
• Output enable puts output data bus in high-impedance
state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
INPUT REGISTER
OFFSET REGISTER
FLAG
WRITE CONTROL
LOGIC
•
•
LOGIC
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
)
READ POINTER
WRITE POINTER
•
•
READ CONTROL
LOGIC
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
2766 drw 01
RCLK
Q0-Q17
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 2000
©2000 Integrated Device Technology, Inc.
DSC-2766/-
1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
PIN CONFIGURATIONS
9 8 7 6 5 4 3 2
6867666564636261
60
V
Q
Q
GND
Q
Q
CC
D
D
D
D
D
14
13
12
11
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
14
13
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
12
11
D
9
VCC
VCC
Q
Q
GND
Q
10
9
D
GND
8
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
8
Q
7
VCC
Q
Q
GND
Q
6
5
4
2728 2930 3132 3334 3536 3738 3940 4142 43
2766 drw 02
PLCC (J68-1, order code: J)
TOP VIEW
PIN 1
61
56
50
63
62
60
59
58
57
54
53
52
51
64
55
49
D
D
D
D
D
D
15
14
13
12
11
10
48
47
46
45
44
43
42
41
40
39
38
37
36
Q
Q
GND
14
13
1
2
3
4
5
6
7
8
Q
Q
12
11
V
CC
D
D
9
8
7
6
5
4
3
2
1
Q
Q
GND
Q
Q
Q
Q
10
9
D
D
D
D
D
D
D
9
8
7
6
5
10
11
12
13
14
15
16
GND
Q
VCC
35
34
33
4
D
0
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
2766 drw 03
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
PIN DESCRIPTION
Symbol
D0–D17
RS
Name
Data Inputs
Reset
I/O
Description
I
I
Data inputs for a 18-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the
RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an
initial WRITE after power-up.
WCLK
WEN
Write Clock
I
I
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,
if the FIFO is not full.
Write Enable
When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH
transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be
written into the FIFO if the FF is LOW.
RCLK
REN
Read Clock
I
I
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the
FIFO is not empty.
Read Enable
When REN is LOW and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH
transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will
not be read from the FIFO if the EF is LOW.
OE
LD
Output Enable
Load
I
I
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will
be in a high-impedance state.
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers
on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW,
data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-
HIGH transition of the RCLK, when REN is LOW.
FL
First Load
I
Inthesingledeviceorwidthexpansionconfiguration, FLisgrounded. Inthedepthexpansion
configuration, FLisgroundedonthefirstdevice(firstloaddevice)andset toHIGHforallother
devices in the Daisy Chain.
WXI
RXI
FF
Write Expansion
Read Expansion
Full Flag
I
In the single device or width expansion configuration, WXI is grounded. In the depth
expansion configuration, WXIis connected to WXO (Write Expansion Out) of the previous device.
I
Inthesingledeviceorwidthexpansionconfiguration, RXIisgrounded. Inthedepthexpansion
configuration, RXI is connected to RXO (Read Expansion Out) of the previous device.
O
O
O
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.
EF
Empty Flag
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.
When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
PAE
Programmable
Almost-Empty Flag
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the
FIFO. The default offset at reset is 31 from empty for IDT72205LB, 63 from empty for
IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB.
PAF
Programmable
Almost-Full Flag
O
O
When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO.
The default offset at reset is 31 from full for IDT72205LB, 63 from full for IDT72215LB, and
127 from full for IDT72225LB/72235LB/72245LB.
WXO/HF
RXO
Write Expansion
Out/Half-Full Flag
In the single device or width expansion configuration, the device is more than half full
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to
WXI of the next device when the last location in the FIFO is written.
Read Expansion
Out
O
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device
when the last location in the FIFO is read.
Q0–Q17
VCC
Data Outputs
Power
Data outputs for a 18-bit bus.
+5V power supply pins.
GND
Ground
Eight ground pins for the PLCC and seven pins for the TQFP/STQFP.
3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC
Symbol
Rating
Com'l & Ind'l
Unit
OPERATING CONDITIONS
VTERM
Terminal Voltage
–0.5 to +7.0
V
Symbol
Parameter
Min.
Typ. Max. Unit
with respect to GND
VCC
Supply Voltage
Com'l/Ind'l
4.5
5.0
5.5
V
TSTG
Storage
Temperature
–55 to +125
–50 to +50
°C
GND Supply Voltage
0
0
0
V
V
IOUT
DC Output Current
mA
VIH
Input High Voltage
Com'l/Ind'l
2.0
—
—
NOTE:
2766 tbl 02
(1)
VIL
Input Low Voltage
Com'l/Ind'l
—
0
—
—
—
0.8
70
85
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
TA
Operating Temperature
Commercial
°C
TA
Operating Temperature
Industrial
–40
°C
NOTE:
2766 tbl 03
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C )
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
Commercial and Industrial(1)
tCLK = 10, 15, 25 ns
Symbol
Parameter
Input Leakage Current (any input)
Output Leakage Current
Min.
–1
Typ.
—
Max.
1
Unit
µA
µA
V
(2)
ILI
(3)
ILO
–10
2.4
—
—
10
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
—
0.4
V
(4,5,6)
ICC1
Active Power Supply Current
Standby Current
—
—
—
—
60
5
mA
mA
(4,7)
ICC2
2766 tbl 04
NOTES:
1. Industrial temperature range product for the 15ns and the 25 ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. For the 72205/72215/72225 the typical ICC1 = 1.81 + 1.12*fS + 0.02*CL*fS (in mA);
for the 72235/72245 the typical ICC1 = 2.85 + 1.30*fS + 0.02*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
AC TEST CONDITIONS
Input Pulse Levels
Symbol Parameter(1)
Conditions
Max.
Unit
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
1.5V
1.5V
(1,2)
COUT
Output
Capacitance
VOUT = 0V
10
pF
See Figure 1
2766 tbl 06
NOTES:
2766 tbl 05
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
4
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
(1)
Commercial
Com'l & Ind'l
72205LB10
72215LB10
72225LB10
72235LB10
72245LB10
72205LB15
72205LB25
72215LB25
72225LB25
72235LB25
72245LB25
72215LB15
72225LB15
72235LB15
72245LB15
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Min. Max. Min. Max. Min. Max. Unit
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
20
—
8
—
2
40
15
—
—
—
—
—
—
—
—
—
—
25
—
12
12
15
15
26
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
25
10
10
6
Clock HIGH Time
Clock LOW Time
6
Data Set-up Time
4
tDH
Data Hold Time
0
1
1
tENS
tENH
tRS
Enable Set-up Time
3
4
6
Enable Hold Time
Reset Pulse Width(2)
0
1
1
10
8
15
10
10
—
0
25
15
15
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(3)
Output Enable to Output Valid
Output Enable to Output in High-Z(3)
Write Clock to Full Flag
Read Clock to Empty Flag
8
—
0
3
3
3
tOHZ
tWFF
tREF
tPAF
3
6
3
8
3
—
—
—
6.5
6.5
17
—
—
—
10
10
24
—
—
—
Clock to Programmable Almost-Full
Flag
tPAE
Clock to Programmable Almost-Empty
Flag
—
17
—
24
—
26
ns
tHF
tXO
tXI
Clock to Half-Full Flag
—
—
3
17
6.5
—
—
—
6.5
5
24
10
—
—
—
—
—
10
10
10
26
15
—
—
—
ns
ns
ns
ns
ns
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
tXIS
3.5
5
—
tSKEW1 Skew time between Read Clock &
Write Clock for Full Flag
—
6
tSKEW2 Skew time between Read Clock &
Write Clock for Empty Flag
5
—
6
—
10
—
ns
NOTES:
2766 tbl 07
1. Industrial temperature range is available as standard product for the 15ns
and the 25ns speed grade.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
30pF*
680Ω
2766 drw 04
Figure 1. Output Load
* Includes jig and scope capacitances.
5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
OUTPUT ENABLE (OE)
SIGNAL DESCRIPTIONS:
When Output Enable (OE) is enabled (LOW), the parallel
output buffers receive data from the output register. When OE
is disabled (HIGH), the Q output data bus is in a high-
impedance state.
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
LOAD (LD)
CONTROLS:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
devices contain two 12-bit offset registers with data on the
inputs, or read on the outputs. When the Load (LD) pin is set
LOW and WEN is set LOW, data on the inputs D0-D11 is
writtenintotheEmptyoffsetregisteronthefirstLOW-to-HIGH
transition of the write clock (WCLK). When the LD pin and
(WEN) are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK). The third transition of the write clock (WCLK)
again writes to the Empty offset register.
However, writing all offset registers does not have to occur
atonetime. Oneortwooffsetregisterscanbewrittenandthen
by bringing the LD pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and WEN
is LOW, the next offset register in sequence is written.
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and
write pointers are set to the first location. A reset is required
after power-up before a write operation can take place. The
Full Flag (FF), Half-Full Flag (HF) and Programmable Almost-
Full Flag (PAF) will be reset to HIGH after tRSF. The Empty
Flag(EF)andProgrammableAlmost-EmptyFlag(PAE)willbe
reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the
writeclock(WCLK). Dataset-upandholdtimesmustbemetwith
respecttotheLOW-to-HIGHtransitionofthewriteclock(WCLK).
Thewriteandreadclockscanbeasynchronousorcoincident.
LD
0
WEN
0
WCLK
Selection
Writing to offset registers:
Empty Offset
WRITE ENABLE (WEN)
When the WEN input is LOW and LD input is HIGH, data
may be loaded into the FIFO RAM array on the rising edge of
every WCLK cycle if the device is not full. Data is stored in the
RAM array sequentially and independently of any ongoing
read operation.
When WEN is HIGH, no new data is written in the RAM
array on each WCLK cycle.
To prevent data overflow, FF will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, FF
will go HIGH allowing a write to occur. The FFflag is updated on
the rising edge of WCLK. WENis ignored when the FIFO is full.
Full Offset
0
1
1
0
1
No Operation
Write Into FIFO
No Operation
1
NOTE:
2766 tbl 08
1. The same selection sequence applies to reading from the registers. REN
is enabled and read is performed on the LOW-to-HIGH transition of
RCLK.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransition
of the read clock (RCLK), when Output Enable (OE) is set LOW.
Thewriteandreadclockscanbeasynchronousorcoincident.
Figure 2. Write Offset Register
17
0
11
EMPTY OFFSET REGISTER
READ ENABLE (REN)
When Read Enable is LOW and LD input is HIGH, data is
loaded from the RAM array into the output register on the
rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the
previous data and no new data is loaded into the output
register. The data outputs Q0-Qn maintain the previous data
value.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
11
17
0
FULL OFFSET REGISTER
Every word accessed at Qn, including the first word written
to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF)
willgoLOW,inhibitingfurtherreadoperations. RENisignored
when the FIFO is empty. Once a write is performed, EFwill go
HIGH allowing a read to occur. The EFflag is updated on the
rising edge of RCLK.
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
6
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
EMPTY FLAG (EF)
WhentheLDpinisLOWandWEN isHIGH,theWCLKinput
isdisabled;thenasignalatthisinputcanneitherincrementthe
write offset register pointer, nor execute a write.
The contents of the offset registers can be read on the
output lines when the LD pin is set LOW and REN is set LOW;
then, data can be read on the LOW-to-HIGH transition of the
read clock (RCLK). The act of reading the control registers
employs a dedicated read offset register pointer. (The read
and write pointers operate independently).
When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty.
The EF is updated on the LOW-to-HIGH transition of the
read clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW
when FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (RS), the PAFwill go LOW after (256-m)
writes for the IDT72205LB, (512-m) writes for the IDT72215LB,
(1,024-m) writes for the IDT72225LB, (2,048–m) writes for the
IDT72235LB and (4,096–m) writes for the IDT72245LB. The
offset “m” is defined in the FULL offset register.
IfthereisnoFulloffsetspecified,thePAFwillbeLOWwhen
the device is 31 away from completely full for IDT72205LB, 63
awayfromcompletelyfullforIDT72215LB,and127awayfrom
completely full for IDT72225LB/72235LB/72245LB.
The PAF is asserted LOW on the LOW-to-HIGH transition
of the write clock (WCLK). PAF is reset to HIGH on the LOW-
to-HIGH transition of the read clock (RCLK). Thus PAF is
asynchronous.
A readandawriteshouldnotbeperformedsimultaneously
to the offset registers.
FIRST LOAD (FL)
FL is grounded to indicate operation in the Single Device or
Width Expansion mode. In the Depth Expansion configuration,
FL is grounded to indicate it is the first device loaded and is set
toHIGHforallotherdevicesintheDaisyChain. (SeeOperating
Configurations for further details.)
WRITE EXPANSION INPUT (WXI)
This is a dual purpose pin. WXI is grounded to indicate
operationintheSingleDeviceorWidthExpansionmode. WXI
is connected to Write Expansion Out (WXO) of the previous
device in the Daisy Chain Depth Expansion mode.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty Flag (PAE) will go LOW
when the read pointer is “n+1” locations less than the write
pointer. The offset “n” is defined in the EMPTY offset register.
If there is no Empty offset specified, the Programmable
Almost-Empty Flag (PAE) will be LOW when the device is 31
away from completely empty for IDT72205LB, 63 away from
completely empty for IDT72215LB, and 127 away from com-
pletely empty for IDT72225LB/72235LB/72245LB.
The PAE is asserted LOW on the LOW-to-HIGH transition
of the read clock (RCLK). PAE is reset to HIGH on the LOW-
to-HIGH transition of the write clock (WCLK). Thus PAE is
asynchronous.
READ EXPANSION INPUT (RXI)
This is a dual purpose pin. RXI is grounded to indicate
operation in the Single Device or Width Expansion mode. RXI
is connected to Read Expansion Out (RXO) of the previous
device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG (FF)
When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no
reads are performed after a reset, FF will go LOW after D
writes to the FIFO. D = 256 writes for the IDT72205LB, 512 for
the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the
IDT72235LB and 4,096 for the IDT72245LB.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the Single Device and
Width Expansion mode, when Write Expansion In (WXI) and
Read Expansion In (RXI) are grounded, this output acts as an
indication of a half-full memory.
The FF is updated on the LOW-to-HIGH transition of the
write clock (WCLK).
TABLE I — STATUS FLAGS
Number of Words in FIFO Memory
72205
72215
72225
72235
72245
FF PAF HF PAE EF
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
H
H
H
H
H
(n + 1) to 128
(n + 1) to 256
(n + 1) to 512
(n + 1) to 1,024
(n + 1) to 2,048
H
H
H
H
129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1,024-(m+1)) 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1))
(256-m)(2) to 255
(512-m)(2) to 511 (1,024-m)(2) to 1,023 (2,048-m)(2) to 2,047
(4,096-m)(2) to 4,095
L
256
512 1,024 2,048
4,096
L
L
NOTES:
2766 tbl 09
1. n = Empty Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127)
2. m = Full Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127)
7
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
READ EXPANSION OUT (RXO)
After half of the memory is filled, and at the LOW-to-HIGH
transition of the next write cycle, the Half-Full Flag goes LOW
and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
resettoHIGHbytheLOW-to-HIGHtransitionofthereadclock
(RCLK). The HF is asynchronous.
In the Daisy Chain Depth Expansion configuration, Read
Expansion In (RXI) is connected to Read Expansion Out (RXO)
of the previous device. This output acts as a signal to the next
device in the Daisy Chain by providing a pulse when the
previous device reads from the last location of memory.
DATA OUTPUTS (Q0-Q17)
In the Daisy Chain Depth Expansion mode, WXI is connected
to WXOofthepreviousdevice. Thisoutputactsasasignaltothe
next device in the Daisy Chain by providing a pulse when the
previous device writes to the last location of memory.
Q0-Q17 are data outputs for 18-bit wide data.
tRS
t
RSR
t
RSS
t
RSF
t
t
RSF
RSF
(1)
= 1
Q0 - Q17
2766 drw 06
= 0
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing(2)
8
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
t
CLK
t
CLKH
tCLKL
WCLK
tDH
tDS
D0 - D17
DATA IN VALID
t
ENH
t
ENS
NO OPERATION
t
WFF
t
WFF
(1)
t
SKEW1
RCLK
2766 drw 07
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
t
CLK
t
CLKH
tCLKL
RCLK
t
ENS
tENH
NO OPERATION
REF
t
t
REF
t
A
Q
0
- Q17
VALID DATA
tOLZ
tOHZ
t
OE
(1)
t
SKEW2
WCLK
2766 drw 08
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the
time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
9
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
WCLK
tDS
D0 (first valid write)
D0
- D17
D1
D2
D3
D4
t
ENS
(1)
tFRL
t
SKEW2
RCLK
tREF
tENS
tA
tA
Q0 - Q17
D0
D1
tOLZ
t OE
2766 drw 09
NOTES:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either
2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
NO WRITE
(1)
NO WRITE
(1)
WCLK
SKEW1
SKEW1
t
t
DS
DS
t
t
DATA
D0 - D17
WRITE
DATA WRITE
WFF
WFF
WFF
t
t
t
RCLK
ENS
t
ENS
ENH
t
t
ENH
t
LOW
A
A
t
t
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
2766 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 8. Full Flag Timing
10
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
WCLK
t
DS
tDS
DATA WRITE 1
DATA WRITE 2
D0 - D17
t
ENS
t
ENS
t
ENH
tENH
(1)
(1)
tFRL
tFRL
tSKEW2
t
SKEW2
RCLK
tREF
t
REF
t
REF
LOW
t
A
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
2766 drw 11
NOTE:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2,
or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
t
CLK
t
CLKH
tCLKL
WCLK
t
t
ENS
ENS
tENH
LD
WEN
t
DS
tDH
PAE OFFSET
D0–D15
2766 drw 12
D0–D11
PAE OFFSET
PAF OFFSET
Figure 10. Write Programmable Registers
tCLK
t
CLKH
tCLKL
RCLK
t
ENS
t
ENH
t
ENS
t
A
PAE OFFSET
UNKNOWN
PAE OFFSET
PAF OFFSET
Q0–Q15
2766 drw 13
Figure 11. Read Programmable Registers
11
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
tCLKH
tCLKL
WCLK
tENS
tENH
tPAE
n + 1 words in FIFO
n words in FIFO
tPAE
RCLK
t
ENS
NOTE:
2766 drw 14
1. n = PAE offset. Number of data words written into FIFO already = n.
Figure 12. Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
(1)
tENH
tENS
tPAF
D – m words
D – m + 1 words in FIFO memory (1)
(2)
D – m + 1 words
in FIFO memory
in FIFO memory(1)
tPAF
RCLK
tENS
2766 drw 15
NOTES:
1. m = PAFoffset. D = maximum FIFO Depth. Number of data words written into FIFO memory = 256 - m + 1 for the IDT72205, 512 -m + 1 for the IDT72215,
1,024 - m + 1 for the IDT72225, 2,048 - m + 1 for the IDT72235 and 4,096 - m + 1 for the IDT72245.
2. 256 - m words in IDT72205, 512 - m words in IDT72215, 1,024 - m words in IDT72225, 2,048 - m words in IDT72235 and 4,096 - m words in IDT72245.
Figure 13. Programmable Almost-Full Flag Timing
tCLKH
tCLKL
WCLK
tENH
tENS
tHF
D/2 + 1 words in
FIFO memory(2)
D/2 words in FIFO memory(1)
D/2 words in
FIFO memory(1)
tHF
RCLK
tENS
2766 drw 16
NOTE:
1. D = maximum FIFO Depth = 256 words for the IDT72205, 512 words for the IDT72215, 1,024 words for the IDT72225, 2,048 words for the IDT72235 and
4,096 words for the IDT72245.
Figure 14. Half-Full Flag Timing
12
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
t
CLKH
WCLK
Note 1
t
XO
t
XO
tENS
2766 drw 17
NOTE:
1. Write to Last Physical Location.
Figure 15. Write Expansion Out Timing
t
CLKH
RCLK
Note 1
t
XO
t
XO
t
ENS
2766 drw 18
NOTE:
1. Read from Last Physical Location.
Figure 16. Read Expansion Out Timing
t
XI
t
XIS
WCLK
2766 drw 19
Figure 17. Write Expansion In Timing
t
XI
t
XIS
RCLK
2766 drw 20
Figure 18. Read Expansion In Timing
13
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
OPERATING CONFIGURATIONS
512/1,024/2,048/4,096 words or less. These FIFOs are in a
single Device Configuration when the First Load (FL), Write
ExpansionIn(WXI)andReadExpansionIn(RXI) controlinputs
are grounded (Figure 19).
SINGLE DEVICE CONFIGURATION
AsingleIDT72205LB/72215LB/72225LB/72235LB/72245LB
may be used when the application requirements are for 256/
RESET
)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
WRITE ENABLE
LOAD
)
READ ENABLE
)
)
OUTPUT ENABLE
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
DATA IN (D
0
- D17
)
DATA OUT (Q
0
- Q17
)
FULL FLAG
)
EMPTY FLAG
)
PROGRAMMABLE
HALF-FULL FLAG
)
PROGRAMMABLE
)
)
2766 drw 21
READ EXPANSION IN
WRITE EXPANSION IN
)
FIRST LOAD (
)
)
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
WIDTH EXPANSION CONFIGURATION
user must create composite flags by ANDing the Empty Flags
of every FIFO, and separately ANDing all Full Flags. Figure 20
demonstratesa36-wordwidthbyusingtwoIDT72205B/72215B/
72225B/72235B/72245Bs. Any word width can be attained by
adding additional IDT72205B/72215B/72225B/72235B/
72245Bs. Please see the Application Note AN-83.
Wordwidthmaybeincreasedsimplybyconnectingtogether
the control signals of multiple devices. Status flags can be
detected from any one device. The exceptions are the Empty
Flag and Full Flag. Because of variations in skew between
RCLKandWCLK,itispossibleforflagassertionanddeassertion
to vary by one cycle between FIFOs. To avoid problems the
RESET
)
RESET
)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE
LOAD
READ ENABLE
OUTPUT ENABLE
PROGRAMMABLE
)
)
)
)
)
72205LB
72215LB
72225LB
72235LB
72245LB
PROGRAMMABLE
HALF FULL FLAG
)
72205LB
72215LB
72225LB
72235LB
72245LB
)
EMPTY FLAG
)
18
DATA OUT (Q)
36
FULL FLAG
)
18
FIRST LOAD
WRITE EXPANSION IN
READ EXPANSION IN
)
2766 drw 22
)
)
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
14
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
the next device. See Figure 21.
DEPTH EXPANSION CONFIGURATION
4. The Read Expansion Out (RXO) pin of each device
must be tied to the Read Expansion In (RXI) pin of
the next device. See Figure 21.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in this Depth
Expansion Configuration.
7. EF, FF, PAE, and PAF are created with composite
flags by ORing together every respective flags for
monitoring. The composite PAE and PAF flags are not
precise.
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requir-
ing more than 256/512/1,024/2,048/4,096 words of buffering.
Figure 21 shows Depth Expansion using three IDT72205LB/
72215LB/72225LB/72235LB/72245LBs. Maximum depth is
limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the
First Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device
must be tied to the Write Expansion In (WXI) pin of
WCLK
RCLK
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
Dn
Qn
Vcc
WCLK
RCLK
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
Dn
DATA OUT
DATA IN
Qn
Vcc
WRITE CLOCK
WRITE ENABLE
RESET
WCLK
Dn
READ CLOCK
RCLK
Qn
READ ENABLE
OUTPUT ENABLE
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
LOAD
FIRST LOAD
)
2766 drw 23
Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
15
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
XX
Speed
X
X
Power
Package
Process /
Temperature
Range
BLANK Commercial (0°C to +70°C)
I(1)
Industrial (–40°C to +85°C)
J
PF
TF
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
10
15
25
Commercial Only
Clock Cycle Time (tCLK
)
Commercial & Industrial
Speed in Nanoseconds
Commercial & Industrial
LB
Low Power
72205
72215
72225
72235
72245
256 x 18 Synchronous FIFO
512 x 18 Synchronous FIFO
1,024 x 18 Synchronous FIFO
2,048 x 18 Synchronous FIFO
4,096 x 18 Synchronous FIFO
2766 drw 24
NOTE:
1. Industrial temperature range is available as standard product for the 15ns and the 25 ns speed grade.
16
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