IDT72255LA15TFG_技术文档

CMOS SuperSync FIFO^™

8,192 x 18

16,384 x 18

IDT72255LA

IDT72265LA

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

FEATURES

• Choose among the following memory organizations:

IDT72255LA

IDT72265LA

—

8,192 x 18

16,384 x 18

• Pin-compatible with the IDT72275/72285 SuperSync FIFOs

• 10ns read/write cycle time (8ns access time)

DESCRIPTION

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOs offer numerous improvements over previous SuperSync FIFOs,

includingthefollowing:

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is runningatthe higherfrequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

• Independent Read and Write clocks (permit reading and writing

simultaneously)

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

LD

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF /OR

FLAG

LOGIC

WRITE CONTROL

LOGIC

PAE

HF

FWFT/SI

RAM ARRAY

8,192 x 18

16,384 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

RT

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4670 drw01

Q0 -Q17

OE

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OCTOBER 2005

1



DSC-4670/2

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0

tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency

ofoneclockinputwithrespecttotheother.

Therearetwopossibletimingmodesofoperationwiththesedevices:IDT

Standard mode and First Word Fall Through (FWFT) mode.

InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear

onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread

operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,

willshiftthewordfrominternalmemorytothedataoutputlines.

DESCRIPTION (CONTINUED)

SuperSync FIFOs are particularly appropriate for networking, video,

telecommunications,datacommunicationsandotherapplicationsthatneedto

bufferlargeamountsofdata.

TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable

(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen

WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input

andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge

ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor

three-statecontroloftheoutputs.

PIN CONFIGURATIONS

PIN 1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

48

WEN

SEN

DC

Q17

2

47

Q16

3

46

GND

4

45

VCC

Q15

5

44

GND

D17

D16

D15

D14

D13

D12

D11

D10

D9

Q14

6

43

42

41

40

39

38

37

36

35

34

33

VCC

7

Q13

Q12

Q11

GND

Q10

Q9

8

9

10

11

12

13

14

15

16

Q8

Q7

D8

Q6

D7

GND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

4670 drw02

TQFP (PN64-1, ORDER CODE: PF)

STQFP (PP64-1, ORDER CODE: TF)

TOP VIEW

NOTE:

1. DC = Don’t Care. Must be tied to GND or V^CC, cannot be left open.

2

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused

toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge

ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether

serialorparalleloffsetloadinghasbeenselected.

DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault

settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023

withserialprogramming. Theflagsareupdatedaccordingtothetimingmode

anddefaultoffsetsselected.

The Partial Reset (PRS) also sets the read and write pointers to the first

locationofthememory. However,thetimingmode,partialflagprogramming

method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset

remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand

offsets ineffect. PRS is usefulforresettingadeviceinmid-operation, when

reprogrammingpartialflagswouldbeundesirable.

TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan

once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit

operationbysettingthereadpointertothefirstlocationofthememoryarray.

If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill

automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply

currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

TheIDT72255LA/72265LAarefabricatedusingIDT’shighspeedsubmi-

cronCMOStechnology.

DESCRIPTION (CONTINUED)

InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto

thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot

havetobeassertedforaccessingthefirstword.However,subsequentwords

writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/

SIinputduringMasterResetdeterminesthetimingmodeinuse.

ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan

provide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs

inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding

data inputs of the next). No external logic is required.

TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/

IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-

Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions

areselectedinIDTStandardmode. TheIRandORfunctionsareselectedin

FWFTmode. HF,PAEandPAFarealwaysavailableforuse,irrespectiveof

timingmode.

PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin

memory. (SeeTableIandTable2.) Programmableoffsetsdeterminetheflag

switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two

defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127

or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset

at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith

the LD pinduringMasterReset.

For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,

are used to load the offset registers via the Serial Input (SI). For parallel

PARTIAL RESET (PRS) MASTER RESET (MRS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

DATA OUT (Q0 - Qn)

DATA IN (D0 - Dn)

IDT

72255LA

72265LA

RETRANSMIT (RT)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

FULL FLAG/INPUT READY (FF/IR)

HALF FULL FLAG (HF)

PROGRAMMABLE ALMOST-FULL (PAF)

4670 drw03

Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO

3

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

D0–D17

MRS

Name

I/O

Description

DataInputs

MasterReset

I

Datainputs fora18-bitbus.

MRSinitializes the readandwrite pointers tozeroandsets the outputregisterto allzeroes. During

Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program

mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.

PRS

RT

PartialReset

Retransmit

I

PRS initializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes. During

PartialReset, the existingmode (IDTorFWFT), programmingmethod(serialorparallel), and

programmable flag settings are all retained.

RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to

LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming

method, existing timing mode or programmable flag settings. RT is useful to reread data from the first

physical location of the FIFO.

FWFT/SI

WCLK

FirstWordFall

Through/Serial In

I

DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,

thispinfunctionsasaserialinputforloadingoffsetregisters.

WriteClock

WhenenabledbyWEN,therisingedgeofWCLKwrites dataintotheFIFOandoffsets intothe

programmable registers for parallel programming, and when enabled by SEN, the rising edge of

WCLK writes one bit of data into the programmable register for serial programming.

WEN

RCLK

Write Enable

ReadClock

I

WEN enables WCLK for writing data into the FIFO memory and offset registers.

WhenenabledbyREN, the risingedge ofRCLKreads data fromthe FIFOmemoryandoffsets from

theprogrammableregisters.

REN

OE

SEN

LD

ReadEnable

OutputEnable

SerialEnable

Load

I

RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.

OEcontrolstheoutputimpedanceofQn.

SENenablesserialloadingofprogrammableflagoffsets.

DuringMasterReset, LD selects one oftwopartialflagdefaultoffsets (127or1,023)anddetermines

the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to

andreadingfromtheoffsetregisters.

DC

Don't Care

I

This pinmustbe tiedtoeitherVCC orGNDandmustnottoggle afterMasterReset.

FF/IR

Full Flag/

Input Ready

O

In the IDT Standard mode, the FF functionis selected. FF indicates whetherornotthe FIFO

memoryis full. Inthe FWFTmode, the IR functionis selected. IR indicates whetherornot

there is space available for writing to the FIFO memory.

EF/OR

PAF

Empty Flag/

OutputReady

O

In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO

memoryis empty. InFWFTmode, the OR functionis selected.OR indicates whetherornotthereis

validdataavailableattheoutputs.

Programmable

Almost-FullFlag

PAF goes LOWifthe numberofwords inthe FIFOmemoryis more thantotalwordcapacityofthe

FIFOminus thefulloffsetvaluem,whichis storedintheFullOffsetregister. Therearetwopossible

default values for m: 127 or 1,023.

PAE

Programmable

Almost-EmptyFlag

PAEgoes LOWifthe numberofwords inthe FIFOmemoryis less thanoffsetn, whichis storedin

the EmptyOffsetregister. There are twopossible defaultvalues forn:127or1,023. Othervalues

forncanbe programmedintothe device.

HF

Q0–Q17

VCC

Half-FullFlag

DataOutputs

Power

O

HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.

Dataoutputsforan18-bitbus.

+5 Volt power supply pins.

GND

Ground

Groundpins.

4

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

RECOMMENDEDDCOPERATING

CONDITIONS

Symbol

Rating

Com’l & Ind’l

Unit

VTERM

TerminalVoltage

–0.5to+7.0

V

Symbol

Parameter

Min.

4.0

0

Typ.

5.0

0

Max.

5.5

0

Unit

V

with respect to GND

VCC

Supply Voltage (Com’l/Ind’l)

Input High Voltage (Com’l/Ind’l)

Input Low Voltage (Com’l/Ind’l)

TSTG

IOUT

Storage

Temperature

–55to+125

–50to+50

° C

GND

VIH

V

2.0



0



—

V

DCOutputCurrent

mA

(1)

VIL

0.8

+70

V

NOTE:

TA

OperatingTemperature

Commercial

°C

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

OperatingTemperature

Industrial

-40



+85

°C

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)

IDT72255LA

IDT72265LA

Commercial & Industrial⁽¹⁾

tCLK = 10, 15, 20 ns

Symbol

Parameter

Min.

–1

Max.

Unit

(2)

ILI

InputLeakageCurrent

1

µ A

µA

V

(3)

ILO

OutputLeakageCurrent

–10

2.4

—

10

—

0.4

VOH

VOL

Output Logic “1” Voltage, IOH = –2 mA

Output Logic “0” Voltage, IOL = 8 mA

V

(4,5,6)

ICC1

Active Power Supply Current

StandbyCurrent

—

80

20

mA

(4,7)

ICC2

NOTES:

1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

2. Measurements with 0.4 ≤ V^IN≤ VCC.

3. OE ≥ V^IH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs disabled (I^OUT= 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical I^CC1= 15 + 2.1*fS + 0.02*CL*fS (in mA) with VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data

switching at f^S/2, CL = capacitive load (in pF).

7. All Inputs = V^CC–0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

Max.

Unit

(2)

CIN

Input

VIN = 0V

10

pF

Capacitance

(1,2)

COUT

Output

VOUT = 0V

10

pF

Capacitance

NOTES:

1. With output deselected, (OE ≥ V^IH).

2. Characterized values, not currently tested.

5

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

Commercial

Commercial & Industrial⁽²⁾

IDT72255LA10

IDT72265LA10

IDT72255LA15

IDT72265LA15

Min. Max.

IDT72255LA20

IDT72265LA20

Symbol

fS

Parameter

Clock Cycle Frequency

Min.

Max.

100

8

Min.

Max.

Unit

MHz

ns

—

2

—

2

66.7

10

—

15

—

8

—

2

50

12

—

20

—

10

12

22

—

tA

DataAccessTime

Clock Cycle Time

Clock High Time

tCLK

tCLKH

tCLKL

tDS

10

4.5

3

—

10

—

6

15

6

20

8

Clock Low Time

6

8

DataSetupTime

4

5

tDH

DataHoldTime

0

1

tENS

tENH

tLDS

EnableSetupTime

EnableHoldTime

LoadSetupTime

3

4

5

0

1

3

4

5

tLDH

tRS

LoadHoldTime

0

1

ResetPulseWidth⁽³⁾

ResetSetupTime

ResetRecoveryTime

ResettoFlagandOutputTime

ModeSelectTime

RetransmitSetupTime

10

—

0

15

—

0

20

—

0

tRSS

tRSR

tRSF

tFWFT

tRTS

tOLZ

tOE

3

4

5

(4)

OutputEnabletoOutputinLowZ

OutputEnabletoOutputValid

0

2

3

(4)

tOHZ

tWFF

tREF

tPAF

tPAE

tHF

OutputEnabletoOutputinHighZ

Write Clock to FF or IR

2

6

3

8

3

—

5

8

—

6

10

20

—

10

20

60

25

Read Clock to EF or OR

8

Write Clock to PAF

8

Read Clock to PAE

8

Clock to HF

16

—

tSKEW1

tSKEW2

tSKEW3

tSKEW4

Skew time between RCLK and WCLK for FF/IR

Skew time between RCLK and WCLK for PAE and PAF

Skew time between RCLK and WCLK for EF/OR

12

60

15

60

17

Skew time between RCLK and WCLK for PAE and PAF

forRe-transmitoperation

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

3. Pulse widths less than minimum values are not allowed.

5V

4. Values guaranteed by design, not currently tested.

1.1K

D.U.T.

AC TEST CONDITIONS

30pF*

680Ω

Input Pulse Levels

GND to 3.0V

3ns

4670 drw04

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figure 2. Output Load

* Includes jig and scope capacitances.

See Figure 2

6

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

If the FIFO is full, the first read operation will cause FF to go HIGH.

Subsequent read operations will cause PAF and HF to go HIGH at the

conditions described in Table 1. If further read operations occur, without

write operations, PAE will go LOW when there are n words in the FIFO,

where n is the empty offset value. Continuing read operations will cause the

FIFO to become empty. When the last word has been read from the FIFO,

the EF will go LOW inhibiting further read operations. REN is

ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are

double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in

Figure 7, 8 and 11.

FUNCTIONALDESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH

(FWFT) MODE

The IDT72255LA/72265LA support two different timing modes of

operation: IDT Standard mode or First Word Fall Through (FWFT) mode.

The selection of which mode will operate is determined during Master Re-

set, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode

will be selected. This mode uses the Empty Flag (EF) to indicate whether

or not there are any words present in the FIFO. It also uses the Full Flag

function (FF) to indicate whether or not the FIFO has any free space for

writing. In IDT Standard mode, every word read from the FIFO, including

the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (OR) to indicate whether or not

there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to

indicate whether or not the FIFO has any free space for writing. In the

FWFT mode, the first word written to an empty FIFO goes directly to Qn

after three RCLK rising edges, REN = LOW is not necessary. Subsequent

words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depend-

ing on which timing mode is in effect.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the

manner outlined in Table 2. To write data into to the FIFO, WEN must be

LOW. Data presented to the DATA IN lines will be clocked into the FIFO on

subsequent transitions of WCLK. After the first write is performed, the Output

Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the

FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO,

where n is the empty offset value. The default setting for this value is stated

in the footnote of Table 2. This parameter is also user programmable. See

section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the HF would toggle to LOW once the 4,098th

word for the IDT72255LA and 8,194th word for the IDT72265LA, respec-

tively was written into the FIFO. Continuing to write data into the FIFO will

cause the PAF to go LOW. Again, if no reads are performed, the PAF will

go LOW after (8,193-m) writes for the IDT72255LA and (16,385-m) writes

for the IDT72265LA, where m is the full offset value. The default setting for

this value is stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting

further write operations. If no reads are performed after a reset, IR will go

HIGH after D writes to the FIFO. D = 8,193 writes for the IDT72255LA and

16,385 writes for the IDT72265LA, respectively. Note that the additional

word in FWFT mode is due to the capacity of the memory plus output

register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW.

Subsequent read operations will cause the PAF and HF to go HIGH at the

conditions described in Table 2. If further read operations occur, without

write operations, the PAE will go LOW when there are n + 1 words in the

FIFO, where n is the empty offset value. Continuing read operations will

cause the FIFO to become empty. When the last word has been read from

the FIFO, OR will go HIGH inhibiting further read operations. REN is ig-

nored when the FIFO is empty.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the

manner outlined in Table 1. To write data into to the FIFO, Write Enable

(WEN) must be LOW. Data presented to the DATA IN lines will be clocked

into the FIFO on subsequent transitions of the Write Clock (WCLK). After the

first write is performed, the Empty Flag (EF) will go HIGH. Subsequent

writes will continue to fill up the FIFO. The Programmable Almost-Empty flag

(PAE) will go HIGH after n + 1 words have been loaded into the FIFO,

where n is the empty offset value. The default setting for this value is stated

in the footnote of Table 1. This parameter is also user programmable. See

section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read

operations were taking place, the Half-Full flag (HF) would toggle to LOW

once the 4,097th word for IDT72255LA and 8,193th word for IDT72265LA

respectively was written into the FIFO. Continuing to write data into the

FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.

Again, if no reads are performed, the PAF will go LOW after (8,192-m)

writes for the IDT72255LA and (16,384-m) writes for the IDT72265LA.

The offset “m” is the full offset value. The default setting for this value is

stated in the footnote of Table 1. This parameter is also user programmable.

See section on Programmable Flag Offset Loading.

When configured in FWFT mode, the OR flag output is triple register-

buffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 9, 10

and 12.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further

write operations. If no reads are performed after a reset, FF will go LOW

after D writes to the FIFO. D = 8,192 writes for the IDT72255LA and

16,384 for the IDT72265LA, respectively.

7

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PROGRAMMING FLAG OFFSETS

value of 07FH (a threshold 127 words from the empty boundary), and a

Full and Empty Flag offset values are user programmable. The default PAF offset value of 07FH (a threshold 127 words from the full

IDT72255LA/72265LA has internal registers for these offsets. Default set- boundary). See Figure 3, Offset Register Location and Default Values.

tings are stated in the footnotes of Table 1 and Table 2. Offset values can be

In addition to loading offset values into the FIFO, it also possible to read

programmed into the FIFO in one of two ways; serial or parallel loading the current offset values. It is only possible to read offset values via parallel

method. The selection of the loading method is done using the LD (Load) read.

pin. During Master Reset, the state of the LD input determines whether

Figure 4, Programmable Flag Offset Programming Sequence, summa-

serial or parallel flag offset programming is enabled. A HIGH on LD during rizes the control pins and sequence for both serial and parallel program-

Master Reset selects serial loading of offset values and in addition, sets a ming modes. For a more detailed description, see discussion that follows.

default PAE offset value of 3FFH (a threshold 1,023 words from the empty

The offset registers may be programmed (and reprogrammed) any time

boundary), and a default PAF offset value of 3FFH (a threshold 1,023 after Master Reset, regardless of whether serial or parallel programming

words from the full boundary). A LOW on LD during Master Reset selects has been selected.

parallel loading of offset values, and in addition, sets a default PAE offset

TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE

IDT72255LA

IDT72265LA

FF PAF HF PAE EF

0

H

L

H

L

H

L

H

1 to n ⁽¹⁾

Number of

Words in

FIFO

(n + 1) to 4,096

4,097 to (8,192–(m+1))

(n + 1) to 8,192

8,193 to (16,384–(m+1))

H

(8,192

–

m)⁽²⁾to 8,191

8,192

(16,384

–

m)⁽²⁾to16,383

16,384

L

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

TABLE 2 — STATUS FLAGS FOR FWFT MODE

IDT72255LA

IDT72265LA

FF PAF HF PAE EF

0

L

H

L

H

L

H

L

1 to n+1 ⁽¹⁾

Number of

Words in

FIFO ⁽¹⁾

(n + 2) to 4,097

4,098 to (8,193–(m+1))⁽²⁾

(n + 2) to 8,193

8,194 to (16,385–(m+1)) ⁽²⁾

H

(8,193

–

m) to 8,192

(16,385

–

m)⁽²⁾to16,384

16,385

8,193

L

NOTES:

1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.

2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.

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TEMPERATURE RANGES

72255LA — 8,192 x 18–BIT

72265LA — 16,384 x 18–BIT

17

12

0

17

13

0

EMPTY OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

17

12

13

0

FULL OFFSET REGISTER

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

DEFAULT VALUE

07FH if LD is LOW at Master Reset,

3FFH if LD is HIGH at Master Reset

4670 drw06

Figure 3. Offset Register Location and Default Values

Selection

LD

WEN

SEN

WCLK

REN

RCLK

X

Parallel write to registers:

Empty Offset

0

1

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

0

1

0

X

0

1

Serial shift into registers:

26 bits for the 72255LA

X

28 bits for the 72265LA

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

No Operation

Write Memory

Read Memory

No Operation

X

1

0

X

1

X

1

X

0

1

X

4670 drw07

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 4. Programmable Flag Offset Programming Sequence

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SERIAL PROGRAMMING MODE

alternative to holding WEN LOW and toggling LD, parallel programming

If Serial Programming mode has been selected, as described above, then can also be interrupted by setting LD LOW and toggling WEN.

programming of PAE and PAF values can be achieved by using a combi-

Note that the status of a partial flag (PAE or PAF) output is invalid dur-

nation of the LD, SEN, WCLK and SI input pins. Programming PAE and ing the programming process. From the time parallel programming has

PAF proceeds as follows: when LD and SEN are set LOW, data on the begun, a partial flag output will not be valid until the appropriate offset word

SI input are written, one bit for each WCLK rising edge, starting with the has been written to the register(s) pertaining to that flag. Measuring from

Empty Offset LSB and ending with the Full Offset MSB. A total of 26 bits for the rising WCLK edge that achieves the above criteria; PAF will be valid

the IDT72255LA and 28 bits for the IDT72265LA. See Figure 13, Serial after two more rising WCLK edges plus tPAF, PAE will be valid after the

Loading of Programmable Flag Registers, for the timing diagram for this next two rising RCLK edges plus tPAE plus tSKEW2

mode. The act of reading the offset registers employs a dedicated read offset

Using the serial method, individual registers cannot be programmed se- register pointer. The contents of the offset registers can be read on the Q

.

0-

lectively. PAE and PAF can show a valid status only after the complete Qn pins when LD is set LOW and REN is set LOW. Data are read via Qn

set of bits (for all offset registers) has been entered. The registers can be from the Empty Offset Register on the first LOW-to-HIGH transition of RCLK.

reprogrammed as long as the complete set of new offset bits is entered. Upon the second LOW-to-HIGH transition of RCLK, data are read from the

When LD is LOW and SEN is HIGH, no serial write to the registers can Full Offset Register. The third transition of RCLK reads, once again, from

occur.

the Empty Offset Register. See Figure 15, Parallel Read of Programmable

Write operations to the FIFO are allowed before and during the serial Flag Registers, for the timing diagram for this mode.

programming sequence. In this case, the programming of all offset bits does

It is permissible to interrupt the offset register read sequence with reads

not have to occur at once. A select number of bits can be written to the SI or writes to the FIFO. The interruption is accomplished by deasserting REN,

input and then, by bringing LD and SEN HIGH, data can be written to LD, or both together. When REN and LD are restored to a LOW level,

FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with reading of the offset registers continues where it left off. It should be noted,

LD and SEN restored to a LOW, the next offset bit in sequence is written to and care should be taken from the fact that when a parallel read of the flag

the registers via SI. If an interruption of serial programming is desired, it is offsets is performed, the data word that was present on the output lines Qn

sufficient either to set LD LOW and deactivate SEN or to set SEN LOW will be overwritten.

and deactivate LD. Once LD and SEN are both restored to a LOW level,

serial offset programming continues.

Parallel reading of the offset registers is always permitted regardless of

which timing mode (IDT Standard or FWFT modes) has been selected.

From the time serial programming has begun, neither partial flag will be

valid until the full set of bits required to fill all the offset registers has been RETRANSMIT OPERATION

written. Measuring from the rising WCLK edge that achieves the above The Retransmit operation allows data that has already been read to be

criteria; PAF will be valid after two more rising WCLK edges plus tPAF accessed again. There are two stages: first, a setup procedure that resets

PAE will be valid after the next two rising RCLK edges plus tPAE plus the read pointer to the first location of memory, then the actual retransmit,

,

t

SKEW2

.

which consists of reading out the memory contents, starting at the

beginning of memory.

It is not possible to read the flag offset values in a serial mode.

Retransmit setup is initiated by holding RT LOW during a rising RCLK

edge. REN and WEN must be HIGH before bringing RT LOW. At least

PARALLEL MODE

If Parallel Programming mode has been selected, as described above, one word, but no more than D - 2 words should have been written into the

then programming of PAE and PAF values can be achieved by using a FIFO between Reset (Master or Partial) and the time of Retransmit setup.

combination of the LD, WCLK , WEN and Dn input pins. ProgrammingPAE D = 8,192 for the IDT72255LA and D = 16,384 for the IDT72265LA. In

and PAF proceeds as follows: when LD and WEN are set LOW, data on FWFT mode, D = 8,193 for the IDT72255LA and D = 16,385 for the

the inputs Dn are written into the Empty Offset Register on the first LOW-to- IDT72265LA.

HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK,

If IDT Standard mode is selected, the FIFO will mark the beginning of

data are written into the Full Offset Register. The third transition of WCLK the Retransmit setup by setting EF LOW. The change in level will only be

writes, once again, to the Empty Offset Register. See Figure 14, Parallel noticeable if EF was HIGH before setup. During this period, the internal

Loading of Programmable Flag Registers, for the timing diagram for this read pointer is initialized to the first location of the RAM array.

mode.

When EF goes HIGH, Retransmit setup is complete and read opera-

The act of writing offsets in parallel employs a dedicated write offset tions may begin starting with the first location in memory. Since IDT Stan-

register pointer. The act of reading offsets employs a dedicated read offset dard mode is selected, every word read including the first word following

register pointer. The two pointers operate independently; however, a read Retransmit setup requires a LOW on REN to enable the rising edge of

and a write should not be performed simultaneously to the offset registers. RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the

A Master Reset initializes both pointers to the Empty Offset (LSB) register. relevant timing diagram.

A Partial Reset has no effect on the position of these pointers.

If FWFT mode is selected, the FIFO will mark the beginning of the

Write operations to the FIFO are allowed before and during the parallel Retransmit setup by setting OR HIGH. During this period, the internal read

programming sequence. In this case, the programming of all offset pointer is set to the first location of the RAM array.

registers does not have to occur at one time. One, two or more offset reg-

When OR goes LOW, Retransmit setup is complete; at the same time,

isters can be written and then by bringing LD HIGH, write operations can the contents of the first location appear on the outputs. Since FWFT mode

be redirected to the FIFO memory. When LD is set LOW again, and WEN is selected, the first word appears on the outputs, no LOW on REN is

is LOW, the next offset register in sequence is written to. As an necessary. Reading all subsequent words requires a LOW on REN to

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TEMPERATURE RANGES

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT

Mode), for the relevant timing diagram.

For either IDT Standard mode or FWFT mode, updating of the PAE,

HF and PAF flags begin with the rising edge of RCLK that RT is setup.

PAE is synchronized to RCLK, thus on the second rising edge of RCLK

after RT is setup, the PAE flag will be updated. HF is asynchronous, thus

the rising edge of RCLK that RT is setup will update HF. PAF is synchro-

nized to WCLK, thus the second rising edge of WCLK that occurs tSKEW

after the rising edge of RCLK that RT is setup will update PAF. RT is

synchronized to RCLK.

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the read pointer to the first location of memory, then the actual retransmit,

which consists of reading out the memory contents, starting at beginning of

the memory.

SIGNALDESCRIPTION

INPUTS:

Retransmit setup is initiated by holding RT LOW during a rising RCLK

edge. REN and WEN must be HIGH before bringing RT LOW.

If IDT Standard mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting EF LOW. The change in level will only be

noticeable if EF was HIGH before setup. During this period, the internal

read pointer is initialized to the first location of the RAM array.

When EF goes HIGH, Retransmit setup is complete and read operations

may begin starting with the first location in memory. Since IDT Standard

mode is selected, every word read including the first word following Re-

transmit setup requires a LOW on REN to enable the rising edge of RCLK.

See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant

timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Re-

transmit setup by setting OR HIGH. During this period, the internal read

pointer is set to the first location of the RAM array.

When OR goes LOW, Retransmit setup is complete; at the same time, the

contents of the first location appear on the outputs. Since FWFT mode is

selected, the first word appears on the outputs, no LOW on REN is neces-

sary. Reading all subsequent words requires a LOW on REN to enable the

rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for

the relevant timing diagram.

DATA IN (D0 - D17)

Data inputs for 18-bit wide data.

CONTROLS:

MASTER RESET (MRS)

A Master Reset is accomplished whenever the MRS input is taken to a

LOW state. This operation sets the internal read and write pointers to the first

location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF

will go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard mode,

along with EF and FF are selected. EF will go LOW and FF will go HIGH. If

FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with

IR and OR, are selected. OR will go HIGH and IR will go LOW.

If LD is LOW during Master Reset, then PAE is assigned a threshold 127

words from the empty boundary and PAF is assigned a threshold 127

words from the full boundary; 127 words corresponds to an offset value of

07FH. Following Master Reset, parallel loading of the offsets is permitted,

but not serial loading.

If LD is HIGH during Master Reset, then PAE is assigned a threshold

1,023 words from the empty boundary and PAF is assigned a threshold

1,023 words from the full boundary; 1,023 words corresponds to an offset

value of 3FFH. Following Master Reset, serial loading of the offsets is

permitted, but not parallel loading.

Parallel reading of the registers is always permitted. (See section

describing the LD pin for further details.)

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state of the FWFT/

SI input determines whether the device will operate in IDT Standard mode

or First Word Fall Through (FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode

will be selected. This mode uses the Empty Flag (EF) to indicate whether

or not there are any words present in the FIFO memory. It also uses the

Full Flag function (FF) to indicate whether or not the FIFO memory has any

free space for writing. In IDT Standard mode, every word read from the

FIFO, including the first, must be requested using the Read Enable (REN)

and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (OR) to indicate whether or not

there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to

indicate whether or not the FIFO memory has any free space for writing. In

the FWFT mode, the first word written to an empty FIFO goes directly to Qn

after three RCLK rising edges, REN = LOW is not necessary. Subsequent

words must be accessed using the Read Enable (REN) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for loading PAE and

PAF offsets into the programmable registers. The serial input function can

only be used when the serial loading method has been selected during

Master Reset. Serial programming using the FWFT/SI pin functions the

same way in both IDT Standard and FWFT modes.

During a Master Reset, the output register is initialized to all zeroes. A

Master Reset is required after power up, before a write operation can take

place. MRS is asynchronous.

See Figure 5, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (PRS)

A Partial Reset is accomplished whenever the PRS input is taken to a

LOW state. As in the case of the Master Reset, the internal read and write

pointers are set to the first location of the RAM array, PAE goes LOW, PAF

goes HIGH, and HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode

or First Word Fall Through, that mode will remain selected. If the IDT

Standard mode is active, then FF will go HIGH and EF will go LOW. If the

First Word Fall Through mode is active, then OR will go HIGH, and IR will

go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The programming method (parallel or serial) currently active

at the time of Partial Reset is also retained. The output register is initialized

to all zeroes. PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation, when reprogramming partial flag offset settings may not be

convenient.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the WCLK input. Data setup

and hold times must be met with respect to the LOW-to-HIGH transition of the

WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the

FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only

capable of updating HF flag to LOW). The Write and Read Clocks can

either be independent or coincident.

See Figure 6, Partial Reset Timing, for the relevant timing diagram.

RETRANSMIT (RT)

The Retransmit operation allows data that has already been read to be

accessed again. There are two stages: first, a setup procedure that resets

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WRITE ENABLE (WEN)

When the WEN input is LOW, data may be loaded into the FIFO RAM

OUTPUT ENABLE (OE)

When Output Enable is enabled (LOW), the parallel output buffers

array on the rising edge of every WCLK cycle if the device is not full. Data receive data from the output register. When OE is HIGH, the output data

is stored in the RAM array sequentially and independently of any ongoing bus (Qn) goes into a high impedance state.

read operation.

When WEN is HIGH, no new data is written in the RAM array on each LOAD (LD)

WCLK cycle.

This is a dual purpose pin. During Master Reset, the state of the LD

To prevent data overflow in the IDT Standard mode, FF will go LOW, input determines one of two default offset values (127 or 1,023) for the PAE

inhibiting further write operations. Upon the completion of a valid read cycle, and PAF flags, along with the method by which these offset registers can be

FF will go HIGH allowing a write to occur. The FF is updated by two WCLK programmed, parallel or serial. After Master Reset, LD enables write op-

cycles + tSKEW after the RCLK cycle.

erations to and read operations from the offset registers. Only the offset

To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting loading method currently selected can be used to write to the registers.

further write operations. Upon the completion of a valid read cycle, IR will Offset registers can be read only in parallel. A LOW on LD during Master

go LOW allowing a write to occur. The IR flag is updated by two WCLK Reset selects a default PAE offset value of 07FH (a threshold 127 words

cycles + tSKEW after the valid RCLK cycle.

WEN is ignored when the FIFO is full in either FWFT or IDT Standard 127 words from the full boundary), and parallel loading of other offset

from the empty boundary), a default PAF offset value of 07FH (a threshold

mode.

READ CLOCK (RCLK)

values. A HIGH on LD during Master Reset selects a default PAE offset

value of 3FFH (a threshold 1,023 words from the empty boundary), a

default PAF offset value of 3FFH (a threshold 1,023 words from the full

A read cycle is initiated on the rising edge of the RCLK input. Data can boundary), and serial loading of other offset values.

be read on the outputs, on the rising edge of the RCLK input. It is permis-

After Master Reset, the LD pin is used to activate the programming

sible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and process of the flag offset values PAE and PAF. Pulling LD LOW will begin a

HF flags will not be updated. (Note that RCLK is only capable of updating serial loading or parallel load or read of these offset values. See Figure 4,

the HF flag to HIGH). The Write and Read Clocks can be independent or Programmable Flag Offset Programming Sequence.

coincident.

OUTPUTS:

READ ENABLE (REN)

FULL FLAG (FF/IR)

When Read Enable is LOW, data is loaded from the RAM array into the

output register on the rising edge of every RCLK cycle if the device is not

empty.

This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)

function is selected. When the FIFO is full, FF will go LOW, inhibiting further

write operations. When FF is HIGH, the FIFO is not full. If no reads are

performed after a reset (either MRS or PRS), FF will go LOW after D writes

When the REN input is HIGH, the output register holds the previous data

and no new data is loaded into the output register. The data outputs Q0-Qn

to the FIFO (D = 8,192 for the IDT72255LA and 16,384 for the

maintain the previous data value.

IDT72265LA). See Figure 7, Write Cycle and Full Flag Timing (IDT Stan-

dard Mode), for the relevant timing information.

In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW

when memory space is available for writing in data. When there is no

In the IDT Standard mode, every word accessed at Qn, including the first

word written to an empty FIFO, must be requested using REN. When the

last word has been read from the FIFO, the Empty Flag (EF) will go LOW,

inhibiting further read operations. REN is ignored when the FIFO is empty.

longer any free space left, IR goes HIGH, inhibiting further write operations.

Once a write is performed, EF will go HIGH allowing a read to occur. The

If no reads are performed after a reset (either MRS or PRS), IR will go

EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.

HIGH after D writes to the FIFO (D = 8,193 for the IDT72255LA and 16,385

for the IDT72265LA) See Figure 9, Write Timing (FWFT Mode), for the

In the FWFT mode, the first word written to an empty FIFO automatically

goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK +

relevant timing information.

tSKEW after the first write. REN does not need to be asserted LOW. In order

The IR status not only measures the contents of the FIFO memory, but

also counts the presence of a word in the output register. Thus, in FWFT

mode, the total number of writes necessary to deassert IR is one greater

than needed to assert FF in IDT Standard mode.

to access all other words, a read must be executed using REN. The RCLK

LOW to HIGH transition after the last word has been read from the FIFO,

Output Ready (OR) will go HIGH with a true read (RCLK with REN =

LOW), inhibiting further read operations. REN is ignored when the FIFO is

FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR

empty.

are double register-buffered outputs.

SERIAL ENABLE (SEN)

EMPTY FLAG (EF/OR)

The SEN input is an enable used only for serial programming of the

This is a dual purpose pin. In the IDT Standard mode, the Empty Flag

offset registers. The serial programming method must be selected during

(EF) function is selected. When the FIFO is empty, EF will go LOW,

Master Reset. SEN is always used in conjunction with LD. When these lines

are both LOW, data at the SI input can be loaded into the program register

one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)

inhibiting further read operations. When EF is HIGH, the FIFO is not empty.

See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing

(IDT Standard Mode), for the relevant timing information.

In FWFT mode, the Output Ready (OR) function is selected. OR goes

LOW at the same time that the first word written to an empty FIFO appears

When SEN is HIGH, the programmable registers retains the previous

settings and no offsets are loaded. SEN functions the same way in both IDT

Standard and FWFT modes.

valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition

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that shifts the last word from the FIFO memory to the outputs. OR goes LOW when there are n words or less in the FIFO. The offset “n” is the

HIGH only with a true read (RCLK with REN = LOW). The previous data empty offset value. The default setting for this value is stated in the footnote

stays at the outputs, indicating the last word was read. Further data reads of Table 1.

are inhibited until OR goes LOW again. See Figure 10, Read Timing

(FWFT Mode), for the relevant timing information.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode, OR is a triple register-buffered output.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in the footnote of

Table 2.

See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-

dard and FWFT Mode), for the relevant timing information.

PAE is synchronous and updated on the rising edge of RCLK.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO HALF-FULL FLAG (HF)

reaches the almost-full condition. In IDT Standard mode, if no reads are

This output indicates a half-full FIFO. The rising WCLK edge that fills the

performed after reset (MRS), PAF will go LOW after (D - m) words are FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-

written to the FIFO. The PAF will go LOW after (8,192-m) writes for the ence between the write and read pointers becomes less than or equal to

IDT72255LA and (16,384-m) writes for the IDT72265LA. The offset “m” is half of the total depth of the device; the rising RCLK edge that accomplishes

the full offset value. The default setting for this value is stated in the footnote this condition sets HF HIGH.

of Table 1.

In IDT Standard mode, if no reads are performed after reset (MRS or

In FWFT mode, the PAF will go LOW after (8,193-m) writes for the PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 8,192

IDT72255LA and (16,385-m) writes for the IDT72265LA, where m is the for the IDT72255LA and 16,384 for the IDT72265LA.

full offset value. The default setting for this value is stated in the footnote of

Table 2.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF

will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 8,193 for the

See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard IDT72255LA and 16,385 for the IDT72265LA.

and FWFT Mode), for the relevant timing information.

See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),

PAF is synchronous and updated on the rising edge of WCLK.

for the relevant timing information. Because HF is updated by both RCLK

and WCLK, it is considered asynchronous.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO DATA OUTPUTS (Q0-Q17)

reaches the almost-empty condition. In IDT Standard mode, PAE will go (Q0 - Q17) are data outputs for 18-bit wide data.

14

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tRS

MRS

REN

WEN

tRSS

tRSR

tRSS

tRSR

tFWFT

FWFT/SI

LD

tRSS

tRSR

tRSS

RT

tRSS

SEN

t

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

EF/OR

FF/IR

t

RSF

tRSF

PAE

tRSF

PAF, HF

tRSF

OE = HIGH

OE = LOW

Q0 - Qn

4670 drw08

Figure 5. Master Reset Timing

15

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tRS

PRS

REN

tRSS

tRSR

tRSS

tRSR

WEN

RT

t

RSS

t

SEN

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

t

RSF

EF/OR

tRSF

FF/IR

PAE

tRSF

PAF, HF

tRSF

OE = HIGH

OE = LOW

Q0 - Qn

4670 drw09

Figure 6. Partial Reset Timing

16

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCLK

tDH

tCLKH

NO WRITE

tCLKL

2

1

WCLK

1

2

(1)

tSKEW1⁽¹⁾

tSKEW1

tDS

tDH

DX

DX+1

D0 - Dn

tWFF

FF

WEN

RCLK

tENS

tENH

tENS

tENH

REN

tA

DATA IN OUTPUT REGISTER

tA

Q0 - Qn

DATA READ

NEXT DATA READ

4670 drw10

NOTES:

1. t^SKEW1is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the

rising edge of the RCLK and the rising edge of the WCLK is less than t^SKEW1, then the FF deassertion may be delayed one extra WCLK cycle.

2. LD = HIGH, OE = LOW, EF = HIGH

Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)

tCLK

tCLKH

tCLKL

1

2

RCLK

tENH

tENS

tENH

tENS

NO OPERATION

tREF

tA

D0

Q0

- Qn

LAST WORD

D1

LAST WORD

tOLZ

tOHZ

tOE

(1)

SKEW3

t

WCLK

tENH

tENS

tDS

tDH

tDHS

tDS

D0

- Dn

D0

D1

4670 drw 11

NOTES:

1. t^SKEW3is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the

rising edge of WCLK and the rising edge of RCLK is less than t^SKEW3, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First word latency: 60ns + t^REF+ 1*TRCLK.

Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)

17

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

18

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

19

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

1

2

RCLK

tENS

tENH

tENS

tENH

tRTS

REN

t

A

tA

(3)

Q0 - Qn

Wx

Wx+1

W1

W2

tSKEW4

1

2

WCLK

WEN

RT

tRTS

tENS

tENH

(5)

tREF

EF

PAE

HF

tPAE

tHF

tPAF

PAF

4670 drw 14

NOTES:

1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.

2. OE = LOW.

3. W¹= first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.

4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.

D = 8,192 for IDT72255LA and 16,384 for IDT72265LA.

5. EF goes HIGH at 60 ns + 1 RCLK cycle + t^REF.

Figure 11. Retransmit Timing (IDT Standard Mode)

20

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

3

1

2

4

RCLK

tENH

tENS

tENH

tRTS

REN

- Q

t

A

tA

(4)

Q0

n

Wx

Wx+1

W2

W1

W3

tSKEW4

1

2

WCLK

tRTS

WEN

tENS

tENH

RT

OR

(5)

tREF

tPAE

PAE

tHF

HF

tPAF

PAF

4670 drw15

NOTES:

1. Retransmit setup is complete after OR returns LOW.

2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup

procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

3. OE = LOW

4. W¹, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5. OR goes LOW at 60 ns + 2 RCLK cycles + t^REF.

Figure 12. Retransmit Timing (FWFT Mode)

WCLK

tENH

t

ENS

tENH

tLDH

tLDS

tDS

tDH

(1)

BIT 0

BIT X

SI

4670 drw 16

EMPTY OFFSET

FULL OFFSET

NOTE:

1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.

Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

21

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

t

CLK

t

CLKH

t

CLKL

WCLK

t

LDH

t

LDS

t

LDH

tENH

t

ENH

t

ENS

t

DS

tDH

t

DH

PAE

OFFSET

PAF

OFFSET

D0

- D15

4670 drw 17

Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

t

CLK

t

CLKH

tCLKL

RCLK

t

LDS

t

LDH

t

LDH

t

ENS

tENH

t

ENH

t

A

t

A

DATA IN OUTPUT

REGISTER

PAE

OFFSET

PAF

OFFSET

Q0

- Q15

4670 drw 18

NOTE:

1. OE = LOW

Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)

t

CLKH

t

CLKL

WCLK

1

2

1

t

ENS

tENH

tPAF

D - (m+1) words in FIFO⁽²⁾

D - m words in FIFO⁽²⁾

D-(m+1) words

2)

in FIFO⁽

(3)

SKEW2

t

RCLK

t

ENH

t

ENS

4670 drw 19

NOTES:

1. m = PAF offset.

2. D = maximum FIFO depth.

In IDT Standard mode: D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.

In FWFT mode: D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

3. t^SKEW2is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the

rising edge of RCLK and the rising edge of WCLK is less than t^SKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.

4. PAF is asserted and updated on the rising edge of WCLK only.

Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

22

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

t

CLKH

t

CLKL

WCLK

t

ENH

tENS

n words in FIFO ⁽²⁾

n+1 words in FIFO ⁽³⁾

,

n words in FIFO ⁽²⁾

n+1 words in FIFO ⁽³⁾

,

n+1 words in FIFO ⁽²⁾

n+2 words in FIFO ⁽³⁾

,

(4)

tPAE

t

SKEW2

1

2

1

2

RCLK

tENS

tENH

4670 drw 20

NOTES:

1. n = PAE offset.

2. For IDT Standard mode

3. For FWFT mode.

4. t^SKEW2is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between

the rising edge of WCLK and the rising edge of RCLK is less than t^SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of WCLK only.

Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

tCLKH

tCLKL

WCLK

tENH

tENS

tHF

D/2 + 1 words in FIFO⁽¹⁾

+ 2

words in FIFO⁽²⁾

,

D/2 words in FIFO⁽¹⁾

+ 1

words in FIFO⁽²⁾

,

D/2 words in FIFO⁽¹⁾

+ 1

words in FIFO⁽²⁾

,

[

]

[

]

[

]

tHF

RCLK

tENS

4670 drw 21

NOTES:

1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.

2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)

23

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT Standard mode, such problems can be avoided by creating compos-

ite flags, that is, ANDing EF of every FIFO, and separately ANDing FF of

every FIFO. In FWFT mode, composite flags can be created by ORing

OR of every FIFO, and separately ORing IR of every FIFO.

Figure 23 demonstrates a width expansion using two IDT72255LA/

72265LA devices. D0 - D17 from each device form a 36-bit wide input

bus and Q0-Q17 from each device form a 36-bit wide output bus. Any

word width can be attained by adding additional IDT72255LA/72265LA

devices.

OPTIONAL CONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the

control signals of multiple devices. Status flags can be detected from

any one device. The exceptions are the EF and FF functions in IDT

Standard mode and the IR and OR functions in FWFT mode. Because

of variations in skew between RCLK and WCLK, it is possible for EF/FF

deassertion and IR/OR assertion to vary by one cycle between FIFOs. In

PARTIAL RESET (

MASTER RESET (

)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (

)

Dm+1 - Dn

n

m + n

m

D

0 - Dm

DATA IN

READ CLOCK (RCLK)

WRITE CLOCK (WCLK)

READ ENABLE (

)

WRITE ENABLE (

LOAD (

FULL FLAG/INPUT READY (

)

OUTPUT ENABLE (

PROGRAMMABLE (

)

IDT

72255LA

72265LA

IDT

72255LA

72265LA

)

/

)

#1

EMPTY FLAG/OUTPUT READY (

/

) #1

) #2

(1)

GATE

/

) #2

GATE

PROGRAMMABLE (

HALF-FULL FLAG (

)

m + n

n

Qm+1 - Qn

FIFO

#1

FIFO

#2

DATA OUT

m

4670 drw 22

Q0 - Qm

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion

24

OCTOBER17,2005

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)

that the tSKEW3 specification is not met between WCLK and transfer clock,

The IDT72255LA can easily be adapted to applications requiring depths or RCLK and transfer clock, for the OR flag.

greater than 8,192 and 16,384 for the IDT72265LA with an 18-bit bus

The "ripple down" delay is only noticeable for the first word written to an

width. In FWFT mode, the FIFOs can be connected in series (the data empty depth expansion configuration. There will be no delay evident for

outputs of one FIFO connected to the data inputs of the next) with no subsequent words written to the configuration.

external logic necessary. The resulting configuration provides a total

The first free location created by reading from a full depth expansion

depth equivalent to the sum of the depths associated with each single configuration will "bubble up" from the last FIFO to the previous one until it

FIFO. Figure 24 shows a depth expansion using two IDT72255LA/72265LA finally moves into the first FIFO of the chain. Each time a free location is

devices.

created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling

Care should be taken to select FWFT mode during Master Reset for all the preceding FIFO to write a word to fill it.

FIFOs in the depth expansion configuration. The first word written to an

For a full expansion configuration, the amount of time it takes for IR of the

empty configuration will pass from one FIFO to the next ("ripple down") first FIFO in the chain to go LOW after a word has been read from the last

until it finally appears at the outputs of the last FIFO in the chain–no read FIFO is the sum of the delays for each individual FIFO:

operation is necessary but the RCLK of each FIFO must be free-running.

Each time the data word appears at the outputs of one FIFO, that device's

OR line goes LOW, enabling a write to the next FIFO in line.

For an empty expansion configuration, the amount of time it takes for OR

of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last

FIFO's outputs) after a word has been written to the first FIFO is the sum of

the delays for each individual FIFO:

(N – 1)*(3*transfer clock) + 2 TWCLK

where N is the number of FIFOs in the expansion and TWCLK is the

WCLK period. Note that extra cycles should be added for the possibility

that the tSKEW1 specification is not met between RCLK and transfer clock,

or WCLK and transfer clock, for the IR flag.

The Transfer Clock line should be tied to either WCLK or RCLK, which-

ever is faster. Both these actions result in data moving, as quickly as

possible, to the end of the chain and free locations to the beginning of the

chain.

(N – 1)*(4*transfer clock) + 3*TRCLK

where N is the number of FIFOs in the expansion and TRCLK is the

RCLK period. Note that extra cycles should be added for the possibility

FWFT/SI

•

TRANSFER CLOCK

FWFT/SI

READ CLOCK

READ ENABLE

WRITE CLOCK

WCLK

RCLK

WCLK

RCLK

•

WRITE ENABLE

INPUT READY

IDT

72255LA

72265LA

IDT

72255LA

72265LA

OUTPUT READY

OUTPUT ENABLE

GND

n

DATA OUT

n

DATA IN

Dn

Qn

Dn

4670 drw 23

Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion

25

OCTOBER17,2005

ORDERING INFORMATION

IDT

XXXXX

X

XX

X

Process /

Temperature

Range

Device Type

Power

Speed

Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Green

G

Thin Plastic Quad Flatpack (TQFP, PN64-1)

Slim Thin Quad Flatpack (STQFP, PP64-1)

PF

TF

Commercial Only

10

15

20

Clock Cycle Time (tCLK

)

Com'l & Ind'l

Speed in Nanoseconds

Com‘l & Ind’l

Low Power

LA

8,192 x 18 — SuperSync FIFO

16,384 x 18 — SuperSync FIFO

72255

72265

4670 drw24

NOTES:

1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device.

2. Green parts available. For specific speeds and packages contact your sales office.

DATASHEETDOCUMENTHISTORY

04/25/2001

10/17/2005

pgs. 1, 5, 6 and 26.

pgs. 1, 6, 20, 21 and 26. PCN F0509-01.

#

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

26

5 VOLT CMOS SuperSync FIFO^™

8,192 x 18

IDT72255LA

IDT72265LA

16,384 x 18

ADDENDUM

DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L

IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-

for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences.

Item

NEW PART

OLD PART

Comments

IDT72255LA

IDT72265LA

IDT72255L

IDT72265L

Pin #3

DC (Don’t Care) - There is

no restriction on WCLK and

RCLK. See note 1.

FS (Frequency Select)

In the LA part this pin must be tied

to either VCC or GND and must

not toggle after reset.

(4)

(3)

(4)

First Word Latency

(IDT Standard Mode)

60ns⁽²⁾+ tREF + 1 TRCLK

tFWL1 = 10*Tf + 2TRCLK (ns) First word latency in the LA part is

a fixed value, independent of the

frequency of RCLK or WCLK.

(4)

(3)

(4)

First Word Latency

(FWFT Mode)

60ns⁽²⁾+ tREF + 2 TRCLK

tFWL2 = 10*Tf + 3TRCLK (ns) First word latency in the LA part is

a fixed value, independent of the

frequency of RCLK or WCLK.

(4)

(3)

(4)

Retransmit Latency

(IDT Standard Mode)

60ns⁽²⁾+ tREF + 1 TRCLK

tRTF1 = 14*Tf + 3TRCLK (ns) Retransmit latency in the LA part is

a fixed value, independent of the

frequency of RCLK or WCLK.

(4)

(3)

(4)

Retransmit Latency

(FWFT Mode)

60ns⁽²⁾+ tREF + 2 TRCLK

tRTF2 = 14*Tf + 4TRCLK (ns) Retransmit latency in the LA part is

a fixed value, independent of the

frequency of RCLK or WCLK.

ICC1

80mA

180mA

15mA

Active supply current

Standby current

ICC2

20mA

Typical ICC1⁽⁵⁾

15 + 2.1*fS + 0.02*CL*fS(mA)

Not Given

Typical ICC1 Current calculation

NOTES:

1. WCLK and RCLK can vary independently and can be stopped. There is no restriction on operating WCLK and RCLK.

2. This is tSKEW3.

3. Tf is the period of the ‘selected clock’.

4. TRCLK is the cycle period of the read clock.

5. Typical ICC1 is based on VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz using TTL levels), data switching at fS/2, CL = Capacitive Load (in pF).

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,IncandtheSuperSyncFIFOisatrademark ofIntegratedDeviceTechnology,Inc.

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

27


型号：	IDT72255LA15TFG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CMOS SuperSync FIFO CMOS SuperSync FIFO 先进先出芯片
文件：	总27页 (文件大小：329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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