IDT72275L15PFI8 [IDT]
FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64;
| 型号： | IDT72275L15PFI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总25页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SuperSync FIFO™
32,768 x 18
65,536 x 18
IDT72275
IDT72285
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
IDT72275 — 32,768 x 18
IDT72285 — 65,536 x 18
• Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
DESCRIPTION:
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
TheIDT72275/72285areexceptionallydeep,highspeed,CMOSFirst-In-
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe
following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
FUNCTIONAL BLOCK DIAGRAM
D0 -D17
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
32,768 x 18
65,536 x 18
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
4674 drw 01
Q0 -Q17
OE
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AUGUST 2013
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4674/6
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
arisingRCLKedge,willshiftthewordfrominternalmemorytothedataoutput
lines.
DESCRIPTION (CONTINUED)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-
munications,datacommunicationsandotherapplicationsthatneedtobuffer
largeamountsofdata.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequentwordswrittentotheFIFOdorequireaLOWonRENforaccess.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFand
FF functions are selected in IDT Standard mode. The IR and OR functions
areselectedinFWFTmode. HF,PAEandPAFarealwaysavailableforuse,
irrespectiveoftimingmode.
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLKwhenWENisasserted.TheoutputportiscontrolledbyaReadClock
(RCLK) input and Read Enable (REN) input. Data is read from the FIFO on
every rising edge of RCLK when REN is asserted. An Output Enable (OE)
input is provided for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from
0 to fMAX with complete independence. There are no restrictions on the
frequency of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsistsofactivatingRENandenabling
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
WEN
SEN
DC
Q17
2
47
Q16
3
46
GND
4
45
VCC
Q15
5
44
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
Q14
6
43
42
41
40
39
38
37
36
35
34
33
VCC
7
Q13
Q12
Q11
GND
Q10
Q9
8
9
10
11
12
13
14
15
16
Q8
Q7
D8
Q6
D7
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4674 drw 02
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
2
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
of1,023withserialprogramming. Theflagsareupdatedaccordingtothetiming
modeanddefaultoffsetsselected.
DESCRIPTION (CONTINUED)
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith
the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn. REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode. The LD pin selects either a partial flag
defaultsettingof127withparallelprogrammingorapartialflagdefaultsetting
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timingmodeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-
operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72275/72285 are fabricated using high speed submicron CMOS
technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72275
72285
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4674 drw 03
Figure 1. Block Diagram of Single 32,768 x 18 and 65,536 x 18 Synchronous FIFO
3
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
D0–D17
MRS
Name
I/O
Description
DataInputs
I
I
Datainputsfora18-bitbus.
MasterReset
PartialReset
Retransmit
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. During
MasterReset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,oneoftwoprogrammable
flagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
RT
I
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmableflagsettingsareallretained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets theEFflagtoLOW
(OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method,existingtimingmodeorprogrammableflagsettings.RTisusefultorereaddatafromthefirst
physicallocationoftheFIFO.
FWFT/SI
WCLK
FirstWordFall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
thispinfunctionsasaserialinputforloadingoffsetregisters
WriteClock
WhenenabledbyWEN, therisingedgeofWCLKwritesdataintotheFIFOandoffsetsintothe
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheFIFOmemoryandoffsetsfromthe
programmableregisters.
REN
OE
SEN
LD
Read Enable
OutputEnable
SerialEnable
Load
I
I
I
I
RENenablesRCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
DuringMasterReset,LDselectsoneoftwopartialflagdefaultoffsets(127or1,023anddeterminesthe
flagoffsetprogrammingmethod,serialorparallel.AfterMasterReset,thispinenableswritingtoandreading
fromtheoffsetregisters
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory
isfull.IntheFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailable
forwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
IntheIDTStandardmode, theEFfunctionisselected. EFindicateswhetherornottheFIFO memory
is empty. In FWFT mode, the OR function isselected. OR indicateswhether or notthereisvaliddata
availableattheoutputs.
Programmable
AlmostFullFlag
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFOminusthefulloffsetvaluem,whichisstoredintheFullOffsetregister.Therearetwopossible
default values for m: 127 or 1,023.
PAE
Programmable
AlmostEmptyFlag
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
EmptyOffsetregister.Therearetwopossibledefaultvaluesforn:127or1,023.Othervaluesforncan
beprogrammedintothedevice.
HF
Q0–Q17
VCC
Half-FullFlag
DataOutputs
Power
O
O
HFindicateswhethertheFIFOmemoryismoreorlessthanhalf-full.
Dataoutputsforan18-bitbus.
+5 Volt power supply pins.
GND
Ground
Groundpins.
4
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
TerminalVoltage
–0.5 to +7
V
Symbol
Parameter
Min.
Typ.
Max.
Unit
with respect to GND
VCC
Supply Voltage(Com’l & Ind’l)
Supply Voltage(Com’l & Ind’l)
4.5
5.0
5.5
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND
VIH
0
0
0
V
InputHighVoltage
(Com’l & Ind’l)
DCOutputCurrent
mA
2.0
—
—
V
NOTE:
VIL(1)
TA
InputLowVoltage
(Com’l & Ind’l)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
—
0
—
—
0.8
V
OperatingTemperature
Commercial
+70
°C
TA
OperatingTemperature
Industrial
-40
⎯
+85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%, TA = -40°C to +85°C)
IDT72275
IDT72285
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
–1
Max.
Unit
ILI(2)
ILO(3)
InputLeakageCurrent
OutputLeakageCurrent
1
μA
μA
V
–10
2.4
—
10
—
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
0.4
90
20
V
ICC1(4,5,6)
ICC2(4,7)
—
mA
mA
—
NOTES:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
2 .Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 20 + 1.8*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at
fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN(2)
Input
VIN = 0V
10
pF
Capacitance
COUT(1,2)
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%,TA = -40°C to +85°C)
Commercial
Commercial & Industrial(2)
IDT72275L10
IDT72285L10
IDT72275L15
IDT72285L15
Min.
IDT72275L20
IDT72285L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
Min.
Max.
50
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
—
2
—
2
tA
DataAccessTime
tCLK
Clock Cycle Time
10
4.5
4.5
3
15
6
20
8
tCLKH
tCLKL
tDS
Clock High Time
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0
1
1
tENS
tENH
tLDS
EnableSetupTime
3
4
5
EnableHoldTime
0
1
1
LoadSetupTime
3
4
5
tLDH
LoadHoldTime
ResetPulseWidth(3)
0
1
1
tRS
10
10
10
—
0
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
ResetSetupTime
Reset Recovery Time
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
OutputEnabletoOutputinLowZ(4)
OutputEnabletoOutputValid
OutputEnabletoOutputinHighZ(4)
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
3
4
5
0
0
0
2
3
3
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
—
—
10
20
60
Read Clock to PAE
Clock to HF
tSKEW1
tSKEW2
tSKEW3
Skew time between RCLK and WCLK for FF/IR
Skew time between RCLK and WCLK for PAE and PAF
Skew time between RCLK and WCLK for EF/OR
12
60
15
60
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product fot 15ns and 20ns speed grade are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
680Ω
30pF*
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
4674 drw 04
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
1.5V
*
Includes jig and scope capacitances.
1.5V
SeeFigure2
Figure 2. Output Load
6
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONAL DESCRIPTION
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
TIMINGMODES
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
TheIDT72275/72285supporttwodifferenttimingmodesofoperation:IDT
Standard mode or First Word Fall Through (FWFT) mode. The selection of
whichmodewilloperateisdeterminedduringMasterReset,bythestateofthe
FWFT/SIinput.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
16,386th word for the IDT72275 and 32,770th word for the IDT72285,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (32,769-m) writes for the IDT72275 and (65,537-m)
writes for the IDT72285, where m is the full offset value. The default setting
for this value is stated in the footnote of Table 2.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO has any free space for writing. In the
FWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafter
threeRCLKrisingedges, REN =LOWisnotnecessary. Subsequentwords
must be accessed using the Read Enable (REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepend-
ing on which timing mode is in effect.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 32,769 writes for the IDT72275 and
65,537 writes for the IDT72285, respectively. Note that the additional word
in FWFT mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
theFIFO,ORwillgoHIGHinhibitingfurtherreadoperations.RENisignored
when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthe
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 16,385th word for IDT72275 and 32,769th word for IDT72285
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (32,768-m)
writes for the IDT72275 and (65,536-m) writes for the IDT72285. The offset
“m” is the full offset value. The default setting for this value is stated in the
footnoteofTable1. Thisparameterisalsouserprogrammable. Seesection
on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 32,768 writes for the IDT72275 and 65,536
for the IDT72285, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause the
FIFO to become empty. When the last word has been read from the FIFO,
theEFwillgoLOWinhibitingfurtherreadoperations.RENisignoredwhenthe
FIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72275/
72285 has internal registers for these offsets. Default settings are stated in
the footnotes of Table 1 and Table 2. Offset values can be programmed into
theFIFOinoneoftwoways;serialorparallelloadingmethod. Theselection
oftheloadingmethodisdoneusingtheLD(Load)pin. DuringMasterReset,
the state of the LD input determines whether serial or parallel flag offset
programming is enabled. A HIGH on LD during Master Reset selects serial
loading of offset values and in addition, sets a default PAE offset value of
3FFH (a threshold 1,023 words from the empty boundary), and a default
PAF offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on LD during Master Reset selects parallel loading of offset values,
and in addition, sets a default PAE offset value of 07FH (a threshold 127
words from the empty boundary), and a default PAF offset value of 07FH
(athreshold127wordsfromthefullboundary).SeeFigure3,OffsetRegister
LocationandDefaultValues.
7
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
InadditiontoloadingoffsetvaluesintotheFIFO,italsopossibletoreadthe Foramoredetaileddescription,seediscussionthatfollows.
currentoffsetvalues.Itisonlypossibletoreadoffsetvaluesviaparallelread. The offset registers may be programmed (and reprogrammed) any time
Figure4,ProgrammableFlagOffsetProgrammingSequence,summarizes after Master Reset, regardless of whether serial or parallel programming
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes. has been selected.
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72275
IDT72285
FF
H
H
H
H
H
L
PAF HF PAE EF
0
0
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
(n + 1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m)(2) to32,767
32,768
(n + 1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m)(2) to65,535
65,536
H
H
H
H
L
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72275
IDT72285
0
1 to n+ 1(1)
IR
L
PAF HF PAE OR
0
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+ 1(1)
L
Number of
Words in
FIFO(1)
(n + 2) to 16,385
16,386 to (32,769-(m+1))(2)
(32,769-m)to32,768
32,769
(n + 2) to 32,769
32,770 to (65,537-(m+1))(2)
(65,537-m)to65,536
65,537
L
H
H
H
H
L
L
L
H
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72275 (32,768 x 18 ⎯ BIT)
IDT72285 (65,536 x 18 ⎯ BIT)
15 14
17
17
0
17
17
16 15
0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
0
0
15 14
16 15
FULL OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
DEFAULT VALUE
007FH if LD is LOW at Master Reset,
03FFH if LD is HIGH at Master Reset
4674 drw06
Figure 3. Offset Register Location and Default Values
IDT72275
IDT72285
LD WEN REN SEN
WCLK
RCLK
X
Parallel write to registers:
Empty Offset
0
0
0
1
1
0
1
1
0
Full Offset
Parallel read from registers:
Empty Offset
X
Full Offset
Serial shift into registers:
0
1
1
1
X
30 bits for the IDT72275
32 bits for the IDT72285
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
1
1
X
X
X
No Operation
Write Memory
1
1
0
X
0
X
X
X
X
X
Read Memory
No Operation
1
1
1
X
X
4674 drw07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SERIAL PROGRAMMING MODE
theregister(s)pertainingtothatflag.MeasuringfromtherisingWCLKedgethat
If Serial Programming mode has been selected, as described above, achievestheabovecriteria;PAFwillbevalidaftertwomorerisingWCLKedges
then programming of PAE and PAF values can be achieved by using a plustPAF,PAEwillbevalidafterthenexttworisingRCLKedgesplustPAEplus
combination of the LD, SEN, WCLK and SI input pins. Programming PAE tSKEW2.
andPAFproceedsasfollows:whenLDandSENaresetLOW,dataontheSI
The act of reading the offset registers employs a dedicated read offset
inputarewritten,onebitforeachWCLKrisingedge,startingwiththeEmptyOffset registerpointer.ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
LSBandendingwiththeFullOffsetMSB.Atotalof30bitsfortheIDT72275and pinswhenLDissetLOWandRENissetLOW.DataarereadviaQnfromthe
32bitsfortheIDT72285.SeeFigure13,SerialLoadingofProgrammableFlag EmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.Uponthe
Registers,forthetimingdiagramforthismode.
secondLOW-to-HIGHtransitionofRCLK, dataarereadfromtheFullOffset
Usingtheserialmethod,individualregisterscannotbeprogrammedselec- Register.ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffset
tively.PAEandPAFcanshowavalidstatusonlyafterthecompletesetofbits Register.SeeFigure15, ParallelReadofProgrammableFlagRegisters,for
(foralloffsetregisters)hasbeenentered.Theregisterscanbereprogrammed thetimingdiagramforthismode.
aslongasthecompletesetofnewoffsetbitsisentered.WhenLDisLOWand
SEN is HIGH, no serial write to the registers can occur.
It is permissible to interrupt the offset register read sequence with reads
orwritestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,
Write operations to the FIFO are allowed before and during the serial LD,orbothtogether.WhenRENandLDarerestoredtoaLOWlevel,reading
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot oftheoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
havetooccuratonce.AselectnumberofbitscanbewrittentotheSIinputand betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia the data word that was present on the output lines Qn will be overwritten.
DnbytogglingWEN.WhenWENisbroughtHIGHwithLDandSENrestored
Parallelreadingoftheoffsetregistersisalwayspermittedregardlessofwhich
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI.Ifan timing mode (IDT Standard or FWFT modes) has been selected.
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW
anddeactivateSENortosetSENLOWanddeactivateLD.OnceLDandSEN RETRANSMIT OPERATION
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
The Retransmit operation allows data that has already been read to be
Fromthetimeserialprogramminghasbegun,neitherpartialflagwillbevalid accessedagain.Therearetwostages:first,asetupprocedurethatresetsthe
until the full set of bits required to fill all the offset registers has been written. readpointertothefirstlocationofmemory,thentheactualretransmit,which
MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;PAF consistsofreadingoutthememorycontents,startingatthebeginningofmemory.
willbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalidafter
the next two rising RCLK edges plus tPAE plus tSKEW2.
Itisnotpossibletoreadtheflagoffsetvaluesinaserialmode.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW.Atleastoneword,but
nomorethanD-2wordsshouldhavebeenwrittenintotheFIFObetweenReset
(Master or Partial) and the time of Retransmit setup. D = 32,768 for the
IDT72275 and D = 65,536 for the IDT72285. In FWFT mode, D = 32,769 for
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, the IDT72275 and D= 65,537 for the IDT72285.
then programming of PAE and PAF values can be achieved by using a
If IDT Standard mode is selected, the FIFO will mark the beginning of the
combinationoftheLD,WCLK,WENandDninputpins.ProgrammingPAEand RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
PAFproceedsasfollows:whenLDandWENaresetLOW,dataontheinputs if EF was HIGH before setup. During this period, the internal read pointer is
DnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGHtransition initializedtothefirstlocationoftheRAMarray.
ofWCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,dataarewritten
intotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,onceagain,to maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode
When EF goes HIGH, Retransmit setup is complete and read operations
theEmptyOffsetRegister.SeeFigure14,ParallelLoadingofProgrammable isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
FlagRegisters,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
pointer. The act of reading offsets employs a dedicated read offset register IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
pointer.Thetwopointersoperateindependently;however,areadandawrite setupbysettingORHIGH. Duringthisperiod, theinternalreadpointerisset
shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset tothefirstlocationoftheRAMarray.
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
Write operations to the FIFO are allowed before and during the parallel thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
programmingsequence.Inthiscase,theprogrammingofalloffsetregisters all subsequent words requires a LOW on REN to enable the rising edge of
does not have to occur at one time. One, two or more offset registers can be RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
written and then by bringing LD HIGH, write operations can be redirected to diagram.
theFIFOmemory.WhenLDissetLOWagain,andWENisLOW,thenextoffset
ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HFand
registerinsequenceiswrittento.AsanalternativetoholdingWENLOWand PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
togglingLD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
andtogglingWEN.
thePAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
Notethatthestatusofapartialflag(PAEorPAF)outputisinvalidduringthe thatRTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
programmingprocess.Fromthetimeparallelprogramminghasbegun,apartial risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
flagoutputwillnotbevaliduntiltheappropriateoffsetwordhasbeenwrittento is setup will update PAF. RT is synchronized to RCLK.
10
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
If IDT Standard mode is selected, the FIFO will mark the beginning of the
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperationsmay
begin starting with the first location in memory. Since IDT Standard mode is
selected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH. Duringthisperiod, theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - D17)
Datainputsfor18-bitwidedata.
CONTROLS:
MASTER RESET (MRS)
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray. PAE willgoLOW, PAFwillgoHIGH, andHF willgoHIGH.
IfFWFTisLOWduringMasterResetthentheIDTStandardmode, along
with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT
is HIGH, then the First Word Fall Through mode (FWFT), along with IR and
OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
wordsfromtheemptyboundaryandPAFisassignedathreshold127words
from the full boundary; 127 words corresponds to an offset value of 07FH.
FollowingMasterReset,parallelloadingoftheoffsetsispermitted,butnotserial
loading.
IfLDisHIGHduringMasterReset,thenPAEisassignedathreshold1,023
wordsfromtheemptyboundaryandPAFisassignedathreshold1,023words
fromthefullboundary;1,023wordscorrespondstoanoffsetvalueof3FFH.
FollowingMasterReset,serialloadingoftheoffsetsispermitted,butnotparallel
loading.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
Thisisadualpurposepin. DuringMasterReset, thestateoftheFWFT/SI
inputdetermineswhetherthedevicewilloperateinIDTStandardmodeorFirst
Word Fall Through (FWFT) mode.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmodewill
beselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornotthere
areanywordspresentintheFIFOmemory.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters.Theserialinputfunctioncanonlybe
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
Parallelreadingoftheregistersisalwayspermitted.(Seesectiondescribing
theLDpinforfurtherdetails.)
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRSinputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW,PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmodeor
First Word Fall Through, that mode will remain selected. If the IDT Standard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW.IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged.Theprogrammingmethod(parallelorserial)currentlyactiveatthe
timeofPartialResetisalsoretained.Theoutputregisterisinitializedtoallzeroes.
PRS isasynchronous.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetupand
holdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionoftheWCLK.
ItispermissibletostoptheWCLK.NotethatwhileWCLKisidle,theFF/IR,PAF
andHFflagswillnotbeupdated.(NotethatWCLKisonlycapableofupdating
HF flag to LOW.) The Write and Read Clocks can either be independent or
coincident.
APartialResetisusefulforresettingthedeviceduringthecourseofoperation,
whenreprogrammingpartialflagoffsetsettingsmaynotbeconvenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
WRITE ENABLE (WEN)
RETRANSMIT (RT)
WhentheWENinputisLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
The Retransmit operation allows data that has already been read to be
accessedagain.Therearetwostages:first,asetupprocedurethatresetsthe
readpointertothefirstlocationofmemory,thentheactualretransmit,which
consistsofreadingoutthememorycontents, startingatthebeginningofthe
memory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
REN and WEN must be HIGH before bringing RT LOW.
11
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
selectedcanbeusedtowritetotheregisters.Offsetregisterscanbereadonly
inparallel.ALOWonLDduringMasterResetselectsadefaultPAEoffsetvalue
of07FH(athreshold127wordsfromtheemptyboundary),adefaultPAFoffset
value of 07FH (a threshold 127 words from the full boundary), and parallel
loading of other offset values. A HIGH on LD during Master Reset selects a
default PAE offset value of 3FFH (a threshold 1,023 words from the empty
boundary),adefaultPAFoffsetvalueof3FFH(athreshold1,023wordsfrom
thefullboundary), andserialloadingofotheroffsetvalues.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations.Uponthecompletionofavalidreadcycle,FF
willgoHIGHallowingawritetooccur.TheFFisupdatedbytwoWCLKcycles
+ tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle, IRwillgo
LOWallowingawritetooccur. TheIRflagisupdatedbytwoWCLKcycles+
tSKEW after the valid RCLK cycle.
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
orparallelloadorreadoftheseoffsetvalues.SeeFigure4,ProgrammableFlag
Offset Programming Sequence.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
readontheoutputs, ontherisingedgeoftheRCLKinput. Itispermissibleto
stoptheRCLK.NotethatwhileRCLKisidle,theEF/OR,PAEandHFflagswill
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
OUTPUTS:
FULL FLAG (FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 32,768 for the IDT72275 and 65,536 for the IDT72285). See Figure 7,
WriteCycleandFullFlagTiming(IDTStandardMode),fortherelevanttiming
information.
InFWFTmode,theInputReady(IR)functionisselected.IRgoesLOWwhen
memoryspaceisavailableforwritingindata.Whenthereisnolongeranyfree
space left, IR goes HIGH, inhibiting further write operations. If no reads are
performedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writesto
the FIFO (D = 32,769 for the IDT72275 and 65,537 for the IDT72285) See
Figure 9, Write Timing (FWFT Mode), for the relevant timing information.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
READ ENABLE (REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister.ThedataoutputsQ0-Qnmaintain
the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
wordwrittentoanemptyFIFO,mustberequestedusingREN.Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
furtherreadoperations.RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur.TheEFflagisupdated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW
afterthefirstwrite.RENdoesnotneedtobeassertedLOW.Inordertoaccess
allotherwords,areadmustbeexecutedusingREN.TheRCLKLOWtoHIGH
transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
doubleregister-bufferedoutputs.
EMPTY FLAG (EF/OR)
Thisisadualpurposepin.IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited until OR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
SERIAL ENABLE (SEN)
TheSENinputisanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.SENisalwaysusedinconjunctionwithLD.Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK.(SeeFigure4.)
WhenSENisHIGH,theprogrammableregistersretainstheprevioussettings
andnooffsetsareloaded.SENfunctionsthesamewayinbothIDTStandard
andFWFTmodes.
OUTPUTENABLE(OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister.WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode,ORisatripleregister-bufferedoutput.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD input
determinesoneoftwodefaultoffsetvalues(127or1,023)forthePAEandPAF
flags,alongwiththemethodbywhichtheseoffsetregisterscanbeprogrammed,
parallelorserial.AfterMasterReset,LDenableswriteoperationstoandread
operationsfromtheoffsetregisters.Onlytheoffsetloadingmethodcurrently
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten
totheFIFO.ThePAFwillgoLOWafter(32,768-m)writesfortheIDT72275and
12
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(65,536-m)writesfortheIDT72285.Theoffset“m”isthefulloffsetvalue.The HALF-FULL FLAG (HF)
defaultsettingforthisvalueisstatedinthefootnoteofTable1.
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
InFWFTmode,thePAFwillgoLOWafter(32,769-m)writesfortheIDT72275 beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
and(65,537-m)writesfortheIDT72285, wheremisthefulloffsetvalue. The thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
defaultsettingforthisvalueisstatedinthefootnoteofTable2.
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
SeeFigure16,ProgrammableAlmost-FullFlagTiming(IDTStandardand HIGH.
FWFTMode),fortherelevanttiminginformation.
PAF is synchronous and updated on the rising edge of WCLK.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HFwillgoLOWafter((D/2) + 1)writestotheFIFO, whereD=32,768forthe
IDT72275 and 65,536 for the IDT72285.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
InFWFTmode,ifnoreadsareperformedafterreset(MRSorPRS),HFwill
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO go LOW after ((D-1)/2 + 2) writes to the FIFO, where D = 32,769 for the
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW IDT72275 and 65,537 for the IDT72285.
whentherearenwordsorless in the FIFO. The offset “n” is the empty offset
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
value. The default setting for this value is stated in the footnote of Table 1. fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
In FWFT mode, the PAE will go LOW when there are n+1 words or less WCLK,itisconsideredasynchronous.
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
DATAOUTPUTS(Q0-Q17)
(Q0 - Q17) are data outputs for 18-bit wide data.
andFWFTMode),fortherelevanttiminginformation.
PAE is synchronous and updated on the rising edge of RCLK.
13
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
FWFT/SI
LD
t
RSR
t
FWFT
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4674 drw 08
Figure 5. Master Reset Timing
14
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
PRS
tRSS
tRSR
REN
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
tRSF
FF/IR
PAE
tRSF
tRSF
PAF, HF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
4674 drw09
Figure 6. Partial Reset Timing
15
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
NO WRITE
NO WRITE
tCLKH
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
tDS
tDH
tDS
tDH
D
X
DX+1
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
tA
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4674 drw10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle plus tWFF). If the time
between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
tENS
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
t
A
t
A
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
tOLZ
tOHZ
tOE
OE
(1)
SKEW3
t
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4674 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
16
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
17
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
18
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4674 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit
setup procedure. D = 32,768 for IDT72275 and 65,536 for IDT72285.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
19
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
3
t
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
tRTS
REN
- Q
A
tA
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
(5)
tREF
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4674 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit
setup procedure. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
t
ENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4674 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 14 for the IDT72275 and X = 15 for the IDT72285.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
20
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
t
LDH
ENH
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAE
OFFSET
PAF
OFFSET
D0
- D15
4674 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKL
tCLKH
RCLK
tLDS
tLDH
tLDH
LD
tENS
tENH
tENH
REN
t
A
tA
DATA IN OUTPUT
REGISTER
PAE
OFFSET
PAF
OFFSET
Q
0
- Q15
4674 drw18
NOTE:
1. OE = LOW
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
t
PAF
D - m words in FIFO(2)
D - (m+1) words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4674 drw 19
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
In FWFT mode: D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
21
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
SKEW2
tPAE
t
PAE
1
2
1
2
RCLK
t
ENS
tENH
4674 drw 20
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D-1
[
+ 2]
words in FIFO(2)
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4674 drw 21
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72275 and 65,536 for the IDT72285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72275 and 65,537 for the IDT72285.
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
22
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
problems can be avoided by creating composite flags, that is, ANDing EF of
every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
compositeflagscanbecreatedbyORingORofeveryFIFO, andseparately
ORing IR of every FIFO.
Figure19,BlockDiagramof32,768x36and65,536x36WidthExpansion
demonstratesawidthexpansionusingtwoIDT72275/72285devices. D0-D17
from each device form a 36-bit wide input bus and Q0-Q17 from each device
form a 36-bit wide output bus. Any word width can be attained by adding
additionalIDT72275/72285devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertiontovarybyonecyclebetweenFIFOs. InIDTStandardmode, such
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72275
72285
PROGRAMMABLE (PAE)
72275
72285
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4674 drw 22
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 19. Block Diagram of 32,768 x 36 and 65,536 x 36 Width Expansion
23
IDT72275/72285
CMOS SuperSync FIFO™ 32,768 x 18 and 65,536 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FWFT/SI
•
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
•
READ ENABLE
WRITE ENABLE
INPUT READY
OR
WEN
REN
IDT
72275
72285
IDT
72275
72285
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4674 drw 23
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
TheIDT72275caneasilybeadaptedtoapplicationsrequiringdepthsgreater
than 32,768 and 65,536 for the IDT72285 with an 18-bit bus width. In FWFT
mode, the FIFOs can be connected in series (the data outputs of one FIFO
connectedtothedatainputsofthenext)withnoexternallogicnecessary. The
resultingconfigurationprovidesatotaldepthequivalenttothesumofthedepths
associated with each single FIFO. Figure 20, Block Diagram of 65,536 x 18
and 131,072 x 18 Depth Expansion shows a depth expansion using two
IDT72275/72285devices.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down") until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
EachtimethedatawordappearsattheoutputsofoneFIFO,thatdevice'sOR
line goes LOW, enabling a write to the next FIFO in line.
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW3
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocationstothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
24
ORDERINGINFORMATION
X
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed Package
BLANK
8
Tube or Tray
Tape and Reel
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BLANK
I(1)
G
Green
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Commercial Only
Com'l & Ind'l
Com'l & Ind'l
10
15
20
Clock Cycle Time (tCLK
)
Speed in Nanoseconds
Low Power
L
72275
72285
32,768 x 18 SuperSyncFIFO
65,536 x 18 SuperSyncFIFO
4674 drw 24
NOTES:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
2. Green parts are available, for specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
04/24/2001
02/18/2003
02/11/2009
08/08/2013
pgs. 1, 5, 6, and 25.
pg. 16.
pgs. 1 and 25.
pgs. 3, 13, 23-25.
CORPORATE HEADQUARTERS
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San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
25
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