IDT723613L20PFG8 [IDT]
FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP120, TQFP-120;
| 型号： | IDT723613L20PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 64X36, 12ns, Synchronous, CMOS, PQFP120, TQFP-120 先进先出芯片 |
| 文件： | 总26页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS CLOCKED FIFO WITH
BUS-MATCHING AND
IDT723613
BYTE SWAPPING 64 x 36
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin quad flatpack (PQFP) or space-saving
120-pin thin quad flatpack (TQFP)
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
• 64 x 36 storage capacity FIFO buffering data from Port A to
Port B
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36 bits (long word), 18-bits (word),
and 9 bits (byte)
• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro-
nous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto67MHz
andhasread-accesstimesasfastas10ns.The64x36dual-portSRAMFIFO
buffersdatafromportAtoportB.TheFIFOhasflagstoindicateemptyandfull
conditions,andtwoprogrammableflags,Almost-Full(AF)andAlmost-Empty
(AE),toindicatewhenaselectednumberofwordsisstoredinmemory.FIFO
dataonportBcanbeoutputin36-bit,18-bit,and9-bitformatswithachoiceof
big-orLittle-Endianconfigurations.Threemodesofbyte-orderswappingare
possiblewithanybus-sizeselection.Communicationbetweeneachportcan
bypass theFIFOviatwo36-bitmailboxregisters.Eachmailboxregisterhas
a flagtosignalwhen newmailhas beenstored. Parityis checkedpassively
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• FF, AF flags synchronized by CLKA
• EF, AE flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
MBF1
PEFB
Parity
Gen/Check
Mail 1
Register
RST
PGB
Device
Control
ODD/
EVEN
RAM ARRAY
64 x 36
64 x 36
36
36
Read
Pointer
Write
Pointer
B0 - B35
Status Flag
FF
AF
EF
Logic
AE
FIFO
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Programmable
Flag Offset
Registers
FS
0
1
Port-B
FS
Control
A - A35
0
Logic
PGA
Mail 2
Register
Parity
Gen/Check
3145 drw01
PEFA
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnologyInc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MARCH 2002
1
DSC-3145/1
©
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
DESCRIPTION(CONTINUED)
anotherandcanbeasynchronousorcoincident.Theenablesforeachportare
arrangedtoprovideasimpleinterfacebetweenmicroprocessorsand/orbuses
withsynchronousinterfaces.
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronizedtotheportclock(CLKA)thatwritesdataintoitsarray.TheEmpty
Flag(EF)andAlmost-Empty(AE)flagoftheFIFOaretwo-stagesynchronized
totheportclock(CLKB)thatreads datafromits array.
on each port and may be ignored if not desired. Parity generation can be
selected for data read from each port. Two or more devices may be used in
paralleltocreatewiderdatapaths.
The IDT723613 is a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
to the LOW-to-HIGH transition of a continuous (free-running) port clock by
enable signals. The continuous clocks foreachportare independentofone
The IDT723613 is characterized for operation from 0°C to 70°C.
PINCONFIGURATIONS
A
A
A
23
22
21
1
B
22
21
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
B
3
GND
GND
4
B
B
B
B
B
B
B
B
B
B
B
20
19
18
17
16
15
14
13
12
11
10
A
A
A
A
A
A
A
A
A
A
A
20
19
18
17
16
15
14
13
12
11
10
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
9
A
A
9
8
7
B
8
B
7
A
VCC
V
CC
B
6
A
6
5
4
3
B
5
A
B
4
A
B
3
A
GND
GND
B
2
A
2
1
0
B
1
A
B
0
A
EF
AE
NC
NC
NC
3145 drw02
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
NOTE:
1. NC = No internal connection.
2
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINCONFIGURATIONS(CONTINUED)
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
EF
*
A
0
B
0
A
1
B
1
A
2
B
2
GND
GND
A
3
B
3
A
4
B
4
A
5
B
5
A
6
CC
B
6
V
VCC
A
7
B
7
A
8
B
8
A
9
B
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
GND
94
A
A
A
A
A
A
15
16
17
18
19
20
B
B
B
B
B
B
15
16
17
18
19
20
93
92
91
90
89
88
GND
GND
87
A21
A22
A23
B21
B22
B23
86
85
84
3145 drw03
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP(2) (PQ132-1, ORDER CODE: PQF)
TOP VIEW
NOTES:
1. NC = No internal connection.
2. Uses Yamaichi socket IC51-1324-828.
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
Port A Data
36-bit bidirectional data port for side A.
Almost-Empty Flag
Almost-Full Flag
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit
Port B words in the FIFO is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty location
Port A in the FIFO is less than or equal to the value in the offset register, X.
AF
O
B0-B35
Port B Data
I/O
I
36-bit bidirectional data port for side B
B E
Big-Endian Select
Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most significant
bytes on B0-B35 for use, and a HIGH selects the least significant bytes.
CLKA
CLKB
Port A Clock
Port B Clock
I
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
CSB
EF
Port A Chip Select
Port B Chip Select
Empty Flag
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0-B35 outputs are in the high-impedance state when CSB is HIGH.
O
EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and
Port B reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is
HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition
of CLKB after data is loaded into empty FIFO memory.
ENA
ENB
FF
Port A Enable
Port B Enable
Full Flag
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and writes
O
Port A to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after reset.
FS1, FS0
MBA
Flag Offset Selects
Port A Mailbox Select
Mail1 Register Flag
I
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the Almost-Full flag and Almost-Empty flag offsets.
I
A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
outputs are active, mail2 register data is output.
MBF1
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the
device is reset.
MBF2
Mail2 Register Flag
O
I
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to
the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition
of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/
EVEN
Odd/Even Parity Select
Port A Parity Error Flag
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD
EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
PEFA
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17,
(Port A) A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35
inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore,
if a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH
and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of the A0-A35 inputs.
PEFB
Port B Parity Error Flag
O
When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8,
(PortB) B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte serving as the parity bit. A byte is
valid when it is used by the bus size selected for port B. The type of parity checked is determined by the
state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1
register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity
generation is set up by having CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB
HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs.
4
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/O
Description
PGA
Port A Parity Generation
I
Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity
generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17,
A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB
Port B Parity
Reset
I
I
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and
B27-B35. The generated parity bits are output in the most significant bit of each byte.
RST
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF
flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select
Almost-Full flag and Almost-Empty flag offset.
SIZ0,
SIZ1
Port B Bus Size Selects
Port B Byte Swap Selects
I
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to
(Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be
long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit
write or read.
SW0,
SW1
I
At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by
(Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte order
swapping is possible with any bus-size selection.
W/RA
W/RB
Port A Write/Read Select
Select
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
Port B Write/Read Select
I
A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE
RANGE(UNLESSOTHERWISENOTED)(1)
Symbol
VCC
VI(2)
VO(2)
IIK
Rating
Commercial
–0.5 to 7
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
Supply Voltage Range
Input Voltage Range
V
Output Voltage Range
V
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
Storage Temperature Range
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±500
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Max.
5.5
—
0.8
–4
Unit
Supply Voltage
V
High-Level Input Voltage
Low-Level Input Voltage
V
VIL
—
—
—
0
V
IOH
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
mA
mA
°C
IOL
8
TA
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723613
(1)
Commercial & Industrial
TA = 15, 20 ns
Parameter
Test Conditions
Min.
Typ.(2) Max.
Unit
VOH
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
VCC = 5.5V,
VI = 0
IOH = –4 mA
IOL = 8 mA
VI = VCC or 0
VO = VCC or 0
IO = 0 mA,
f = 1 MHz
2.4
—
—
—
—
—
4
—
0.5
±50
±50
1
V
VOL
II
—
—
—
—
—
—
V
µ A
µ A
mA
pF
IOZ
ICC(3)
C i
VI = VCC or GND
—
Co
VO = 0,
f = 1 MHz
8
—
pF
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device. All other speed grades are available by special order.
2. All typical values are at VCC = 5V, TA = 25°C.
3. For additional ICC information, see the following page.
6
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
400
VCC = 5.5V
f
data
= 1/2 f
S
350
300
T
A
= 25°C
C
L
= 0 pF
250
200
VCC = 5V
VCC = 4.5V
150
100
50
0
80
0
10
20
30
40
50
60
70
3145 drw04
fS
Clock Frequency
MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
CALCULATING POWER DISSIPATION
The ICCf current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723613 with CLKA and CLKB set to
fS. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with
the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723613 may be calculated by:
PT = VCC x ICC(f) + Σ[CL x (VOH – VOL)2 x fo)
where:
CL
fo
VOH
VOL
=
=
=
=
output capacitive load
switching frequency of an output
output high-level voltage
output high-level voltage
When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.29mA/MHz
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Commercial
IDT723613L15
Com’l & Ind’l(1)
IDT723613L20
Symbol
fS
Parameter
Min.
–
Max.
Min.
–
Max.
50
–
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
66.7
–
tCLK
tCLKH
tCLKL
tDS
15
6
20
8
Pulse Duration, CLKA and CLKB HIGH
–
–
ns
Pulse Duration, CLKA and CLKB LOW
6
–
8
–
ns
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
4
–
5
–
ns
tENS
Setup Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB,W/RB, and ENB before
CLKB↑
5
–
5
–
ns
tSZS
Setup Time, SIZ0, SIZ1,and BE before CLKB↑
Setup Time, SW0 and SW1 before CLKB↑
Setup Time, ODD/EVEN and PGB before CLKB↑(2)
Setup Time, RST LOW before CLKA↑ or CLKB↑(3)
Setup Time, FS0 and FS1 before RST HIGH
4
5
4
5
5
1
1
2
0
0
5
4
8
14
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
7
5
6
6
1
1
2
0
0
6
4
8
16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSWS
tPGS
tRSTS
tFSS
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB after CLKB↑
Hold Time, SIZ0, SIZ1, and BE after CLKB↑
tENH
tSZH
tSWH
tPGH
tRSTH
tFSH
Hold Time, SW0 and SW1 after CLKB↑
Hold Time, ODD/EVEN and PGB after CLKB↑(2)
Hold Time, RST LOW after CLKA↑ or CLKB↑(3)
Hold Time, FS0 and FS1 after RST HIGH
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EF and FF
tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ for AE and AF
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
8
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
Commercial
IDT723613L15
Com’l & Ind’l(1)
IDT723613L20
Symbol
tA
Parameter
Access Time, CLKA↑ to A0-A35 and CLKB↑to B0-B35
Propagation Delay Time, CLKA↑ to FF
Min.
2
Max.
Min.
2
Max.
12
Unit
ns
10
10
10
10
10
9
tWFF
tREF
2
2
12
ns
Propagation Delay Time, CLKB↑ to EF
2
2
12
ns
tPAE
Propagation Delay Time, CLKB↑ to AE
2
2
12
ns
tPAF
Propagation Delay Time, CLKA↑ to AF
2
2
12
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2
LOW or MBF1 HIGH
1
1
12
ns
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3)
3
2
1
3
3
2
1
11
11
11
10
11
12
11
3
2
1
3
3
2
1
12
12
ns
ns
ns
ns
ns
ns
ns
(4)
tPPE
Propagation delay time, CLKB↑ to PEFB
tMDV
Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid
11.5
11
tPDPE
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
tPOPE
12
(5)
tPOPB
Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35)
13
tPEPE
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB,
SIZ1, SIZ0, or PGB to PEFB
12
(5)
tPEPB
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35);
CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
3
12
3
13
ns
tRSF
tEN
Propagation Delay Time, RST to AE, EF LOW and AF, MBF1, MBF2 HIGH
1
2
15
10
1
2
20
12
ns
ns
Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to
B0-B35 active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB
LOW to B0-B35 at high impedance
1
8
1
9
ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active.
4. Only applies when a new port-B bus size is implemented by the rising CLKB edge.
5. Only applies when reading data from a mail register.
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
FIFOtotheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKBwhenCSB
is LOW, W/RBis LOW, ENBis HIGH, EFB is HIGH, andeitherSIZ0orSIZ1
is LOW (see Table 3).
FUNCTIONALDESCRIPTION
RESET (RST)
Thesetupandhold-timeconstraintstotheportclocksfortheportChipSelects
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata
outputs. IfaportenableisLOWduringaclockcycle,theport’sChipSelectand
Write/Readselectcanchangestatesduringthesetupandholdtimewindowof
thecycle.
The IDT723613 is reset by taking the Reset (RST) input LOW for at least
four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A
device reset initializes the internal read and write pointers of the FIFO and
forcestheFullFlag(FF)LOW,theEmptyFlag(EF)LOW,theAlmost-Empty
flag (AE) LOW, and the Almost-Full flag (AF) HIGH. A reset also forces the
Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two
LOW-to-HIGH transitions of CLKA. The device must be reset after power
up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the value selected by the Flag Select
(FS0,FS1)inputs. Thevaluesthatcanbeloadedintotheregisterareshown
in Table 1.
SYNCHRONIZED FIFO FLAGS
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages.
This is done to improve the flags’ reliability by reducing the probability of
metastable events on their outputs when CLKA and CLKB operate asyn-
chronously to one another. FF and AF are synchronized to CLKA. EF and
AE are synchronized to CLKB. Table 4 shows the relationship of each port
flag to the level of FIFO fill.
FIFO WRITE/READ OPERATION
EMPTY FLAG (EF)
The state of the port A data (A0-A35) outputs is controlled by the port-A
Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35
outputsareinthehigh-impedancestatewheneitherCSAorW/RAisHIGH.The
A0-A35 outputs are active when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSA is LOW, W/RAis HIGH, ENAis HIGH, MBAis
LOW, and FFA is HIGH (see Table 2).
The FIFO Empty Flag is synchronized to the port clock that reads data
from its array (CLKB). When the EF is HIGH, new data can be read to the
FIFO output register. When the EF is LOW, the FIFO is empty and
attempted FIFO reads are ignored. When reading the FIFO with a byte or
word size on port B, EF is set LOW when the fourth byte or second word of
the last long word is read.
The FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls the EF monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is empty, empty+1, or empty+2. A word written to the FIFO
can be read to the FIFO output register in a minimum of three port B clock
(CLKB)cycles. Therefore,anEFisLOWifawordinmemoryisthenextdata
tobesenttotheFIFOoutputregisterandtwoCLKBcycleshavenotelapsed
since the time the word was written. The EF of the FIFO is set HIGH by the
second LOW-to-HIGH transition of CLKB, and the new data word can be
read to the FIFO output register in the following cycle.
ThestateoftheportBdata(B0-B35)outputsiscontrolledbytheportBChip
Select(CSB)andtheportBWrite/Readselect(W/RB).TheB0-B35outputsare
inthe high-impedance state wheneitherCSB orW/RBis HIGH. The B0-B35
outputsareactivewhenbothCSBandW/RBareLOW. Dataisreadfromthe
TABLE 1 FLAG PROGRAMMING
Almost-Full and
ALOW-to-HIGHtransitiononCLKBbeginsthefirstsynchronizationcycle
ofawriteiftheclocktransitionoccursattimetSKEW1 orgreaterafterthewrite.
Otherwise, the subsequent CLKB cycle can be the first synchronization
cycle (see Figure 10).
FS1
FS0
RST
Almost-Empty Flag
Offset Register (X)
H
H
L
L
H
L
H
L
↑
↑
↑
↑
16
12
8
4
TABLE 2 PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
A0-A35 Outputs
Port Function
X
X
X
X
X
↑
In high-impedance state
In high-impedance state
In high-impedance state
In high impedance state
Active, mail2 register
Active, mail2 register
Active, mail2 register
Active, mail2 register
None
H
L
X
None
L
H
H
L
FIFO write
L
H
H
H
↑
Mail1 write
L
L
L
L
X
↑
None
L
L
H
L
None
None
L
L
L
H
X
↑
L
L
H
H
Mail2 read (set MBF2 HIGH)
10
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
SIZ1, SIZ0
CLKB
B0-B35 Outputs
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
Port Function
X
X
X
X
X
↑
None
H
L
X
None
L
H
H
One, both LOW
Both HIGH
One, both LOW
One, both LOW
Both HIGH
Both HIGH
None
Mail2 write
L
H
H
↑
L
L
L
X
↑
None
L
L
H
FIFO read
L
L
L
X
↑
None
L
L
H
Active mail1 register
Mail1 read (set MBF1 HIGH)
aFIFOwritefortheAEflagtoreflectthenewleveloffill. Therefore,theAEflag
ofaFIFOcontaining(X+1)ormorelongwordsremainsLOWiftwoCLKBcycles
havenotelapsedsincethewritethatfilledthememorytothe(X+1)level. The
AEflagissetHIGHbythesecondCLKBLOW-to-HIGHtransitionaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofCLKB
beginsthefirstsynchronizationcycle ifitoccursattimetSKEW2orgreaterafter
thewritethatfillstheFIFOto(X+1)longwords. Otherwise,thesubsequentCLKB
cycle canbe the firstsynchronizationcycle (see Figure 12).
FULL FLAG (FF)
TheFIFOFullFlagissynchronizedtotheportclockthatwritesdatatoitsarray
(CLKA). WhentheFF isHIGH,aSRAMlocationisfreetoreceivenewdata.
NomemorylocationsarefreewhentheFFisLOWandattemptedwritestothe
FIFO are ignored.
Each time a word is written to the FIFO, its write-pointer is incremented.
The state machine that controls the FF monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM status is full, full-1,
or full-2. From the time a word is read from the FIFO, its previous memory
locationisreadytobewritteninaminimumofthreeCLKAcycles.Therefore,
a FF is LOW if less than two CLKA cycles have elapsed since the next
memorywrite locationhas beenread. The secondLOW-to-HIGHtransition
ontheFF synchronizingclockafterthe readsets the FF HIGHanddata can
be written in the following clock cycle.
ALMOST FULL FLAG (AF)
TheFIFOAlmost-Fullflagissynchronizedtotheportclockthatwritesdata
to its array (CLKA). The state machine that controls an AF flag monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is almost -full, almost- full-1, or almost-full-2. The almost-full
state is defined by the value of the Almost-Full and Almost-Empty Offset
register (X). This register is loaded with one of four preset values during a
devicereset(seeresetabove). TheAFflagisLOWwhentheFIFOcontains
(64-X) or more long words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less long words.
ALOW-to-HIGHtransitiononCLKAbeginsthefirstsynchronizationcycle
ofareadiftheclocktransitionoccursattimetSKEW1orgreateraftertheread.
Otherwise,thesubsequentclockcyclecanbethefirstsynchronizationcycle
(see Figure 11).
Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required
aftera FIFOreadfortheAF flagtoreflectthe newleveloffill. Therefore, the
AF flag of a FIFO containing [64-(X+1)] or less words remains LOW if two
CLKA cycles have not elapsed since the read that reduced the number of
long words in memory to [64-(X+1)]. The AF flag is set HIGH by the second
CLKALOW-to-HIGHtransitionaftertheFIFOreadthatreducesthenumber
oflongwords inmemoryto[64-(X+1)]. ALOW-to-HIGHtransitiononCLKA
beginsthefirstsynchronizationcycleifitoccursattimetSKEW2orgreaterafter
the read that reduces the number of long words in memory to [64-(X+1)].
Otherwise, the subsequent CLKA cycle can be the first synchronization
cycle (see Figure 13).
ALMOST-EMPTY FLAG (AE)
The FIFO Almost-Empty flag is synchronized to the port clock that reads
data from its array (CLKB). The state machine that controls the AE flag
monitors a write-pointer and read-pointer comparator that indicates when
theFIFOSRAMstatusisalmost-empty,almost-empty+1,oralmost-empty+2.
The almost-empty state is defined by the value of the Almost-Full and
Almost-Empty Offset register (X). This register is loaded with one of four
preset values during a device reset (see reset above). The AE flag is LOW
when the FIFO contains X or less long words in memory and is HIGH when
the FIFO contains (X+1) or more long words.
TwoLOW-to-HIGHtransitionsontheportBClock(CLKB)arerequiredafter
MAILBOX REGISTERS
Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass
commandandcontrolinformationbetweenportAandportBwithoutputting
it in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the
mail1registerwhena portAwrite is selectedbyCSA, W/RA, andENA(with
MBA HIGH). A LOW-to-HIGH transition on CLKB writes B0-B35 data to the
mail2 register when a port B write is selected by CSB, W/RB, andENB(and
both SIZ0 and SIZ1 are HIGH). Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail
register are ignored while its mail flag is LOW.
WhentheportBdata(B0-B35)outputsareactive,thedataonthebuscomes
fromtheFIFOoutputregisterwheneitheroneorbothSIZ1andSIZ0areLOW
and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1
RegisterFlag(MBF1)is setHIGHbyarisingCLKBedgewhenaportBread
TABLE 4 FIFO FLAG OPERATION
Number of 36-Bit
Words in the FIFO
Synchronized
to CLKB
Synchronized
to CLKA
(1)
EF
L
AE
L
AF
H
H
H
L
FF
0
1 to X
H
H
H
H
L
H
H
H
H
L
(X + 1) to [64 – (X + 1)]
(64 – X) to 63
64
H
H
H
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
is selected by CSB, W/RB, and ENB, (and both SIZ1 and SIZ0 HIGH). The SIZ1areHIGH,themail1registerisaccessedforaportBlong-wordreadand
Mail2 Register Flag (MBF2) is set HIGH by a rising CLKA edge when a port themail2registerisaccessedforaportBlong-wordwrite.Themailregisteris
Areadis selectedbyCSA, W/RA,andENA(withMBAHIGH). Thedataina accessedimmediatelyandanybus-sizingoperationthatcanbeunderwayis
mailregisterremainsintactafteritisreadandchangesonlywhennewdatais unaffectedbythemailregisteraccess.Afterthemailregisteraccessiscomplete,
writtentotheregister.
thepreviousFIFOaccesscanresumeinthenextCLKBcycle.Thelogicdiagram
inFigure3showsthepreviousbus-sizeselectionispreservedwhenthemail
registersareaccessedfromportB.AportBbus-sizeisimplementedoneach
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9- risingCLKBedgeaccordingtothestates ofSIZ0_Q,SIZ1_Q,andBE_Q.
bit byte format for data read from the FIFO. Word- and byte-size bus
selections can utilize the most significant bytes of the bus (Big-Endian) or PARITY CHECKING
least significant bytes of the bus (Little-Endian). Port B bus-size can be
changed dynamically and synchronous to CLKB to communicate with four parity trees to check the parity of incoming (or outgoing) data. A parity
peripherals of various bus widths. failure on one or more bytes of the port A data bus is reported by a low level
TheportAdatainputs(A0-A35) andportBdatainputs(B0-B35)eachhave
ThelevelsappliedtotheportBbus-sizeselect(SIZ0,SIZ1)inputsandthe on the port A Parity Error Flag (PEFA). A parity failure on one or more bytes
Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH of the port B data inputs that are valid for the bus-size implementation is
transition. The stored port B bus-size selection is implemented by the next reported by a low level on the port B Parity Error Flag (PEFB). Odd or Even
rising edge on CLKB according to Figure 2.
parity checking can be selected, and the Parity Error Flags can be ignored
Only 36-bit long-word data is written to or read from the FIFO memory on if this feature is not desired.
the IDT723613. Bus-matching operations are done after data is read from
Parity status is checked on each input bus according to the level of the
the FIFO RAM. Port B bus sizing does not apply to mail register operations. Odd/Even parity (ODD/EVEN) select input. A parity error on one or more
valid bytes of a port is reported by a LOW level on the corresponding port
BUS-MATCHING FIFO READS
ParityErrorFlag(PEFA,PEFB)output. PortAbytesarearrangedasA0-A8,
Datais readfromtheFIFORAMin36-bitlong-wordincrements.Ifalong- A9-A17, A18-A26, and A27-A35, and port B bytes are arranged as B0-B8, B9-
wordbus-sizeisimplemented,theentirelongwordimmediatelyshiftstothe B17, B18-B26, andB27-B35, andits validbytes are those usedina portBbus
FIFOoutputregisteruponaread.Ifbyteorwordsizeisimplementedonport size implementation. When Odd/Even parity is selected, a port Parity Error
B, only the first one or two bytes appear on the selected portion of the FIFO Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number
output register, with the rest of the long word stored in auxiliary registers. In of LOW levels applied to its bits.
this case, subsequent FIFO reads with the same bus-size implementation
output the rest of the long word to the FIFO output register in the order mail2registerwhenparitygenerationisselectedforport-Areads(PGA=HIGH).
shown by Figure 2. WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
The four parity trees used to check the A0-A35 inputs are shared by the
Each FIFO read with a new bus-size implementation automatically un- CSA LOW, ENAHIGH, W/RALOW, MBAHIGH, andPGAHIGH, the portA
loads data from the FIFO RAM to its output register and auxiliary registers. ParityErrorFlag(PEFA)is heldHIGHregardless ofthelevels appliedtothe
Therefore,implementinganewportBbus-sizeandperformingaFIFOread A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
before all bytes or words stored in the auxiliary registers have been read sharedbythemail1registerwhenparitygenerationisselectedforportBreads
results in a loss of the unread data in these registers.
(PGB=HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
When reading data from FIFO in byte or word format, the unused B0-B35 isselectedwithCSBLOW,ENBHIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
outputs remain inactive but static, with the unused FIFO output register bits andPGBHIGH,theportBParityErrorFlag(PEFB)isheldHIGHregardless
holding the last data value to decrease power consumption.
ofthelevels appliedtotheB0-B35 inputs.
BYTE SWAPPING
PARITY GENERATION
The byte-order arrangement of data read from the FIFO can be changed
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
synchronous to the rising edge of CLKB. Byte-order swapping is not Generate select (PGB) enables the IDT723613 to generate parity bits for
available formailregisterdata. Fourmodes ofbyte-orderswapping(includ- portreadsfromaFIFOormailboxregister. PortAbytesarearrangedasA0-
ing no swap) can be done with any data port size selection. The order of the A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte
bytes are rearranged within the long word, but the bit order within the bytes usedas the paritybit. PortBbytes are arrangedas B0-B8, B9-B17, B18-B26,
remainsconstant.
and B27-B35, with the most significant bit of each byte used as the parity bit.
BytearrangementischosenbytheportBSwapselect(SW0,SW1)inputs A write to a FIFO or mail register stores the levels applied to all nine inputs
on a CLKB rising edge that reads a new long word from the FIFO. The byte of a byte regardless of the state of the Parity Generate select (PGA, PGB)
order chosen on the first byte or first word of a new long word read from the inputs. When data is read from a port with parity generation selected, the
FIFOismaintaineduntiltheentirelongwordistransferred,regardlessofthe lowereightbitsofeachbyteareusedtogenerateaparitybitaccordingtothe
SW0 and SW1 states during subsequent reads. Figure 4 is an example of levelontheODD/EVENselect. Thegeneratedparitybitsaresubstitutedfor
the byte-order swapping available for long word reads. Performing a byte thelevelsoriginallywrittentothemostsignificantbitsofeachbyteastheword
swapandbus-sizesimultaneouslyforaFIFOreadfirstrearrangesthebytes is read to the data outputs.
as shown in Figure 4, then outputs the bytes as shown in Figure 2.
Paritybits forFIFOdataaregeneratedafterthedatais readfromSRAM
andbeforethedataiswrittentotheoutputregister. Therefore,theportAParity
Generateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)havesetup
PORT-B MAIL REGISTER ACCESS
InadditiontoselectingportBbussizesforFIFOreads,theportBbusSize and hold time constraints to the port A Clock (CLKA) and the port B Parity
select(SIZ0,SIZ1)inputsalsoaccessthemailregisters.WhenbothSIZ0and Generate select (PGB) and ODD/EVEN select have setup and hold time
12
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A35 A27
A26 A18
A17 A9
A8 A0
BYTE ORDER ON PORT A:
D
Write to FIFO
A
B
C
B35 B27
B26 B18
B17 B9
B8 B0
BE SIZ1 SIZ0
Read from FIFO
A
B
D
C
X
L
L
(a) LONG WORD SIZE
B35 B27
B26 B18
B17 B9
B17 B9
B8 B0
B8 B0
BE
SIZ1 SIZ0
A
B
1st: Read from FIFO
2nd: Read from FIFO
L
L
H
B35 B27
B26 B18
D
C
(b) WORD SIZE
BIG-ENDIAN
B35 B27
B35 B27
B26 B18
B17 B9
B8 B0
BE SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
L
H
B26 B18
B17 B9
B8 B0
A
B
(c) WORD SIZE
LITTLE-ENDIAN
B35 B27
B26 B18
B17 B9
B17 B9
B17 B9
B17 B9
B8 B0
BE SIZ1 SIZ0
A
B35 B27
B
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
B26 B18
B26 B18
B26 B18
B8 B0
B8 B0
B35 B27
C
3rd: Read from FIFO
4th: Read from FIFO
B35 B27
B8 B0
D
(d) BYTE SIZE
BIG-ENDIAN
B35 B27
B35 B27
A35 A27
B35 B27
B26 B18
B17 B9
B8 B0
BE SIZ1 SIZ0
H
H
L
D
1st: Read from FIFO
2nd: Read from FIFO
B26 B18
A26 A18
B17 B9
A17 A9
B17 B9
B8 B0
C
A8 A0
3rd: Read from FIFO
B
B8 B0
A
B26 B18
4th: Read from FIFO
(d) BYTE SIZE
LITTLE-ENDIAN
3145 fig01
Figure 2. Dynamic Bus Sizing
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, and
Write/Readselect(W/RA,W/RB)inputisLOW,themailregisterisselected (MBA
HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generateselect(PGA,PGB)isHIGH. Generatingparityformailregisterdata
doesnotchangethecontentsoftheregister.
constraintstotheportBClock(CLKB).Thesetimingconstraintsonlyapply
forarisingclockedgeusedtoreadanewlongwordtotheFIFOoutputregister.
Thecircuitusedtogenerateparityforthemail1dataissharedbytheportB
bus(B0-B35)tocheckparityandthecircuitusedtogenerateparityforthemail2
data is shared by the port A bus (A0-A35) to check parity. The shared parity
treesofaportareusedtogenerateparitybitsforthedatainamailregisterwhen
CLKB
MUX
G1
1
SIZ0 Q
SIZ1 Q
BE Q
•
D
Q
•
SIZ0
SIZ1
BE
•
1
•
•
3145 fig02
Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register
14
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A35 A27
A26 A18
A17 A9
A8 A0
SW1
SW0
D
A
B
C
L
L
A
B
D
C
B35 B27
B26 B18
B17 B9
B8 B0
(a) NO SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1
L
SW0
H
A
B
C
D
D
C
B
A
B35 B27
B26 B18
B17 B9
B8 B0
(b) BYTE SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1
H
SW0
L
A
B
C
D
C
D
A
B
B35 B27
B26 B18
B17 B9
B8 B0
(c) WORD SWAP
A35 A27
A26 A18
A17 A9
A8 A0
SW1 SW0
A
B
C
D
H
H
B
D
C
A
3145 fig03
(d) BYTE-WORD SWAP
Figure 4. Byte Swapping for FIFO Reads (Long-Word Size Example)
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST
FS1,FS0
FF
0,1
t
WFF
t
WFF
t
REF
EF
AE
AF
t
PAE
t
PAF
t
RSF
MBF1,
MBF2
3145 drw05
Figure 5. Device Reset Loading the X Register with the Value of Eight
tCLK
tCLKH
tCLKL
CLKA
FFA
CSA
HIGH
tENH
tENS
tENH
tENS
W/RA
t
ENH
t
ENS
ENS
MBA
tENH
tENH
t
ENH
t
tENS
tENS
ENA
tDH
t
DS
W1(1)
W2(1)
A0 - A35
No Operation
ODD/
EVEN
tPDPE
tPDPE
PEFA
Valid
Valid
3145 drw06
NOTE:
1. Written to the FIFO.
Figure 6. FIFO Write Cycle Timing
16
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CLKB
EF
HIGH
CSB
W/RB
tENS
tENH
tENH
tENS
ENB
tSWS
No Operation
tSWH
SW1,
SW0
t
t
SZH
t
t
SZS
BE
SZH
SZS
SIZ1,
SIZ0
NOT (1,1)(1)
(0,0)
NOT (1,1)(1)
(0,0)
tPGS
tPGH
PGB,
ODD/
EVEN
tDIS
tEN
tA
tA
W1(2)
W2(2)
Previous Data
B0-B35
3145 drw07
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS
FIFO Data Write
Swap Mode
FIFO Data Read
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B26-B18
B17-B9
B8-B0
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
L
L
L
H
L
A
D
C
B
B
C
D
A
C
B
A
D
D
A
B
C
H
H
H
Figure 7. FIFO Long-Word Read Cycle Timing
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
CLKB
EF
HIGH
CSB
W/RB
tENS
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
SZH
t
t
SZS
SZS
BE
t
SZH
SIZ1,
SIZ0
NOT (1,1) (1)
NOT (1,1)(1)
(0,1)
(0,1)
t
PGS
tPGH
PGB,
ODD/
EVEN
t
EN
tA
t
A
A
tDIS
Little
Previous Data
Read 1
Read 1
Read 2
Read 2
B0-B17
Endian(2)
t
tA
tDIS
Big
Endian(2)
B18-B35
Previous Data
3145 drw08
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR FIFO WORD READS
FIFO Data Read
FIFO Data Write
Swap Mode
Read
No.
Big-Endian
Little-Endian
A35-A27
A26-A18
A17-A9
A8-A0
D
SW1
L
SW0
B35-B27
B26-B18
B17-B9
B8-B0
1
2
A
C
B
D
C
A
D
B
A
A
B
B
C
C
L
1
2
D
B
C
A
B
D
A
C
D
L
H
1
2
C
A
D
B
A
C
B
D
A
A
B
B
C
C
D
D
H
H
L
1
2
B
D
A
C
D
B
C
A
H
Figure 8. FIFO Word Read-Cycle Timing
18
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CLKB
EF
HIGH
CSB
W/RB
tENS
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
t
SZS
SZS
tSZH
BE
t
SZH
SIZ1,
SIZ0
Not (1,1) (1)
(1,0)
(1,0)
(1,0)
(1,0)
(1)
(1)
(1)
Not (1,1)
Not (1,1)
PGH
Not (1,1)
t
tPGS
PGB,
ODD/
EVEN
tDIS
tEN
tA
tA
tA
tA
Read 1
Previous Data
Read 2
Read 3
Read 4
Read 4
B0-B8
tDIS
tA
tA
tA
t
A
B27-B35
Previous Data
Read 1
Read 2
Read 3
3145 drw09
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes hold last FIFO output register data for byte-size reads.
DATA SWAP TABLE FOR FIFO BYTE READS
FIFO Data Read
FIFO Data Write
A26-A18
Swap Mode
Read
No.
Big-
Endian
Little-
Endian
A35-A27
A17-A9
A8-A0
SW1
SW0
B35-B27
B8-B0
1
A
D
2
3
4
B
C
D
C
B
A
A
B
B
B
B
C
D
L
L
H
L
1
2
3
4
D
C
B
A
A
B
C
D
A
A
A
C
C
C
D
D
D
L
H
H
1
2
3
4
C
D
A
B
B
A
D
C
1
2
3
4
B
A
D
C
C
D
A
B
H
Figure 9. FIFO Byte Read-Cycle Timing
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS
tENH
MBA
tENS
tENH
ENA
tDS
FF
tDH
HIGH
W1
A0 - A35
t
t
t
CLKH CLK tCLKL
(1)
SKEW1
1
2
CLKB
t
REF
tREF
EF
FIFO Empty
CSB
LOW
W/RB LOW
SIZ1,
SIZ0
LOW
tENS
tENH
ENB
tA
W1
B0 -B35
3145 drw10
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte read from the
FIFO, respectively.
Figure 10. EF Flag Timing and First Data Read when the FIFO is Empty
20
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKL
tCLKH
CLKB
CSB LOW
W/RB LOW
SIZ1,
SIZ0
LOW
tENH
tENS
ENB
EF HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0 -B35
tCLK
(1)
SKEW1
tCLKH
t
tCLKL
1
2
CLKA
t
WFF
t
WFF
FF
FIFO Full
CSA
LOW
WRA HIGH
tENS
tENH
MBA
tENS
tENH
ENA
tDS
tDH
A0 - A35
To FIFO
3145 drw11
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads
the last word or byte of the long word, respectively.
Figure 11. FF Flag Timing and First Available Write when the FIFO is Full
CLKA
tENH
tENS
ENA
(1)
SKEW2
t
1
2
CLKB
t
PAE
t
PAE
AE
X Long Words in FIFO
(X+1) Long Words in FIFO
ENH
t
t
ENS
ENB
3145 drw12
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long
word, respectively.
Figure 12. Timing for AE when the FIFO is Almost-Empty
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
(1)
SKEW2
t
1
2
CLKA
tENH
tENS
ENA
t
PAF
t
PAF
(64-X) Long Words in FIFO
[64-(X+1)] Long Words in FIFO
AF
CLKB
ENB
t
ENH
tENS
3145 drw13
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L0W, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port-B size of long word is selected for FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the
long word, respectively.
Figure 13. Timing for AF when the FIFO is Almost Full
CLKA
t
ENS
t
ENH
ENH
CSA
W/RA
MBA
tENS
t
tENH
t
ENS
ENS
t
tENH
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
SIZ1, SIZ0
ENB
tENH
tENS
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail1 Register after read)
FIFO Output Register
B0 - B35
4661 drw14
NOTE:
1. Port-B parity generation off (PGB = LOW).
Figure 14. Timing for Mail1 Register and MBF1 Flag
22
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CLKB
t
ENS
ENS
t
ENH
ENH
CSB
t
t
W/RB
t
SZS
t
SZH
SIZ1,
SIZ0
tENS
tENH
ENB
B0 - B35
CLKA
tDH
t
DS
W1
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS
tEN
t
PMR
tDIS
W1 (Remains valid in Mail2 Register after read)
A0 - A35
3145 drw15
NOTE:
1. Port-A parity generation off (PGA = LOW).
Figure 15. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFA
NOTE:
Valid
Valid
Valid
Valid
3145 drw16
1. CSA = LOW and ENA = HIGH.
Figure 16. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
SIZ1,
SIZ0
PGB
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
3145 drw17
NOTE:
1. CSB = LOW and ENB = HIGH.
Figure 17. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB Timing
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
ODD/
EVEN
CSA
LOW
W/RA
MBA
PGA
t
PEPB
t
POPB
tPEPB
tEN
A8, A17,
A26, A35
Generated Parity
Mail2 Data
Generated Parity
Mail2 Data
3145 drw18
NOTE:
1. ENA = HIGH.
Figure 18. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN
CSB
LOW
W/RB
SIZ1,
SIZ0
PGB
t
PEPB
tMDV
t
POPB
tPEPB
tEN
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
3145 drw19
Mail1
Data
NOTE:
1. ENB = HIGH.
Figure 19. Parity Generation Timing when Reading from the Mail1 Register
24
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1kΩ
From Output
Under Test
30 pF (1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
th
High-Level
1.5 V
1.5 V
Input
GND
1.5 V
1.5 V
GND
tS
tW
3 V
3 V
1.5 V
1.5 V
Low-Level
GND
Input
Data,
Enable
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
tPLZ
3 V
≈
3 V
Input
1.5 V
1.5 V
tPD
1.5 V
Low-Level
Output
GND
V
OL
tPD
tPZH
V
OH
V
OH
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
tPHZ
OL
≈OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3145 drw20
Figure 20. Load Circuit and Voltage Waveforms
25
ORDERINGINFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (40°C to +85°C)
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial Only
Com’l & Ind’l
15
20
Clock Cycle Time (tCLK)
Speed in Nanoseconds
L
Low Power
723613
64 x 36 SyncFIFO
3145 drw21
NOTE:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
03/05/2002
pgs. 1, 6, 8, 9, 24 and 26.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
e-mail:FIFOhelp@idt.com
26
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