IDT723633L30TQFP [IDT]
FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP128, TQFP-128;
| 型号： | IDT723633L30TQFP |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 512X36, 15ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片 |
| 文件： | 总28页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
PRELIMINARY
IDT723623
IDT723633
IDT723643
Integrated Device Technology, Inc.
NOTE: There is an errata notice on the last page and the corrections have been incorporated into this document.
• Big- or Little-Endian format for word and byte bus sizes
• Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
FEATURES:
• Memory storage capacity:
IDT723623–256 x 36
IDT723633–512 x 36
IDT723643–1,024 x 36
• Clocked FIFO buffering data from Port A to Port B
• Clock frequencies up to 83 MHz (8 ns access time)
• IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each
has three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word)
and 9 bits (byte)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack
(TQFP)
• High performance sub-micron CMOS technology
•
Industrial temperature range (–40oC to +85oC) is available
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
CLKA
Port-A
Control
Logic
W
ENA
MBA
36
RAM ARRAY
256 x 36
FIFO1
Mail1,
Mail2,
Reset
Logic
512 x 36
1,024 x 36
36
Write
Pointer
Read
Pointer
A0-A35
B
0-B35
Status Flag
Logic
/OR
/IR
36
36
Programmable Flag
Offset Registers
Timing
Mode
FS0/SD
FS
9
CLKB
/RB
ENB
MBB
BE
Port-B
Control
Logic
BM
Mail 2
Register
SIZE
3269 drw 01
The IDT logo is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 1999
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
©1999 Integrated Device Technology, Inc.
DSC-3269/-
1
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asyn-
chronous or coincident. The enables for each port are ar-
ranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
CommunicationbetweeneachportmaybypasstheFIFOs
viatwomailboxregisters.Themailboxregisters'widthmatches
theselectedPortBbuswidth. Eachmailboxregisterhasaflag
(MBF1 and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on these FIFOs: Reset
andPartialReset. Resetinitializesthereadandwritepointers
to the first location of the memory array and selects serial flag
DESCRIPTION:
The IDT723623/723633/723643 is a monolithic, high-
speed, low-power, CMOS unidirectional Synchronous
(clocked) FIFO memory which supports clock frequencies up
to83MHzandhasreadaccesstimesasfastas8ns. The256/
512/1,024 x 36 dual-port SRAM FIFO buffers data in opposite
directions. FIFO data on Port B can output in 36-bit, 18-bit, or
9-bit formats with a choice of big- or Little-Endian configura-
tions.
Thesedevicesare asynchronous(clocked)FIFO, mean-
ing each port employs a synchronous interface. All data
transfers through a port are gated to the LOW-to-HIGH
PIN CONFIGURATION
1
2
CLKB
102
W
ENA
Vcc
101
3
4
5
6
7
8
9
Vcc
100
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
B35
99
B34
98
B33
97
B32
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10
BE/
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
3269 drw 02
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
programming, parallel flag programming, or one of three when a selected number of words written to FIFO memory
possible default flag offset settings, 8, 16 or 64. achieve a predetermined "almost-empty state". AFindicates
Partial Reset also sets the read and write pointers to the when a selected number of words written to the memory
first location of the memory. Unlike Reset, any settings achieve a predetermined "almost-full state".
existing prior to Partial Reset (i.e., programming method and
FF/IRandAFaretwo-stagesynchronizedtotheportclock
partialflagdefaultoffsets)areretained. PartialResetisuseful that writes data into its array. EF/OR and AE are two-stage
since it permits flushing of the FIFO memory without changing synchronized to the port clock that reads data from its array.
any configuration settings.
Programmable offsets for AE and AF are loaded in parallel
These devices have two modes of operation: In the IDT using Port A or in serial via the SD input. The Serial
Standard mode, the first word written to an empty FIFO is Programming Mode pin (SPM) makes this selection. Three
deposited into the memory array. A read operation is required default offset settings are also provided. The AE threshold
to access that word (along with all other words residing in can be set at 8, 16 or 64 locations from the empty boundary
memory). In the First Word Fall Through mode (FWFT), the and the AF threshold can be set at 8, 16 or 64 locations from
first word written to an empty FIFO appears automatically on the full boundary. All these choices are made using the FS0
the outputs, no read operation required (Nevertheless, ac- and FS1 inputs during Reset.
cessing subsequent words does necessitate a formal read
request). The state of the BE/FWFT pin during Reset deter- wider data paths. In First Word Fall Through mode, more than
mines the mode in use. one device may be connected in series to create greater word
The FIFO has a combined Empty/Output Ready Flag (EF/ depths. The addition of external components is unnecessary.
OR ) and a combined Full/Input Ready Flag (FF/IR). The EF If, at any time, the FIFO is not actively performing a
Two or more devices may be used in parallel to create
and FF functions are selected in the IDT Standard mode. EF function, the chip will automatically power down. During the
indicateswhetherornottheFIFOmemoryisempty. FFshows power down state, supply current consumption (ICC) is at a
whetherthememoryisfullornot. TheIRandORfunctionsare minimum. Initiating any operation (by activating control in-
selected in the First Word Fall Through mode. IR indicates puts) will immediately take the device out of the Power Down
whether or not the FIFO has available memory locations. OR state.
shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
The IDT723623/723633/723643 are characterized for op-
erationfrom0°Cto70°C. TheyarefabricatedusingIDT’shigh
The FIFO has a programmable Almost-Empty flag (AE) speed, submicron CMOS technology.
and a programmable Almost-Full flag (AF). AE indicates
3
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
36-bit bidirectional data port for side A.
Port A Data
Almost-
Empty Flag
(Port B)
Programmable Almost-Empty flag synchronized to CLKB. It is LOW
when the number of words in the FIFO is less than or equal to the value in the
Almost-Empty B offset register, X.
AF
Almost-
Full Flag
(Port A)
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when
the number of empty locations in the FIFO is less than or equal to the value in
the Almost-Full A offset register, Y.
B0-B35
Port B Data
I/O
I
36-bit bidirectional data port for side B.
BE/FWFT Big-Endian/
First Word
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-
Endian operation. In this case, depending on the bus size, the most signifi-
cant byte or word written to Port A is read from Port B first. A LOW on BE will
select Little-Endian operation. In this case, the least significant byte or word
written to Port A is read from Port B first. After Master Reset, this pin selects
the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW
Fall Through
selects First Word Fall Through mode. Once the timing mode has been
selected, the level on FWFT must be static throughout device operation.
BM(1)
Bus-Match
Select
(Port B)
I
A HIGH on this pin enables either byte or word bus width on Port B, depend
ing on the state of SIZE. A LOW selects long word operation. BM works with
SIZE and BE to select the bus size and endian arrangement for Port B. The
level of BM must be static throughout device operation.
CLKA
CLKB
CSA
Port A Clock
Port B Clock
I
I
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FF/IR and AF are synchro-
nized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. EF/IR and AEB are synchro-
nized to the LOW-to-HIGH transition of CLKB.
Port A Chip
Select
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or
write on Port A. The A0-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on Port B. The B0-B35 outputs are in the high-impedance state
when CSB is HIGH.
EF/OR
Empty/
Output Ready
Flag
O
This is a dual function pin. In the IDT Standard mode, the EFfunction is selected.
EFindicates whether or not the FIFO memory is empty. In the FWFT mode, the
OR function is selected. OR indicates the presence of valid data on the B0-B35
outputs, available for reading. FF/OR is synchronized to the LOW-to-HIGH
transition of CLKB.
(Port B)
ENA
ENB
FF/IR
Port A Enable
Port B Enable
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on Port B.
Full/Input
Ready Flag
(Port A)
O
This is a dual function pin. In the IDT Standard mode, the FF function is
selected. FF indicates whether or not the FIFO memory is full. In the
FWFT mode, the IR function is selected. IR indicates whether or not there
is space available for writing to the FIFO memory. FF/IR is synchronized
to the LOW-to-HIGH transition of CLKA.
4
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (Continued)
Symbol Name
I/O
Description
FS1/SEN Flag Offset
Select 1/
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Reset, FS1/SEN and FS0/SD, together with
SPM, select the flag offset programming method. Three offset register pro-
gramming methods are available: automatically load one of three
preset values (8, 16, or 64), parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is
used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/
SD into the X and Y registers. The number of bit writes required to program
the offset registers is 16 for the 723623, 18 for the 723633, and 20 for the
723643. The first bit write stores the Y-register MSB and the last bit write
stores the X-register LSB.
Serial Enable,
FS0/SD Flag Offset
Select 0/
I
Serial Data
MBA
MBB
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or
write operation.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a Port B read or
write operation. When the B0-B35 outputs are active, a HIGH level on
MBB selects data from the mail1 register for output and a LOW level selects
FIFO data for output.
MBF1
MBF2
Mail1 Register
Flag
O
O
I
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data
to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B
read is selected and MBB is HIGH. MBF1 is set HIGH following either a
Reset (RS1) or Partial Reset (PRS).
Mail2 Register
Flag
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW.
MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is
selected and MBA is HIGH. MBF2 is set HIGH following either a
Reset (RS2) or Partial Reset (PRS).
RS1/RS2 Resets
A LOW on both pins initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on
RS1 selects the programming method (serial or parallel) and one of three
programmable flag default offsets. It also configures Port B for bus size and
endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RS1 is LOW.
PRS
Partial Reset
I
I
A LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset,
thecurrentlyselectedbussize, endianarrangement, programmingmethod(serial
or parallel), and programmable flag settings are all retained.
SIZE(1)
Bus Size Select
(PortB)
AHIGHonthispinwhenBMisHIGHselectsbytebus(9-bit)sizeonPortB. ALOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with
BM and BE to select the bus size and endian arrangement for Port B. The level
of SIZE must be static throughout device operation.
SPM(1)
W/RA
Serial Program-
I
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
Port A Write/
Read Select
A HIGH selects a write operation and a LOW selects a read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH
impedance state when W/RA is HIGH.
W/RB
Port B Write/
Read Select
I
A LOW selects a write operation and a HIGH selects a read operation on Port B
for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the HIGH
impedance state when W/RB is LOW.
Note:
1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to Vcc or GND.
5
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)(1)
Symbol
VCC
VI(2)
Rating
Commercial
–0.5 to 7
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
Unit
V
Supply Voltage Range
Input Voltage Range
Output Voltage Range
V
VO(2)
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
mA
mA
mA
mA
°C
IOK
±50
IOUT
±50
ICC, IGND Continuous Current Through VCC or GND
Storage Temperature Range
±400
TSTG
NOTES:
–65 to 150
1. Stressesbeyondthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice. Thesearestressratingsonlyandfunctional
operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min. Max. Unit
Supply Voltage
4.5
2
5.5
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Current
Low-Level Output Current
VIL
0.8
–4
8
V
IOH
mA
mA
IOL
TA
Operating Temperature
0
70
°C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723623
IDT723633
IDT723643
Commercial
tA = 12, 15, 20, 30 ns
Parameter
Test Conditions
Min.
Typ.(1) Max.
Unit
VOH
VOL
VCC = 4.5V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
IOH = -4 mA
2.4
V
V
IOL = 8 mA
0.5
ILI
VI = VCC or 0
±5
µA
µA
µA
mA
ILO
VO = VCC or 0
VI = VCC -0.2 V or 0
One Input at 3.4 V,
±5
ICC(2)
∆ICC(2,3)
400
CSA = VIH
CSB = VIH
CSA = VIL
A0-A35
B0-B35
A0-A35
B0-B35
0
0
1
1
1
4
8
Other Inputs at VCC or GND
CSB = VIL
All Other Inputs
CIN
COUT
VI = 0,
f = 1 MHz
f = 1 MHZ
pF
pF
VO = 0,
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see the following page.
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
6
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
300
fdata = 1/2 fS
T
A
= 25°C
CL
= 0pF
250
VCC = 5.5V
V
CC = 5.0V
200
150
100
V
CC = 4.5V
50
0
0
10
20
30
40
50
60
70
80
90
3269 drw 02a
fS – Clock Frequency – MHz
Figure 1. Typical Characteristics: Supply Current vs. Clock Frequency
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the
IDT723623/723633/723643 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each
clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero
capacitance load. Once the capacitance load per data-output channel and the number of IDT723623/723633/723643
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + ∑(CL x VCC X fo)
where:
N
=
number of inputs driven by TTL levels
∆ICC =
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
output capacitance load
dc
CL
fo
=
=
=
switching frequency of an output
When no read or writes are occurring on the IDT723633, the power dissipated by a single clock (CLKA or CLKB) input
running at frequency fS is calculated by:
PT = VCC x fS x 0.184 mA/MHz
7
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURE
723623L12 723623L15 723623L20 723623L30
723633L12 723633L15 723633L20 723633L30
723643L12 723643L15 723643L20 723643L30
Symbol
fS
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
—
12
5
83
—
—
—
—
—
15
6
66.7
—
—
20
8
50
—
—
—
—
—
30
10
10
6
33.4 MHz
tCLK
—
—
—
—
ns
ns
ns
ns
tCLKH
tCLKL
tDS
—
5
6
—
8
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
3
4
—
5
tENS1
tENS2
tRSTS
Setup Time, CSA and W/RA before
CLKA↑; CSB and W/RB before CLKB↑
4
3
5
—
—
—
4.5
4.5
5
—
—
—
5
5
6
—
—
—
6
6
7
—
—
—
ns
ns
ns
Setup Time, ENA, and MBA before
CLKA↑; ENB, and MBB before CLKB↑
Setup Time, RS1 or PRS LOW before CLKA↑
or CLKB↑(1)
tFSS
tBES
Setup Time, FS0 and FS1 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
7.5
7.5
—
—
7.5
7.5
—
—
8.5
8.5
—
—
9.5
9.5
—
—
ns
ns
tSPMS
tSDS
Setup Time, SPM before RS1 HIGH
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
Setup Time, FWFT before CLKA↑
7.5
3
—
—
—
7.5
4
—
—
—
8.5
5
—
—
—
9.5
6
—
—
—
ns
ns
ns
tSENS
3
4
5
6
tFWS
tDH
0
—
—
—
0
1
1
—
—
—
0
1
1
—
—
—
0
1
1
—
—
—
ns
ns
ns
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; 0.5
CSB, W/RB, ENB, and MBB after CLKB↑
tRSTH
tFSH
Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑(1)
Hold Time, FS0 and FS1 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
Hold Time, SPM after RS1 HIGH
4
2
2
2
—
—
—
—
4
2
2
2
—
—
—
—
4
3
3
3
—
—
—
—
5
3
3
3
—
—
—
—
ns
ns
ns
ns
tBEH
tSPMH
tSDH
tSENH
tSPH
Hold Time, FS0/SD after CLKA↑
1
1
—
—
1
1
—
—
1
1
—
—
1
1
—
—
ns
ns
Hold Time, FS1/SEN HIGH after CLKA↑
Hold Time, FS1/SEN HIGH after RS1 HIGH
2
—
—
2
—
—
3
9
—
—
3
—
—
ns
ns
tSKEW1(2) Skew Time, between CLKA↑ and CLKB↑ for EF/OR,
7.5
7.5
11
and FF/IR
tSKEW2(2) Skew Time, between CLKA↑ and CLKB↑ for AE,
12
—
12
—
16
—
20
—
ns
and AF
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB
cycle.
8
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
723623L12 723623L15 723623L20 723623L30
723633L12 723633L15 723633L20 723633L30
723643L12 723643L15 723643L20 723643L30
Symbol
Parameter
Access Time, CLKA↑ to A0-A35 and
CLKB↑ to B0-B35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tA
2
2
1
1
1
0
8
8
8
8
8
8
2
2
1
1
1
0
10
8
2
2
1
1
1
0
12
10
10
10
10
10
2
2
1
1
1
0
15
12
12
12
12
12
ns
ns
ns
ns
ns
ns
tWFF
tREF
tPAE
tPAF
tPMF
Propagation Delay Time, CLKA↑ to FF/IR
Propagation Delay Time, CLKB↑ to EF/OR
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
8
8
8
Propagation Delay Time, CLKA↑ to MBF1
LOW or MBF2 HIGH and CLKB↑ to MBF2
LOW or MBF1 HIGH
8
tPMR
tMDV
Propagation Delay Time, CLKA↑ to B0-B35(1)
2
2
8
8
2
2
10
10
2
2
12
12
2
2
17
15
ns
ns
and CLKB↑ to A0-A35(2)
Propagation Delay Time, MBA to A0-A35
valid and MBB to B0-B35 Valid
tPRF
tEN
Propagation Delay Time, RS1 or PRS LOW
to AEB LOW, AFA, HIGH, MBF1 HIGH,
AEA LOW, AFB HIGH, and MBF2 HIGH
Enable Time, CSA and W/RA LOW to
A0-A35 Activeand CSB LOW and W/RB
HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35
at high-impedanceand CSB HIGH or W/RB
LOW to B0-B35 at high-impedance
1
2
1
10
6
1
2
1
15
10
8
1
2
1
20
12
10
1
2
1
30
14
11
ns
ns
ns
tDIS
6
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
data are transferred through this port. For the following
illustrations, assume that a byte (or word) bus size has been
selected for Port B. (Note that when Port B is configured for
a long word size, the Big-Endian function has no application
and the BE input is a “don’t care”1.)
A HIGH on the BE/FWFT input when the Reset (RS1)
input goes from LOW to HIGH will select a Big-Endian
arrangement. In this case, the most significant byte (word) of
thelongwordwrittentoPortAwillbereadfromPortBfirst;the
least significant byte (word) of the long word written to Port A
will be read from Port B last.
ALOWontheBE/FWFTinputwhentheReset(RS1)input
goes from LOW to HIGH will select a Little-Endian arrange-
ment. In this case, the least significant byte (word) of the long
word written to Port A will be read from Port B first; the most
significant byte (word) of the long word written to Port A will be
readfromPortBlast. RefertoFigure2foranillustrationofthe
BE function.
SIGNAL DESCRIPTION
RESET (RS1/RS2)
After power up, a Reset operation must be performed by
providing a LOW pulse to RS1 and RS2 simultaneously.
Afterwards, the FIFO memory of the IDT723623/723633/
723643 undergoes a complete reset by taking its Reset (RS1/
RS2) input LOW for at least four Port A clock (CLKA) and four
Port B clock (CLKB) LOW-to-HIGH transitions. The Reset
inputs can switch asynchronously to the clocks. A Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Almost-Empty flag (AE) LOW, and the
Almost-Full flag (AF) HIGH. A Reset (RS1) also forces the
Mailboxflag(MBF1)oftheparallelmailboxregisterHIGH, and
at the same time the RS2 and MBF2 operate likewise. After a
Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
clock cycles to begin normal operation.
A LOW-to-HIGH transition on the FlFO Reset (RS1/RS2)
input latches the value of the Big-Endian (BE) input for
determining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on the FlFO Reset (RS1/RS2)
input also latches the values of the Flag Select (FS0, FS1) and
Serial Programming Mode (SPM) inputs for choosing the Al-
most-Full and Almost-Empty offset programming method (see
Almost-EmptyandAlmost-Fullflagoffsetprogramming below).
AfterReset, theFWFTselectfunctionisactive, permitting
a choice between two possible timing modes: IDT Standard
mode or First Word Fall Through (FWFT) mode. Once the
Reset (RS1) input is HIGH, a HIGH on the BE/FWFT input
during the next LOW-to-HIGH transition of CLKA (for FIFO1)
and CLKB (for FIFO2) will select IDT Standard mode. This
mode uses the Empty Flag function (EF) to indicate whether
or not there are any words present in the FIFO memory. It
uses the Full Flag function (FF) to indicate whether or not the
FIFO memory has any free space for writing. In IDT Standard
mode, everywordreadfromtheFIFO, includingthefirst, must
be requested using a formal read operation.
Once the Reset (RS1) input is HIGH, a LOW on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKB (for FIFO2) will select FWFT mode.
This mode uses the Output Ready function (OR) to indicate
whetherornotthereisvaliddataatthedataoutputs(B0-B35).
It also uses the Input Ready function (IR) to indicate whether
or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes
directly to data outputs, no read request necessary. Subse-
quent words must be accessed by performing a formal read
operation.
PARTIAL RESET (PRS)
Each of the two FIFO memories of the IDT723623/
723633/723643 undergoes a limited reset by taking its asso-
ciated Partial Reset (PRS) input LOW for at least four Port A
clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH
transitions. The Partial Reset inputs can switch asynchro-
nously to the clocks. A Partial Reset initializes the internal
read and write pointers and forces the Full/Input Ready flag
(FF/IR)LOW, theEmpty/OutputReadyflag(EF/OR)LOW, the
Almost-Empty flag (AE) LOW, and the Almost-Full flag (AF)
HIGH. A Partial Reset also forces the Mailbox flag (MBF1,
MBF2) of the parallel mailbox register HIGH. After a Partial
Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
clock cycles to begin normal operation
Following Reset, the level applied to the BE/FWFT input
Whatever flag offsets, programming method (parallel or tochoosethedesiredtimingmodemustremainstaticthrough-
serial), and timing mode (FWFT or IDT Standard mode) are out FIFO operation.
currently selected at the time a Partial Reset is initiated, those
settings will be remain unchanged upon completion of the PROGRAMMING THE ALMOST-EMPTY AND ALMOST-
reset operation. A Partial Reset may be useful in the case FULL FLAGS
where reprogramming a FIFO following a Reset would be
inconvenient.
TworegistersintheIDT723623/723633/723643areused
toholdtheoffsetvaluesfortheAlmost-EmptyandAlmost-Full
flags. The Almost-Empty flag (AE) Offset register is labeled
X and Almost-Full flag (AF) Offset register is labeled Y. The
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
This is a dual purpose pin. At the time of Reset, the BE offset registers can be loaded with preset values during the
select function is active, permitting a choice of Big- or Little- reset of a FIFO, programmed in parallel using the FIFO’s Port
Endian byte arrangement for data read from Port B. This A data inputs, or programmed in serial using the Serial Data
selection determines the order by which bytes (or words) of (SD) input (see Table 1).
NOTE:
1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily
“don’t care” (along with unused inputs) must not be left open, rather they must be either HIGH or LOW.
10
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
TABLE 1: FLAG PROGRAMMING
SPM
FS1/SEN
FSO/SD
MRS
X AND Y REGlSTERS(1)
H
H
H
L
H
L
↑
↑
↑
↑
↑
↑
↑
↑
64
H
16
H
H
L
8
Parallel programming via Port A
Serial Programming via SD
reserved
H
L
L
H
H
L
L
L
H
H
L
L
reserved
L
L
reserved
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
To load a FIFO’s Almost-Empty flag and Almost-Full
flag Offset registers with one of the three preset values
listed in Table 1, the Serial Program Mode (SPM) and at
least one of the flag-select inputs must be HIGH during the
LOW-to-HIGH transition of the Reset input (RS1). For
example, to load the preset value of 64 into X and Y, SPM,
FS0 and FS1 must be HIGH when RS1 returns HIGH.
To program the X and Y registers from Port A, perform
a Reset on with SPM HIGH and FS0 and FS1 LOW during
the LOW-to-HIGH transition of RS1. After this reset is
complete, the first four writes to FIFO1 do not store data in
RAM. The first two write cycles load the offset registers in
the order Y, X. The third and fourth write cycle should be
ignored. On the fifth write cycle the FIFO is ready to be
loaded with a data word. See Figure 5, Parallel Program-
ming of the Almost-Full Flag and Almost-Empty Flag Offset
Values after Reset (IDT Standard and FWFT modes), for a
detailed timing diagram. The Port A data inputs used by the
offset registers are (A7-A0), (A8-A0), or (A9-A0) for the
IDT723623, IDT723633 or IDT723643, respectively. The
highest numbered input is used as the most significant bit
of the binary number in each case. Valid programming
values for the registers range from 1 to 252 for the
IDT723623; 1 to 508 for the IDT723633; and 1 to 1,020 for
the IDT723643. After all the offset registers are pro-
grammedfromPortA, theFull/InputReadyflag(FF/IR)isset
HIGH, and both FIFOs begin normal operation.
To program the X and Y registers serially, initiate a
Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH
during the LOW-to-HIGH transition of RS1. After this reset
is complete, the X and Y register values are loaded bit-wise
throughtheFS0/SDinputoneachLOW-to-HIGHtransition
of CLKA that the FS1/SEN input is LOW. Thirty-two-, 36, or
40-bit writes are needed to complete the programming for
the IDT723623, IDT723633, or IDT723643, respectively.
The four registers are written in the order Y, X. The first-bit
write stores the most significant bit of the Y register and the
last-bit write stores the least significant bit of the X register.
Each register value can be programmed from 1 to 508
(IDT723623), 1 to 1,020 (IDT723633), or 1 to 2,044
(IDT723643).
untilallregisterbitsarewritten. FF/IRissetHIGHbytheLOW-
to-HIGH transition of CLKA after the last bit is loaded to allow
normal FIFO operation.
SPM, FS0/SD, and FS1/SEN function the same way in
both IDT Standard and FWFT modes.
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by
Port A Chip Select (CSA) and Port A Write/Read Select (W/
RA). The A0-A35 lines are in the High-impedance state when
either CSA or W/RA is HIGH. The A0-A35 lines are active
outputs when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH (see
Table 2). FIFO writes on Port A are independent of any
concurrent reads on Port B.
The Port B control signals are identical to those of Port A
with the exception that the Port B Write/Read select (W/RB) is
the inverse of the Port A Write/Read select (W/RA). The state
of the Port B data (B0-B35) lines is controlled by the Port B
Chip Select (CSB) and Port B Write/Read select (W/RB). The
B0-B35 lines are in the high-impedance state when either
CSB is HIGH or W/RB is LOW. The B0-B35 lines are active
outputs when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
HIGH, ENB is HIGH, MBB is LOW, and EFB/ORB is HIGH
(see Table 3). FIFO reads on Port B are independent of any
concurrent writes on Port A.
The setup and hold time constraints to the port clocks for
the port Chip Selects and Write/Read selects are only for
enablingwriteandreadoperationsandarenotrelatedtohigh-
impedancecontrolofthedataoutputs. IfaportenableisLOW
during a clock cycle, the port’s Chip Select and Write/Read
select may change states during the setup and hold time
window of the cycle.
When operating the FIFO in FWFT mode and the Output
Ready flag is LOW, the next word written is automatically sent
totheFIFO’soutputregisterbytheLOW-to-HIGHtransitionof
theportclockthatsetstheOutputReadyflagHIGH. Whenthe
Output Ready flag is HIGH, data residing in the FIFO’s
memory array is clocked to the output register only when a
When the option to program the offset registers serially
is chosen, the Full/Input Ready (FF/IR) flag remains LOW
11
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
TABLE 2: PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
A0-A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, mail2 register
Active, mail2 register
Active, mail2 register
Active, mail2 register
PORT FUNCTION
X
H
H
H
L
X
X
X
X
↑
None
L
X
None
L
H
L
FIFO write
L
H
H
↑
Mail1 write
L
L
L
X
↑
None
L
L
H
L
None
None
L
L
L
H
X
↑
L
L
H
H
Mail2 read (set MBF2 HIGH)
TABLE 3: PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
B0-B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
PORT FUNCTION
X
L
X
X
X
X
↑
None
L
X
None
L
L
H
L
None
Mail2 write
L
L
H
H
↑
L
H
H
H
H
L
L
X
↑
None
L
H
L
FIFO read
L
L
H
X
↑
None
L
H
H
Active, mail1 register
Mail1 read (set MBF1 HIGH)
read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
The Empty/Output Ready flag of a FIFO is synchronized
to the port clock that reads data from its array (CLKB). For
WhenoperatingtheFIFOinIDTStandardmode, regard- both the FWFT and IDT Standard modes, the FIFO read
lessofwhethertheEmptyFlagisLOWorHIGH, dataresiding pointer is incremented each time a new word is clocked to its
in the FIFO’s memory array is clocked to the output register output register. The state machine that controls an Output
only when a read is selected using the port’s Chip Select, Ready flag monitors a write pointer and read pointer com-
Write/Read select, Enable, and Mailbox select.
parator that indicates when the FIFO SRAM status is empty,
empty+1, or empty+2.
SYNCHRONIZED FIFO FLAGS
In FWFT mode, from the time a word is written to a FIFO,
Each FIFO is synchronized to its port clock through at it can be shifted to the FIFO output register in a minimum of
least two flip-flop stages. This is done to improve flag-signal three cycles of the Output Ready flag synchronizing clock.
reliability by reducing the probability of metastable events Therefore, an Output Ready flag is LOW if a word in memory
when CLKA and CLKB operate asynchronously to one an- isthenextdatatobesenttotheFlFOoutputregisterandthree
other. FF/IR, and AFare synchronized to CLKA. EF/OR and cycles of the port Clock that reads data from the FIFO have
AE are synchronized to CLKB. Table 4 shows the relation- not elapsed since the time the word was written. The Output
ship of each port flag to the number of words stored in memory. Ready flag of the FIFO remains LOW until the third LOW-to-
HIGH transition of the synchronizing clock occurs, simulta-
EMPTY/OUTPUT READY FLAGS (EF/OR)
neously forcing the Output Ready flag HIGH and shifting the
These are dual purpose flags. In the FWFT mode, the word to the FIFO output register.
Output Ready (OR) function is selected. When the Output-
In IDT Standard mode, from the time a word is written to
Ready flag is HIGH, new data is present in the FIFO output a FIFO, the Empty Flag will indicate the presence of data
register. When the Output Ready flag is LOW, the previous available for reading in a minimum of two cycles of the Empty
data word is present in the FIFO output register and at- Flag synchronizing clock. Therefore, an Empty Flag is LOW
tempted FIFO reads are ignored.
if a word in memory is the next data to be sent to the FlFO
In the IDT Standard mode, the Empty Flag (EF) function outputregisterandtwocyclesoftheportClockthatreadsdata
is selected. When the Empty Flag is HIGH, data is available from the FIFO have not elapsed since the time the word was
in the FIFO’s RAM memory for reading to the output register. written. The Empty Flag of the FIFO remains LOW until the
When the Empty Flag is LOW, the previous data word is second LOW-to-HIGH transition of the synchronizing clock
presentintheFIFOoutputregisterandattemptedFIFOreads occurs, forcing the Empty Flag HIGH; only then can data be
are ignored.
read.
12
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
TABLE 4: FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Synchronized
to CLKA
Number of Words in FIFO
to CLKB
IDT723623(1,2)
IDT723633(1,2)
IDT723643(1,2)
EF/OR
AE
L
AF
H
FF/IR
0
0
0
L
H
H
H
H
L
1 to X1
(X1+1) to [256-(Y1+1)]
(256-Y1) to 255
256
1 to X1
(X1+1) to [512-(Y1+1)]
(512-Y1) to 511
512
1 to X1
(X1+1) to [1,024-(Y1+1)]
(1,024-Y1) to 1,023
1,024
H
H
H
H
L
H
H
H
H
H
L
L
NOTES:
1. X is the almost-empty offset used by AE. Y is the almost-full offset used by AF. Both X and Y are selected during a FIFO reset or Port A
programming.
2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
3. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO
goes unrequested to the output register (no read operation necessary), it is not included in the memory count.
most-empty+2. The Almost-Empty state is defined by the
contents of register X. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmedserially(seeAlmost-EmptyflagandAlmost-Full
flag offset programming above). An Almost-Empty flag is
LOW when its FIFO contains X or less words and is HIGH
when its FIFO contains (X+1) or more words. A data word
present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag
synchronizing clock are required after a FIFO write for its
Almost-Empty flag to reflect the new level of fill. Therefore,
the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost-Empty flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transitionofanAlmost-Emptyflagsynchronizingclockbegins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figure 15).
A LOW-to-HIGH transition on an Empty/Output Ready
flag synchronizing clock begins the first synchronization cycle
of a write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 10 and 11).
FULL/INPUT READY FLAGS (FF/IR)
This is a dual purpose flag. In FWFT mode, the Input
Ready (IR) function is selected. In IDT Standard mode, the
Full Flag (FF) function is selected. For both timing modes,
when the Full/Input Ready flag is HIGH, a memory location is
free in the SRAM to receive new data. No memory locations
are free when the Full/Input Ready flag is LOW and attempted
writes to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the
port clock that writes data to its array (CLKA). For both FWFT
and IDT Standard modes, each time a word is written to a
FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and
read pointer comparator that indicates when the FlFO SRAM
status is full, full-1, or full-2. From the time a word is read from
a FIFO, its previous memory location is ready to be written to
in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is
LOW if less than two cycles of the Full/Input Ready flag
synchronizingclockhaveelapsedsincethenextmemorywrite
location has been read. The second LOW-to-HIGH transition
on the Full/Input Ready flag synchronizing clock after the read
sets the Full/Input Ready flag HIGH.
ALMOST-FULL FLAGS (AF)
The Almost-Full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an Almost-Full flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is almost-full, almost-full-1, or almost-full-2. The Al-
most-Full state is defined by the contents of register Y. These
registersareloadedwithpresetvaluesduringaFlFOresetor,
programmed from Port A, or programmed serially (see Al-
most-Empty flag and Almost-Full flag offset programming
above). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (256-Y), (512-Y),
or (1,024-Y) for the IDT723623, IDT723633, or IDT723643
respectively. An Almost-Full flag is HIGH when the number
of words in its FIFO is less than or equal to [256-(Y+1)],
[512-(Y+1)], or [1,024-(Y+1)] for the IDT723623, IDT723633,
or IDT723643 respectively. Note that a data word present in
the FIFO output register has been read from memory.
A LOW-to-HIGH transition on a Full/Input Ready flag
synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tSKEW1 or greater
after the read. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAGS (AE)
The Almost-Empty flag of a FIFO is synchronized to the
port clock that reads data from its array (CLKB). The state
machine that controls an Almost-Empty flag monitors a write
pointer and read pointer comparator that indicates when the
FIFO SRAM status is almost-empty, almost-empty+1, or al-
13
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-
to-HIGH transition on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed
on A0-A35. For an 18-bit bus size, 18 bits of mailbox data are
placed on A0-A17. (In this case, A18-A35 are indeterminate.)
For a 9-bit bus size, 9 bits of mailbox data are placed on A0-
A8. (In this case, A9-A35 are indeterminate.)
Two LOW-to-HIGH transitions of the Almost-Full flag syn-
chronizing clock are required after a FIFO read for its Almost-Full
flag to reflect the new level of fill. Therefore, the Almost-Full flag
of a FIFO containing [256/512/1,024-(Y+1)] or less words re-
mains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in
memoryto[256/512/1024-(Y+1)]. AnAlmost-FullflagissetHIGH
by the second LOW-to-HIGH transition of its synchronizing clock
after the FIFO read that reduces the number of words in memory
to [256/512/1024-(Y+1)]. A LOW-to-HIGH transition of an Al-
most-Full flag synchronizing clock begins the first synchroniza-
tion cycle if it occurs at time tSKEW2 or greater after the read that
reducesthenumberofwordsinmemoryto[256/512/1024-(Y+1)].
Otherwise, the subsequent synchronizing clock cycle may be the
first synchronization cycle. (See Figure 16).
The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
The Endian Select feature has no effect on mailbox data.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-
bit word, or 9-bit byte format for data read from the FIFO. The
levels applied to the Port B Bus Size Select (SIZE) and the Bus-
Match Select (BM) determine the Port B bus size. These levels
should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Reset, by the
time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either byte-
or word-size. They are referred to as Big-Endian (most
significant byte first) and Little-Endian (least significant byte
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723623/
723633/723643 to pass command and control information
between Port A and Port B without putting it in queue. The
Mailbox Select (MBA, MBB) inputs choose between a mail
register and a FIFO for a port data transfer operation. The
usable width of both the Mail1 and Mail2 registers matches
the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes data to the first). The level applied to the Big-Endian Select (BE) input
Mail1 Register when a Port A write is selected byCSA, W/RA,
and ENA with MBA HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail1 register
employs data lines A0-A35. If the selected Port B bus size is
18 bits, then the usable width of the Mail1 Register employs
data lines A0-A17. (In this case, A18-A35 are don’t care
inputs.) IftheselectedPortBbussizeis9bits,thentheusable
width of the Mail1 Register employs data lines A0-A8. (In this
case, A9-A35 are don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data
to the Mail2 Register when a Port B write is selected by CSB,
W/RB, and ENB with MBB HIGH. If the selected Port B bus
sizeisalso36bits, thentheusablewidthoftheMail2employs
data lines B0-B35. If the selected Port B bus size is 18 bits,
thentheusablewidthoftheMail2Registeremploysdatalines
B0-B17. (In this case, B18-B35 are don’t care inputs.) If the
selected Port B bus size is 9 bits, then the usable width of the
Mail1 Register employs data lines B0-B8. (In this case, B9-
B35 are don’t care inputs.)
during the LOW-to-HIGH transition of RS1 selects the endian
methodthatwillbeactiveduringFIFOoperation. BEisadon’t
care input when the bus size selected for Port B is long word.
The endian method is implemented at the completion of
Reset, by the time the Full/Input Ready flag is set HIGH, as
shown in Figure 2.
Only 36-bit long word data is written to or read from the
FIFOmemoryontheIDT723623/723633/723643. Bus-match-
ingoperationsaredoneafterdataisreadfromtheFIFORAM.
Thesebus-matchingoperationsarenotavailablewhentrans-
ferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limit the width of the data
bus that can be used for mail register operations. In this case,
only those byte lanes belonging to the selected word- or byte-
size bus can carry mailbox data. The remaining data outputs
will be indeterminate. The remaining data inputs will be don’t
care inputs. For example, when a word-size bus is selected,
then mailbox data can be transmitted only between A0-A17
and B0-B17. When a byte-size bus is selected, then mailbox
datacanbetransmittedonlybetweenA0-A8andB0-B8. (See
Figures 17 and 18).
Writing data to a mail register sets its corresponding flag
(MBF1 orMBF2)LOW. Attemptedwritestoamailregisterare
ignored while the mail flag is LOW.
Whendataoutputsofaportareactive,thedataonthebus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-
to-HIGHtransitiononCLKBwhenaPortBreadisselectedby
CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size,
36 bits of mailbox data are placed on B0-B35. For an 18-bit
bussize,18bitsofmailboxdataareplacedonB0-B17. (Inthis
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits
of mailbox data are placed on B0-B8. (In this case, B9-B35
are indeterminate.)
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long word incre-
ments. If a long word bus size is implemented, the entire long
wordimmediatelyshiftstotheFIFOoutputregister. Ifbyteorword
size is implemented on Port B, only the first one or two bytes
appearontheselectedportionoftheFIFOoutputregister,withthe
rest of the long word stored in auxiliary registers. In this case,
subsequent FIFO reads output the rest of the long word to the
FIFO output register in the order shown by Figure 2.
When reading data from FIFO in byte or word format, the
unused B0-B35 outputs are LOW.
14
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
A35—A27
A26—A18
A17—A9
A8—A0
BYTE ORDER ON PORT A:
Write to FIFO
A
B
C
D
B35—B27
B26—B18
B17—B9
B8—B0
BE BM SIZE
B
D
A
C
Read from FIFO
X
L
X
(a) LONG WORD SIZE
B35—B27
B35—B27
B26—B18
B17—B9
B8—B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
A
B
H
H
L
B26—B18
B17—B9
B8—B0
C
D
(b) WORD SIZE — BIG-ENDIAN
B35—B27
B35—B27
B26—B18
B17—B9
B8—B0
BE BM SIZE
1st: Read from FIFO
2nd: Read from FIFO
C
D
L
H
L
B26—B18
B17—B9
B8—B0
A
B
(c) WORD SIZE — LITTLE-ENDIAN
B35—B27
B35—B27
B35—B27
B35—B27
B26—B18
B26—B18
B26—B18
B26—B18
B17—B9
B17—B9
B17—B9
B17—B9
B8—B0
BE BM SIZE
A
1st: Read from FIFO
2nd: Read from FIFO
H
H
H
B8—B0
B
B8—B0
C
3rd: Read from FIFO
4th: Read from FIFO
B8—B0
D
(d) BYTE SIZE — BIG-ENDIAN
B35—B27
B35—B27
B26—B18
B17—B9
B8—B0
BE BM SIZE
D
1st: Read from FIFO
L
H
H
B26—B18
B17—B9
B17—B9
B17—B9
B8—B0
C
2nd: Read from FIFO
3rd: Read from FIFO
B35—B27
B35—B27
B26—B18
B26—B18
B8—B0
B
B8—B0
A
4th: Read from FIFO
(e) BYTE SIZE — LITTLE-ENDIAN
3269 drw 03
Figure 2. Bus sizing
15
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
1
2
CLKA
CLKB
tRSTS
t
RSTH
(3)
tBEH
tBES
t
FWS
B
BE
0,1
FWFT
t
SPMS
tSPMH
tFSH
tFSS
FS1,FS0
t
WFF
t
WFF
/IR
(2)
REF
t
/OR
tRSF
tRSF
tRSF
,
3269 drw 04
NOTES:
1. PRS must be HIGH during Reset.
2. If BE/FWFTis HIGH, then EF/OR will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
3. RS2 only for reset after power up.
Figure 3. Reset Loading X and Y with a Preset Value of Eight
CLKA
CLKB
tRSTS
tRSTH
t
WFF
t
WFF
/IR
(2)
t
REF
/OR
tRSF
tRSF
tRSF
,
3269 drw 05
NOTES
1. RS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
Figure 4. Partial Reset (IDT Standard and FWFT Modes)
16
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA
2
1
4
tFSS
tFSH
tFSS
tFSH
0,0
FS1,FS0
/IR
t
WFF
tENS2
t
ENH
ENA
t
DH
tDS
A0-A35
Dummy
Word
Dummy
Word
Offset
(X)
Offset
(Y)
First Word to FIFO1
3269 drw 06
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 5. Parallel programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset. (IDT Standard and Modes)
CLKA
4
t
t
FSS
FSS
t
FSH
t
WFF
/IR
t
SENS
t
SENH
SDH
t
SENS
t
SENH
SDH
t
SPH
FS
t
SDS
t
t
t
SDS
FS0/SD(2)
Offset
(Y) MSB
Offset
(X) LSB
3269 drw 07
NOTES:
1. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
2. Programmable offsets are written serially to the SD input in the order AF offset (Y) and AE offset (X).
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
17
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
t
CLK
t
CLKH
t
CLKL
CLKA
/IRA
HIGH
tENS1
t
ENH
t
ENS1
t
ENH
ENH
ENH
W
t
ENS2
t
MBA
ENA
tENS2
tENS2
tENH
t
tENS2
t
ENH
tDS
t
DH
(1)
(1)
A0-A35
No Operation
W1
W2
3269 drw 08
NOTE:
1. Written to FIFO.
Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
t
CLKL
CLKB
/OR
HIGH
/RB
MBB
tENS2
tENS2
t
ENH
t
ENH
tENH
tENS2
ENB
No Operation
W2(1)
tDIS
tMDV
tA
tA
tEN
W1(1)
B0-B35
Previous Data
(Standard Mode)
tMDV
t
DIS
OR
tA
tA
(1)
t
EN
B0-B35
W2(1)
W1
W3(1)
(FWFT Mode)
3269 drw 09
NOTE:
1. Data read from the FIFO
DATA SIZE TABLE FOR FIFO LONG-WORD READS
SIZE MODE(1)
DATA WRITTEN TO FIFO
DATA READ FROM FIFO
(SELECT AT RESET)
BM
SIZE
BE
A35-A27
A26-A18 A17-A9 A8-A0 B35-B27
B26-B18
B17-B9
B8-B0
L
X
X
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Reset: MB and SIZE must be static throughout device operation.
Figure 8. Port B Long-Word Read Cycle (IDT Standard and FWFT Modes)
18
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
CLKB
/OR
HIGH
/RB
MBB
tENS2
t
ENH
ENB
No Operation
Read 2
t
DIS
t
MDV
t
A
t
A
B0-B17
t
EN
(Standard Mode)
Previous Data
Read 1
Read 2
t
DIS
t
MDV
OR
t
A
tA
tEN
B0-B17
(FWFT Mode)
Read 1
Read 3
3269 drw 10
NOTE:
1. Unused word B18-B35 contains all zeros for word-size reads
DATA SIZE TABLE FOR WORD READS
SIZE MODE (1)
DATA WRITTEN TO FIFO1
READ
NO.
DATA READ FROM FIFO
BM
SIZE
BE
A35-A27
A26-A18
A17-A9
A9-A0
B17-B9
B8-B0
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 9. Port B Word Read Cycle Timing (IDT Standard and FWFT Modes)
19
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
CLKB
/OR HIGH
/RB
MBB
t
ENS2
t
t
ENH
A
ENB
No Operation
t
MDV
t
DIS
t
A
tA
t
A
t
EN
B0-B8
(Standard Mode)
Read 1
Read 2
Read 3
Read 4
Read 5
Previous Data
t
DIS
OR
t
A
t
MDV
t
A
t
A
tA
t
EN
B0-B8
(FWFT Mode)
Read 1
Read 2
Read 3
Read 4
3269 drw 11
NOTE:
1. Unused bytes B9-B17, B18-B26, and B27-B35 contain all zeros for byte-size reads.
DATA SIZE TABLE FOR BYTE READS
SIZE MODE(1)
SIZE
DATA WRITTEN TO FIFO
READ
NO.
DATA READ FROM FIFO
B8-B0
BM
BE
A35-A27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
H
H
H
H
A
B
C
D
D
1
2
3
4
D
C
B
A
H
L
A
B
C
NOTE:
1. BE is selected at Reset: BM and SIZE must be static throughout device operation.
Figure 10. Port B Byte Read Cycle Timing (IDT Standard and FWFT Modes)
20
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
HIGH
t
ENS2
t
t
ENH
ENH
MBA
ENA
tENS2
IR
HIGH
tDS
tDH
A0-A35
W1
t
t
SKEW1
CLKtCLKL
(1)
t
CLKH
CLKB
OR
1
2
3
t
REF
tREF
FIFO Empty
LOW
/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0-B35
Old Data in FIFO Output Register
W1
3269 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, OR is set LOW by the last word or byte read from the FIFO, respectively.
Figure 11. OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode)
21
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
t
CLK
t
CLKL
t
CLKH
CLKA
LOW
HIGH
tENS2
t
ENH
MBA
ENA
tENS2
t
ENH
HIGH
tDS
t
DH
W1
A0-A35
CLKB
t
CLK
(1)
SKEW1
t
CLKH
t
t
CLKL
1
2
tREF
tREF
FIFO Empty
LOW
/RB
HIGH
LOW
MBB
tENS2
t
ENH
ENB
tA
B0-B35
W1
3269 drw 13
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
Figure 12. EF Flag Timing and First Data Read when FIFO is Empty (IDT Standard Mode)
22
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
t
CLK
t
CLKH
tCLKL
CLKB
LOW
/RB
MBB
HIGH
LOW
tENS2
tENH
ENB
OR
HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
t
CLK
(1)
t
SKEW1
t
CLKH
tCLKL
CLKA
IR
1
2
tWFF
tWFF
FIFO Full
LOW
HIGH
t
ENS2
t
t
ENH
MBA
tENS2
ENH
ENA
tDS
t
DH
A0-A35
To FIFO
3269 drw 14
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
Figure 13. IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode)
23
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
HIGH
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0-B35
CLKA
(1)
tSKEW1
tCLK
tCLKH
tCLKL
1
2
tWFF
tWFF
FIFO Full
LOW
HIGH
tENH
tENS2
tENS2
tDS
MBA
tENH
tDH
ENA
A0-A35
To FIFO
3269 drw 15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFto transition HIGH in the next CLKA cycle. If the time between
the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14. FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
CLKA
tENS2
t
ENH
ENA
(1)
t
SKEW2
CLKB
1
2
tPAE
tPAE
X Word in FIFO1
(X1+1) Words in FIFO1
ENS2
t
t
ENH
ENB
3269 drw 16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
3. If Port B size is word or byte, AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
24
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
CLKA
1
2
(1)
SKEW2
tENS2
tENH
t
ENA
tPAF
tPAF
(D-Y) Words in FIFO
[D-(Y+1)] Words in FIFO
CLKA
tENS2
t
ENH
ENB
3269 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723623, 512 for the IDT723633, 1,024 for the IDT723643.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 16. Timing for AF when the FIFO is Almost-Full (IDT Standard and FWFT Modes).
CLKA
tENS1
t
ENH
t
ENH
t
ENS1
ENS2
W
t
t
ENH
MBA
tENS2
t
ENH
ENA
A0-A35
CLKB
t
DH
t
DS
W1
tPMF
tPMF
/RB
MBB
ENB
t
ENH
tENS2
tMDV
tEN
tDIS
tPMR
B0-B35
FIFO Output Register
W1 (Remains valid in Mail1 Register after read)
3269 drw 18
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 Register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17
will have valid data (B18-B35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8
(A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B35 will be indeterminate).
Figure 17. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
25
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
CLKB
t
ENH
tENS1
tENS1
t
ENH
/RB
MBB
ENB
t
ENS2
t
ENH
tENS2
t
ENH
t
DH
tDS
W1
B0-B35
CLKA
t
PMF
t
PMF
W
MBA
ENA
t
ENH
tENS2
tEN
tPMR
tDIS
tMDV
W1 (Remains valid in Mail2 Register after read)
FIFO Output Register
A0-A35
3269 drw 19
NOTE:
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will
have valid data (A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are
don't care inputs). In this second case, A0-A8 will have valid data (A9-A35 will be indeterminate).
Figure 18. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
READ CLOCK (CLKB)
CLKB
/OR
CLKA
•
CHIP SELECT
WRITE SELECT (W/
)
)
CHIP SELECT
EMPTY FLAG/
)
ENA
/IR
V
CC
OUTPUT READY /OR)
ENB
WRITE ENABLE (ENA)
ALMOST-FULL FLAG
READ ENABLE (ENB)
)
V
)
CC
READ SELECT ( /RB)
ALMOST-EMPTY FLAG
IDT
IDT
723623
723633
723643
723623
723633
723643
A0-A35
n
MBB
MBA
DATA IN (Dn)
A
0
-A35
n
B
0
-B35
Qn
/RB
B
0
-B35
n
FULL FLAG/
INPUT READY /IR)
MBA
DATA OUT (Qn)
Dn
V
CC
VCC
W
MBB
3269 drw 20
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. The amount of time it takes for EF/OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO’s outputs) after a word has been
written to the first FIFO is the sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the
expansion and TRCLK is the CLKB period.
4. The amount of time is takes for FF/IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for
each individual FIFO: (N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 19. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
26
IDT723623/723633/723643 Bus-Matching SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5 V
Ω
1.1 k
From Output
Under Test
30 pF(1)
Ω
680
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
GND
1.5 V
1.5 V
GND
t
S
th
t
W
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
t
PLZ
3 V
GND
≈
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
V
OL
t
PD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
≈
OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3269 drw 21
NOTE:
1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms.
ORDERING INFORMATION
IDT
X
XX
X
X
XXXXXX
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
PF
Thin Quad Flat Pack (TQFP, PK128-1)
12
15
20
30
Clock Cycle Time (tCLK
)
Commercial Only
Speed in Nanoseconds
L
Low Power
723623 256 x 36 x 2 Synchronous FIFO with Bus-Matching
723633 512 x 36 x 2 Synchronous FIFO with Bus-Matching
723643 1,024 x 36 x 2 Synchronous FIFO with Bus-Matching
3269 drw 22
NOTE:
1. Industrial temperature range is available by special order.
27
June 17, 1997
IDT 36-BIT FIFO DATA SHEET ERRATA
CONCERNING THE MASTER RESET FUNCTION
(Affects the IDT723622/723632/723642, the IDT723623/723633/723643, the
IDT723624/723634/723644 and the IDT723626/723636/723646)
IDT has recently identified some omissions and errors regarding the descriptions of the master and partial reset functions
in the following 36-bit FIFO data sheets (all versions dated December 1996 or earlier): the IDT723622/723632/723642, the
IDT723623/723633/723643, the IDT723624/723634/723644 and the IDT723626/723636/723646. The corrections and
clarifications described will be included in new, corrected versions of the data sheets.
THE 723622/723632/723642, 723624/723634/723644 and 723626/723636/723646
Data sheets for these FIFOs do not explicitly state the necessity, right after device power up, of performing a Master Reset
operationbyprovidingaLOWpulseto bothMasterResetinputs, MRS1and MRS2(RST1and RST2 ontheIDT723622/723632/
723642) simultaneously. Afterwards, these inputs can be used independently: MRS1 for a master reset of FIFO1 and MRS2
for a master reset of FIFO2.
THE 723623/723633/723643
The TQFP Pin Configuration in the December 1996 data sheet has two incorrectly labeled pins. Pin 119, previously known
as MRS, has now been renamed RS1. Previously identified as VCC, pin 114 is now called RS2.
To initiate a master reset operation right after device power up, a LOW pulse must be provided to both reset inputs, RS1
and RS2 simultaneously. Afterwards, these inputs can be used independently: a LOW on RS1 for a master reset of the FIFO
together with the Mail1 Register, a LOW on RS2 for a reset of the Mail2 Register (forcing the Mailbox Flag MBF2 HIGH).
In the case of the partial reset operation, a LOW on PRS performs a partial reset for the FIFO together with the Mail1
Register. Once again, a LOW on RS2 resets the Mail2 Register.
Designers who may have already begun designing according to the December 1996 data sheet should consider the
following recommendations where appropriate:
1. If an existing design uses neither the Mail2 Register (associated with the MBF2 and MBB lines) nor the AEB flag, no
changestothedesignareneeded. EvenifthisdesignoriginallyfollowedadatasheetdatedDecember1996orearlier,
the FIFO will operate properly.
2. If the design does use either the Mail2 Register or the AEB flag, then that design must be adapted to meet the new
specification changes.
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